19-2543; Rev 0; 7/02
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
General Description Features MAX9317/MAX9317A/MAX9317B/MAX9317C
The MAX9317/MAX9317A/MAX9317B/MAX9317C low- o Guaranteed 1.0GHz Operating Frequency
skew, dual 1-to-5 differential drivers are designed for o 145ps (max) Part-to-Part Skew
clock and data distribution. The differential input is o 5ps Output-to-Output Skew
reproduced at five LVDS outputs with a low output-to- o 330ps Propagation Delay from CLK_ to Q_
output skew of 5ps. o 2.375V to 2.625V Operation (MAX9317/MAX9317A)
o 3.0V to 3.6V Operation (MAX9317B/MAX9317C)
The MAX9317/MAX9317A are designed for low-voltage o ESD Protection: 2kV (Human Body Model)
operation from a 2.375V to 2.625V power supply for use o Internal 50 Input Termination Resistors
in 2.5V systems. The MAX9317B/MAX9317C operate
from a 3.0V to 3.6V power supply for use in 3.3V sys- (MAX9317A/MAX9317C)
tems. The MAX9317A/MAX9317C feature 50 input ter-
mination resistors to reduce component count. Ordering Information
The MAX9317 family is available in 32-pin 7mm 7mm PA RT TEMP RANGE PIN- NOMINAL
TQFP and space-saving 5mm 5mm QFN packages PA CK A G E SU PPL Y
and operate across the extended temperature range of VO LT A G E
-40C to +85C. The MAX9317A is pin compatible with MAX9317ETJ* -40C to +85C 32 Thin QFN
ON Semiconductor's MC100EP210S. MAX9317ECJ -40C to +85C 32 TQFP ( V)
MAX9317AETJ* -40C to +85C 32 Thin QFN 2.5
Applications MAX9317AECJ -40C to +85C 32 TQFP 2.5
MAX9317BETJ* -40C to +85C 32 Thin QFN 2.5
Precision Clock Distribution MAX9317BECJ -40C to +85C 32 TQFP 2.5
MAX9317CETJ* -40C to +85C 32 Thin QFN 3.3
Low-Jitter Data Repeaters MAX9317CECJ -40C to +85C 32 TQFP 3.3
3.3
Data and Clock Drivers and Buffers *Future product--contact factory for availability. 3.3
Central-Office Backplane Clock Distribution
DSLAM Backplanes
Base Stations
ATE
Pin Configurations appear at end of data sheet.
Functional Diagram
9, 16 31 QA0
VCC 25, 32 30 QA0
29 QA1
28 QA1
27 QA2
26 QA2
VTA 2 MAX9317
MAX9317A
RIN RIN MAX9317B
MAX9317C
50 50 24 QA3
23 QA3
CLKA 3 22 QA4
CLKA 4 21 QA4
CLKB 6
CLKB 7 20 QB0
19 QB0
RIN RIN 18 QB1
17 QB1
50 50
VTB 5
GND 1, 8
MAX9317A/MAX9317C ONLY. QB4 10
QB4 11
QB3 12
QB3 13
QB2 14
QB2 15
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
MAX9317/MAX9317A/MAX9317B/MAX9317C ABSOLUTE MAXIMUM RATINGS Junction-to-Ambient Thermal Resistance in Still Air
32-Pin, 7mm 7mm TQFP......................................+48.4C/W
VCC to GND ...........................................................-0.3V to +4.1V 32-Pin, 5mm 5mm QFN ..........................................+47C/W
Input Pins to GND.......................................-0.3V to (VCC + 0.3V)
Differential Input Voltage .............VCC or 3.0V, whichever is less Junction-to-Case Thermal Resistance
Continuous Output Current .................................................28mA 32-Pin, 7mm 7mm TQFP.........................................+12C/W
Surge Output Current..........................................................50mA 32-Pin, 5mm 5mm QFN ............................................+2C/W
Continuous Power Dissipation (TA = +70C)
Operating Temperature Range ...........................-40C to +85C
32-Pin, 7mm 7mm TQFP Junction Temperature ......................................................+150C
(derate 20.7mW/C above +70C) .................................1.65W Storage Temperature Range .............................-65C to +150C
32-Pin 5mm 5mm QFN ESD Protection
(derate 21.3mW/C above +70C) ...................................1.7W
Human Body Model (CLK_, CLK_, Q_, Q_, VT_) .............2kV
Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A), VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded 100 1%
between Q_ and Q_, unless otherwise noted. Typical values are at VCC = 2.5V (MAX9317/MAX9317A), VCC = 3.3V
(MAX9317B/MAX9317C), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER SYMBOL CONDITIONS -40C +25C +85C UNITS
INPUTS (CLK_, CLK_)
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Differential Input VIHD Figure 1 1.2 VCC 1.2 VCC 1.2 VCC V
High Voltage
Differential Input VILD Figure 1 0 VCC 0 VCC 0 VCC V
Low Voltage - 0.1 - 0.1 - 0.1
MAX9317/ 0.1 VCC 0.1 VCC 0.1 VCC
MAX9317A 3.0 0.1 3.0 0.1 V
Differential Input VIHD -
Voltage VID VILD MAX9317B/ 3.0
MAX9317C
0.1
CLK_, or CLK_ =
Input Current IIH, IIL VIHD or VILD, -60 +60 -60 +60 -60 +60 A
MAX9317/MAX9317B
Input Termination RIN MAX9317A/MAX9317C, 43 50 57 43 50 57 43 50 57
Resistance Figure 2 (Note 4)
OUTPUTS (Q_, Q_)
Output High VOH Figure 1 1.6 1.6 1.6 V
Voltage
Output Low VOL Figure 1 0.9 0.9 0.9 V
Voltage
2 _______________________________________________________________________________________
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
DC ELECTRICAL CHARACTERISTICS (continued) MAX9317/MAX9317A/MAX9317B/MAX9317C
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A), VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded 100 1%
between Q_ and Q_, unless otherwise noted. Typical values are at VCC = 2.5V (MAX9317/MAX9317A), VCC = 3.3V
(MAX9317B/MAX9317C), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER SYMBOL CONDITIONS -40C +25C +85C UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Differential VOD Figure 1 250 350 450 250 350 450 250 350 450 mV
Output Voltage
Change in VOD VOD 7 50 6 50 6 50 mV
Between
Complementary
Output States
Output Offset VOS 1.125 1.25 1.375 1.125 1.25 1.375 1.125 1.25 1.375 V
Voltage
Change in VOS VOS 25 25 25 mV
Between
Complementary Q_ shorted to Q_ 12 12 12
Output States Q_ or Q_ shorted to
IOSC GND 28 28 28 mA
Output Short-
Circuit Current
POWER SUPPLY
Power-Supply ICC MAX9317/9317A 69 107 75 107 80 107
Current (Note 5) 75 107 81 107 mA
MAX9317B/9317C
86 107
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A) or VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded with 100 1%,
between Q_ and Q_, fIN 1.0GHz, input transition time = 125ps (20% to 80%), VIHD - VILD = 0.15V to VCC, unless otherwise noted.
Typical values are at VCC = 2.5V (MAX9317/MAX9317A), VCC = 3.3V (MAX9317B/MAX9317C), fIN = 1.0GHz, VIHD = VCC - 1.0V,
VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1 and 4)
PARAMETER SYMBOL CONDITIONS -40C +25C +85C UNITS
Propagation MIN TYP MAX MIN TYP MAX MIN TYP MAX
Delay CLK_,
CLK_ to Q_, Q_ tPHL Figure 1 250 310 600 250 330 600 250 335 600 ps
tPLH
Output-to-Output tSKEW1 (Note 6) 9 55 5 45 4 25 ps
Skew tSKEW2 145 145
(Note 7) 145 ps
Part-to-Part Skew tRJ fIN = 1.0GHz, clock 0.8 2.0 0.8 2.0
pattern (Note 8) 0.8 2.0 ps(RMS)
Added Random
Jitter
Added tDJ fIN = 1.0GHz, 223 - 1 80 105 80 105 80 105 ps(P-P)
Deterministic Jitter PRBS pattern (Note 8)
Operating fMAX VOD 250mV 1.0 1.0 1.0 GHz
Frequency
_______________________________________________________________________________________ 3
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
AC ELECTRICAL CHARACTERISTICS (continued)
MAX9317/MAX9317A/MAX9317B/MAX9317C
SUPPLY CURRENT (mA)(VCC = 2.375V to 2.625V (MAX9317/MAX9317A) or VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded with 100 1%,
CLK-TO-Q PROPAGATION DELAY (ps)between Q_ and Q_, fIN 1.0GHz, input transition time = 125ps (20% to 80%), VIHD - VILD = 0.15V to VCC, unless otherwise noted.
Typical values are at VCC = 2.5V (MAX9317/MAX9317A), VCC = 3.3V (MAX9317B/MAX9317C), fIN = 1.0GHz, VIHD = VCC - 1.0V,
VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1 and 4)
PARAMETER SYMBOL CONDITIONS -40C +25C +85C UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Differential tR/tF 20% to 80%, Figure 1 140 200 300 140 205 300 140 205 300 ps
Output Rise/Fall
Time
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at +25C. DC limits are guaranteed by design and characterization over the full oper-
ating temperature range.
Note 4: Guaranteed by design and characterization, and are not production tested. Limits are set to 6 sigma.
Note 5: All outputs loaded with 100 differential, all inputs biased differential high or low except VT_.
Note 6: Measured between outputs of the same device at the signal crossing points for a same-edge transition.
Note 7: Measured between outputs on different devices for identical transitions and VCC levels.
Note 8: Device jitter added to the input signal.
Typical Operating Characteristics
(MAX9317, VCC = 2.5V, all outputs loaded with 100 1%, between Q_ and Q_, fIN = 1.0GHz, input transition time = 125ps (20% to
80%), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE OUTPUT AMPLITUDE (VOH - VOL) OUTPUT RISE/FALL TIME
vs. CLK_ FREQUENCY vs. TEMPERATURE
90
INPUTS OPEN, OUTPUTS TERMINATED 400 230
WITH 100 DIFFERENTIAL
300 220
85 MAX9317 toc01 MAX9317 toc03
80 OUTPUT AMPLITUDE (mV) 210 FALL TIME
MAX9317 toc02
200
OUTPUT RISE/FALL TIME (ps)
75 200
RISE TIME
70 100 190
65 0 180
-40 -15 10 35 60 85 0 0.5 1.0 1.5 2.0 -40 -15 10 35 60 85
TEMPERATURE (C) CLK_ FREQUENCY (GHz) TEMPERATURE (C)
CLK-TO-Q PROPAGATION DELAY CLK-TO-Q PROPAGATION DELAY vs. HIGH
vs. TEMPERATURE
VOLTAGE OF DIFFERENTIAL INPUT (VIHD)
340
324.0
MAX9317 toc04
335
CLK-TO-Q PROPAGATION DELAY (ps)
MAX9317 toc05323.5
330
325 323.0 tPHL
tPLH tPLH
320
322.5
315 tPHL
310 322.0
-40 -15 10 35 60 85 1.2 1.5 1.8 2.1 2.4
4 ___________________________T_EM_P_E_RA_T_U_RE_(_C_)______________________H_IG_H_V_O_L_TA_G_E_O_F _DI_FF_E_RE_N_TI_A_L I_N_PU_T_(_V)_____
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
Pin Description MAX9317/MAX9317A/MAX9317B/MAX9317C
NAME
PIN MAX9317 MAX9317A FUNCTION
MAX9317B MAX9317C
1, 8 Ground
GND GND No Connection. Connect this pin to ground or leave floating.
2 CLKA Input Termination Voltage. This pin is connected to CLKA and CLKA through 50
N.C. -- termination resistors. Connect this pin to VCC - 2V for an LVPECL input signal on CLKA or
3 leave floating for an LVDS input signal.
4 -- VTA Noninverting Differential Clock Input A
Inverting Differential Clock Input A
5 CLKA CLKA No Connection. Connect this pin to ground or leave floating.
CLKA CLKA CLKB Input Termination Voltage. This pin is connected to CLKB and CLKB through 50
6 N.C. termination resistors. Connect this pin to VCC - 2V for an LVPECL input signal on CLKB or
7 -- leave floating for an LVDS input signal.
9, 16, Noninverting Differential Clock Input B
25, 32 -- VTB Inverting Differential Clock Input B
10 Positive Supply Voltage. Bypass each VCC pin to ground with 0.1F and 0.01F ceramic
11 CLKB CLKB capacitors. Place the capacitors as close to the device as possible with the 0.01F
12 CLKB CLKB capacitor closest to the device.
13 CLKB Inverting Differential Output 4. Terminate with 100 to QB4.
14 VCC VCC CLKB Noninverting Differential Output 4. Terminate with 100 to QB4.
15 CLKB Inverting Differential Output 3. Terminate with 100 to QB3.
17 QB4 QB4 CLKB Noninverting Differential Output 3. Terminate with 100 to QB3.
18 QB4 QB4 CLKB Inverting Differential Output 2. Terminate with 100 to QB2.
19 QB3 QB3 CLKB Noninverting Differential Output 2. Terminate with 100 to QB2.
20 QB3 QB3 CLKB Inverting Differential Output 1. Terminate with 100 to QB1.
21 QB2 QB2 CLKB Noninverting Differential Output 1. Terminate with 100 to QB1.
22 QB2 QB2 CLKB Inverting Differential Output 0. Terminate with 100 to QB0.
23 QB1 QB1 CLKB Noninverting Differential Output 0. Terminate with 100 to QB0.
24 QB1 QB1 CLKA Inverting Differential Output 4. Terminate with 100 to QA4.
26 QB0 QB0 CLKA Noninverting Differential Output 4. Terminate with 100 to QA4.
27 QB0 QB0 CLKA Inverting Differential Output 3. Terminate with 100 to QA3.
28 QA4 QA4 CLKA Noninverting Differential Output 3. Terminate with 100 to QA3.
29 QA4 QA4 CLKA Inverting Differential Output 2. Terminate with 100 to QA2.
30 QA3 QA3 CLKA Noninverting Differential Output 2. Terminate with 100 to QA2.
31 QA3 QA3 CLKA Inverting Differential Output 1. Terminate with 100 to QA1.
-- QA2 QA2 CLKA Noninverting Differential Output 1. Terminate with 100 to QA1.
QA2 QA2 CLKA Inverting Differential Output 0. Terminate with 100 to QA0.
QA1 QA1 CLKA Noninverting Differential Output 0. Terminate with 100 to QA0.
QA1 QA1 Exposed Pad. QFN package only. Internally connected to ground.
QA0 QA0
QA0 QA0
EP EP
_______________________________________________________________________________________ 5
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
MAX9317/MAX9317A/MAX9317B/MAX9317C CLK VIHD
VIHD - VILD
CLK VILD
tPLH tPHL
Q_ VOH
VOD
Q_ VOL
80% 80%
Q_ - Q_ DIFFERENTIAL 0V
OUTPUT (DIFFERENTIAL)
WAVEFORM
20% 20%
tR tF
Figure 1. MAX9317 Timing Diagram CLK_
Detailed Description CLK_
The MAX9317 family of low-skew, 1-to-5 dual differen- LVPECL RIN RIN
tial drivers are designed for clock or data distribution. DRIVER 50 50
Two independent 1-to-5 splitters accept a differential VT_
input signal and reproduce it on five separate differen- MAX9317A
tial LVDS outputs. The output drivers are guaranteed to VCC - MAX9317C
operate at frequencies up to 1.0GHz with the LVDS out- 2.0V
put levels conforming to the EIA/TIA-644 standard.
(a) MAX9317A/MAX9317C CONFIGURED FOR LVPECL INPUT SIGNALS.
The MAX9317/MAX9317A operate from a 2.375V to
2.625V power supply for use in 2.5V systems. The LVDS CLK_ MAX9317A
MAX9317B/MAX9317C operate from a 3.0V to 3.6V DRIVER MAX9317C
supply for 3.3V systems. RIN
50
Differential LVPECL and LVDS Input VT_
The MAX9317 family has two input differential pairs:
CLKA and CLKA, and CLKB and CLKB. Each differen- RIN
tial input pair can be configured or terminated indepen- 50
dently. The inputs are designed to be driven by either CLK_
LVPECL or LVDS signals with a maximum differential
voltage of VCC or 3.0V, whichever is less. (b) MAX9317A/MAX9317C CONFIGURED FOR LVDS INPUT SIGNALS.
The MAX9317A/MAX9317C reduce external component Figure 2. MAX9317A/MAX9317C Input Terminations
count by having the input 50 termination resistors on
chip. Configure the MAX9317A/MAX9317C to receive
LVPECL signals by connecting VT_ to VCC - 2V (Figure
2(a)). Leaving the VT_ input floating configures the
6 _______________________________________________________________________________________
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
respective input with a differential 100 termination to Circuit Board Traces MAX9317/MAX9317A/MAX9317B/MAX9317C
receive LVDS signals (Figure 2(b)). Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals. Use
The MAX9317/MAX9317B accept LVPECL if the inputs 50 traces for CLK_, CLK_, Q_, and Q_. Maintaining
are externally terminated with 50 resistors from CLKA integrity is accomplished in part by reducing signal
and CLKA or CLKB and CLKB to VCC - 2V. Alternatively, reflections and skew, and increasing common-mode
if the inputs are differentially terminated with 100, they noise immunity by keeping the differential traces close
accept an LVDS input signal. together.
The LVDS input signal must adhere to the specifications Signal reflections are caused by discontinuities in the
given in the Electrical Characteristics table. Note that the 50 characteristic impedance of the traces. Avoid dis-
signal must be at least 1.2V to be a valid logic HIGH. continuities by maintaining the distance between differ-
ential traces, and not using sharp corners or vias.
Applications Information Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
Output Termination is accomplished by matching the electrical length of
Terminate the outputs with 100 across each differen- the differential traces.
tial pair (Q_ to Q_). Ensure that output currents do not
exceed the current limits as specified in the Absolute Chip Information
Maximum Ratings table. Under all operating conditions,
observe the device's total thermal limits. TRANSISTOR COUNT: 1119
Power-Supply Bypassing PROCESS: Bipolar
Bypass each VCC pin to ground with high-frequency sur-
face-mount ceramic 0.1F and 0.01F capacitors in par-
allel and as close to the device as possible, with the
0.01F capacitor closest to the device. Use multiple par-
allel vias to minimize parasitic inductance and reduce
power-supply bounce with high-current transients.
Pin Configurations
TOP VIEW VCC QA0 QA0 QA1 QA1 QA2 QA2 VCC TOP VIEW VCC QA0 QA0 QA1 QA1 QA2 QA2 VCC
32 31 30 29 28 27 26 25 32 31 30 29 28 27 26 25
GND 1 MAX9317 24 QA3 GND 1 MAX9317 24 QA3
N.C. (VTA) 2 MAX9317A 23 QA3 N.C. (VTA) 2 MAX9317A 23 QA3
MAX9317B 22 QA4 MAX9317B 22 QA4
CLKA 3 MAX9317C 21 QA4 CLKA 3 MAX9317C 21 QA4
CLKA 4 20 QB0 CLKA 4 20 QB0
N.C. (VTB) 5 19 QB0 N.C. (VTB) 5 **EXPOSED PADDLE 19 QB0
CLKB 6 18 QB1 CLKB 6 18 QB1
CLKB 7 17 QB1 CLKB 7 17 QB1
GND 8 GND 8
9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16
VCC QB4 QB4 QB3 QB3 QB2 QB2 VCC VCC QB4 QB4 QB3 QB3 QB2 QB2 VCC
TQFP (7mm x 7mm) QFN-EP**
( ) MAX9317A/MAX9317C. **EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO VEE.
_______________________________________________________________________________________ 7
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX9317/MAX9317A/MAX9317B/MAX9317C
QFN THIN 5x5x0.8 .EPS0.15 C AD2
0.15 C B
D CL b 0.10 M C A B
D/2 E/2
E D2/2
PIN # 1 k
I.D.
PIN # 1 I.D.
0.35x45
(NE-1) X e E2/2
CL E2
k
L
DETAIL A e
(ND-1) X e
CL CL
L L
e e
0.10 C
A
0.08 C
C A1 A3
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV. 1
21-0140 C2
8 _______________________________________________________________________________________
Dual 1:5 Differential Clock Drivers with LVPECL MAX9317/MAX9317A/MAX9317B/MAX9317C
Inputs and LVDS Outputs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS EXPOSED PAD VARIATIONS
NOTES: PROPRIETARY INFORMATION
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. TITLE:
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 PACKAGE OUTLINE
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
APPROVAL DOCUMENT CONTROL NO. REV. 2
21-0140 C2
_______________________________________________________________________________________ 9
Dual 1:5 Differential Clock Drivers with LVPECL
Inputs and LVDS Outputs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX9317/MAX9317A/MAX9317B/MAX9317C
32L/48L,TQFP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
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