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KESTX01MPAD

器件型号:KESTX01MPAD
厂商名称:Zarlink Semiconductor (Microsemi)
厂商官网:http://www.zarlink.com/
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器件描述

400MHz - 460MHz ASK Transmitter

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This product is obsolete.  
This information is available for your  
convenience only.  
For more information on  
Zarlink’s obsolete products and  
replacement product lists, please visit  
KESTX01  
400MHz - 460MHz ASK Transmitter  
Preliminary Information  
Supersedes September 1996 version, DS4548 - 2.0  
DS3969 - 3.8 August 1998  
The KESTX01 is a single chip ASK (Amplitude Shift Key)  
transmitter IC. It is designed to operate in a variety of low  
power radio applications including keyless entry, general  
domestic and industrial remote control, RF tagging and local  
paging systems.  
The transmitter offers a high level of integration and per-  
formance, which enables the harmonic rejection and funda-  
mental power requirements of the ESTI 300 220, and  
other governing bodies, to be met.  
XTAL1  
VCOTST  
VEE1  
LF  
1.  
41  
XTAL2  
PWRC  
DATA  
OUTB  
OUT  
LF1  
The basic architecture utilises a crystal reference oscilla-  
tor, an integrated frequency multiplying PLL and a power  
output stage. The design is centred around the popular  
TXEN  
VCC  
VCCPA  
VEE2  
7
8
4
33.92MHz operating frequency and particular emphasis has  
MP14  
been placed on low current drain, including a power–down  
feature which greatly increases battery life.  
Figure.1 Pin connections - top view  
ABSOLUTE MAXIMUM RATINGS  
Junction temperature  
Storage temperature  
Supply voltage  
Voltage on any pin  
Notes:  
FEATURES  
-55 to +150°C  
-55 to +150°C  
Low supply Current  
V -0.5 to +8.0V  
EE  
Power down feature  
V -0.5 to V +0.5V  
EE  
CC  
Adjustable output power level  
Low external part count  
1. The voltage on pin OUT and OUTB (open collector outputs)  
can support a higher voltage than this (+14V)  
Fully integrated VCO, PLL and Power Amplifier  
ORDERING INFORMATION  
KESTX01/IG/MPAD (Tape and Reel)  
KESTX01/IG/MPAS (Tubes)  
VCC  
VCC  
TXEN  
PLL POWER SUPPL  
Y
VCCPA  
PWRC  
DATA  
1
64  
PHASE  
DETECTOR  
OUT  
OUT B  
VEE2  
VEE1  
XTAL  
OSCILLATOR  
VCO  
XTAL1 XTAL2  
LF  
LF1 VCOTST  
Figure.2 block diagram  
KESTX01  
ELECTRICAL CHARACTERISTICS Operating conditions  
T amb = –40°C to + 85°C, VCC = 3.5V to 6.5V. These characteristics are guaranteed by either production test or design.  
They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.  
Parameter  
Symbol  
Value  
Typ  
Units  
Conditions  
Min  
3.5  
Max  
6.5  
Power supply voltage  
Ambient temperature  
VCC  
Ta  
V
–40  
+85  
°C  
Electro static discharge 2kV all pins – human body model  
ELECTRICAL CHARACTERISTICS D.C.  
T amb = –40°C to + 85°C, VCC = 3.5V to 6.5V. These characteristics are guaranteed by either production test or design.  
They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.  
Parameter  
Symbol  
CC1  
Value  
Typ  
Units  
Condition  
Min  
Max  
0.7  
Supply current  
I
µA  
V
TXEN  
=0V; V =0V;Ta=25°C  
DATA  
stand by mode  
VCC = 7V  
Supply current  
PLL enable/transmit space  
I
2
1.6  
6.4  
1.6  
6.4  
2.8  
8.5  
4
mA  
mA  
mA  
mA  
I
V
=0 µA; VCC =V  
=LOW; 434MHz  
DATA  
3.5V  
TXEN  
CC  
CC  
CC  
CC  
mod  
Supply current  
PLL enable/transmit mark  
I
I
I
3
4
5
10.1  
5.0  
I
V
=150 µA; VCC =V  
=3.5V  
TXEN  
mod  
=HIGH; 434MHz  
DATA  
Supply current  
PLL enable/transmit space  
3.17  
9.8  
I
V
=0 µA; VCC =V  
=6.5V  
TXEN  
mod  
=LOW; 434MHz  
DATA  
Supply current  
12.5  
I
=150µA; VCC =V  
=6.5V  
TXEN  
mod  
PLL enable/transmit mark  
see note 1  
V
=HIGH; 434MHz  
DATA  
TXEN – transmit enable  
Ven  
3.5  
VCC +0.2  
0.5  
V
V
TXEN – transmit  
disable/stand by  
V
VEE –0.2  
dis  
Input bias current TXEN  
Bias voltage pin PWRC  
Data pin input logic high  
Data pin input logic low  
I
150  
1.5  
µA  
V
TXEN = VCC transmit enable  
=150 A V = 3.5V  
txen  
1.0  
1.20  
I
mod  
CC  
V
0.7VCC  
V
+0.5  
CC  
V
ih  
V
V
–0.5  
EE  
0.3VCC  
V
il  
Data pin input current –  
logic low  
I
–100  
µA  
µA  
VCC = 7V  
VDATA = 2.1V  
inl  
Data pin input current –  
logic high  
I
+100  
VCC = 7V  
VDATA = 4.9V  
inh  
Notes:– 1. The maximum supply current is directly related to Imod and hence the output power level. (Figure 4)  
2
KESTX01  
ELECTRICAL CHARACTERISTICS A.C.  
T amb = –40°C to + 85°C, V = 3.5V to 6.5V. These characteristics are guaranteed by either production test, characterisation  
CC  
or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.  
Parameter  
Symbol  
IF75  
Value  
Typ  
Units  
Conditions  
Min  
1.4  
Max  
2.8  
Output current at  
2.1  
pk–pk  
mA  
I
I
=75µA, F =434MHz  
mod  
mod  
o
fundamental, V =3.5V  
CC  
Output current at  
Fundamental, VCC = 3.5V  
IF150  
2.4  
3.0  
3.8  
4.6  
4.9  
5.6  
pk-pk  
mA  
=150µA, F =434MHz  
o
Output current  
fundamental VCC = 6.5V  
IF150(6V5)  
pk–pk  
mA  
I
=150µA, F =434MHz  
mod  
mod  
o
Output level at 2 x  
fundamental see note 1  
–32  
–11  
dBc  
dBc  
I
=150µA, F =434MHz  
o
(1)  
Output level at 3 x  
I
=150µA, F =434MHz (1)  
mod  
o
fundamental and all other  
spurii see note 1  
Phase detector gain  
PDG  
ER  
4.7  
40  
8
9.5  
µA/rad  
VCC = 3.5V  
Extinction ratio  
see note 2  
dB  
VCO gain  
G
110  
5.0  
MHz/V  
ms  
VCO  
TXEN settling time  
see note 3  
Txe  
SB  
Output sidebands due to  
reference frequency  
see note 4  
–40  
dBc  
I
=150µA, F =434MHz  
mod o  
(1, 4)  
3
0dB rise timeRF envelope  
T30R  
T30F  
380  
430  
434  
ns  
ns  
of Data pulse  
30dB fall timeRF envelope  
of Data pulse  
VCO operating frequency  
400  
460  
MHz  
VCC = 3.5  
Notes:  
1. The spurii are specified relative to the fundamental, measured in a 300KHz resolution bandwidth.  
2. Extinction ratio is defined as the ratio of the output power SPACE to output power MARK measured at the output  
operating fequency.  
3
. Regulatory issues demand that transmission does not take place until the PLL has acquired lock and the VCO is  
operating at its final output frequency. This requirement demands that pin TXEN is set high at least Txe ms prior to the  
transmission of any data. This value is dependent on the PLL loop bandwidth and hence on the value of the external  
loop filter component values. The specification value above is for the loop filter components shown in the applications  
diagram (Figure. 6)  
4. Sidebands on the output due to the PLL reference are a function of the PLL loop bandwidth and the application.  
Reducing the closed loop bandwidth of the PLL loop will aid in reducing the level of the PLL reference spurii.  
3
KESTX01  
PIN LISTING  
Signal  
LF1  
Description  
Signal  
XTAL1  
XTAL2  
DATA  
TXEN  
OUT  
Description  
VCO control input  
Output power control  
Power amplifier positive supply  
Power amplifier ground  
PLL ground  
Crystal oscillator  
PWRC  
VCCPA  
VEE2  
Crystal oscillator  
Input data  
Transmit enable/stand by  
Power amplifier output/antenna interface  
Power amplifier output/antenna interface  
VEE1  
VCC  
Positive supply  
OUTB  
(complementary output)  
VCOTST  
VCO test control input  
LF  
Phase detector output  
FUNCTION  
Output stage (PA)  
The input signal at pin DATA produces amplitude shift key  
When the IC is enabled (TXEN high) a phase locked loop  
locks the output of the VCO to a multiple of a crystal defined  
reference input. The output of the VCO operates at the final  
output frequency and is the input to a power amplifier stage.  
The power amplifier directly drives the antenna.  
(ASK) modulation of the VCO output. This is achieved by  
on–off keying of the bias current in the output power amplifier  
stage. The output of the PA is a balanced output (pin OUT and  
OUTB) and is current source driven (open collector outputs).  
The outputs of which should be D.C. referenced to a positive  
supply voltage (anticipated to be VCC in most applications).  
The current source outputs can drive a PCB antenna directly  
(Figure 6) or if a higher output power is required on limited  
supply headroom via a simple impedance transforming net-  
work. A balanced output stage is used as it automatically  
suppresses the even order harmonics of the fundamental. In  
order to obtain the benefits of this output stage it is essential  
to use a balanced antenna.  
Phase locked loop  
Dividers  
A divide by 64 prescaler is present in the PLL feedback  
loop. The final output frequency is then Fo = 64xFref.  
Phase detector  
The phase detector used is a phase frequency detector  
(PFD) with a current (charge pump) output. This phase  
detectorhasatriangularcharacteristicforaninputphaseerror  
in the range –2π <θe < 2π. The charge pump provides an  
output current in the range ± 50µA and hence gives a phase  
detector gain of (50/2π ) µA/rad (≈8µA/rad).  
The advantage of the PFD over a pure phase detector is  
that it is also a frequency discriminator and will always lock the  
loop irrespective of the initial frequency offset. The PLL loop  
characteristics such as lock–up time, capture range, loop  
bandwidth and VCO reference sideband suppression are  
controlled by the external loop filter.  
Power up  
In the intended application, it is expected that the  
transmitter will spend a large proportion of time in ‘‘stand by”  
not transmitting data. To maximise battery life it is important  
that very little quiescent current is taken in this mode.  
The ‘‘stand by mode” is selected by setting pin TXEN low  
and similarly the transmitter is enabled by setting TXEN high.  
To minimize stand–by current TXEN is used to bias an on–  
chip npn transistor connected in a common collector  
configuration (Figure 3 below). This transistor is used to  
provide the supply to large portions of the IC. Collapsing the  
supply when TXEN is set low results in a very low stand by  
current. The voltage on TXEN should not exceed VCC by more  
than 0.2Volts.  
For certain applications spurious sidebands at the  
reference frequency must be adequately suppressed and a  
3rd order loop is recommended.  
VCO  
From an application standpoint the TXEN pin must be able  
to source the bias current for the input transistor and should  
also be decoupled if possible to prevent high frequency noise  
directly coupling into the IC power supply. The value of the  
decoupling capacitors and the drive capability of the TXEN  
source will affect power up delay. Since TXEN enables the  
PLL it is therefore essential that it is set high prior to any data  
transmission and that it remains high during the  
transmission.Thereforethreedifferentpowerdrainmodesare  
possible  
To minimize external component cost,s the VCO is fully  
integrated. The frequency of the VCO is controlled by the  
voltage on pin LF.  
Reference crystal oscillator  
A single transistor Collpits crystal oscillator provides a  
reference clock for the PLL. The oscillator is configured for  
parallel resonant operation in the fundamental mode (typical  
operating frequency of 3–7MHz). The crystal is connected  
between pins XTAL2 and VEE1 with external components as  
shown in Figure 6.  
(i) Stand by (TXEN low, DATA low)  
Alternatively, a reference clock can be provided by an  
external source connected to pin XTAL2 Figure 7.  
(ii) PLL Mode/Transmit SPACE (TXEN high, DATA low)  
(iii) Transmit MARK (TXEN high, DATA high)  
4
KESTX01  
vCC  
vCC  
vEE  
TXEN  
power dn  
power up  
ACTIVE CIRCUITS  
vEE  
Figure 3 TXEN power-up operation  
APPLICATIONS INFORMATION  
Power control  
Thebiascurrentforthepoweramplifierdirectlycontrolsthe  
output current (and hence the output power). The bias current  
is set by the external resistor connected between PWRC and  
ground. ThebiasvoltageonpinPWRCisnominally1.20Vand  
hence the modulation current Imod is given by 1.20/R.  
To a first order neither the linearity (harmonic spurii relative  
to fundamental) nor the amplifier efficiency are affected by  
Imod. Thegraphbelowshowstypicalsimulationresultsforthe  
amplifier current output with Imod variation.  
OUTPUT CURRENT VS Imod  
9
8
7
6
5
4
3
2
1
37  
100  
200  
300  
400  
500  
600  
MODULATION CURRENT Imod (uA)  
Figure 4 PWRC power output control  
Frequency accuracy  
Antenna interface  
The stability of the output frequency is equal to that of the  
crystal referenced oscillator and shift in the VCO frequency  
during data modulation. To operate with a final output  
accuracy of ± 66KHz at 433.92MHz (as required for use with  
the receiver KESRX01) would require a crystal with a  
tolerance specification of ± 150ppm. This tolerance should  
encompass e.g. initial accuracy, temperature stability and  
ageing.  
The IC is capable of directly interfacing to a PCB loop  
antenna as shown in the applications diagram.  
Figure 4 is an equivalent circuit for a PCB loop  
antenna.TheinductanceoftheloopisLantandthisisinseries  
withtworesistors. TheserepresentRrtheradiationresistance  
and Rs the series resistance of the antenna.  
The Q of the antenna is defined as (ωo*Lant/(Rs+Rr)  
where ωo is the resonant frequency (rad/s) of the antenna. At  
resonance the antenna can be transformed to the equivalent  
circuit on the right hand side. Here the equivalent parallel  
resistance Rp is given by  
Operation at a final output frequency of 433.92MHz  
requires a crystal specified for operation at 6.78MHz.  
5
KESTX01  
2
Rp = (Rs+ Rr)(Q + 1)  
For example, Ls=40nH, fo=433MHz, (Rs+Rr)=2.2,  
Q=50, gives an equivalent parallel resistance of 5.4k.  
Typically the antenna will be d.c. referenced to VCC as  
shown in the applications diagram. The maximum voltage  
swing across the antenna is therefore limited by the RF  
saturation voltage of the output PA stage. This is of the order  
of 0.5V and hence the peak to peak voltage across the  
antenna will be 2*(VCC–0.5V) e.g. 9V for VCC=5V. This means  
that the maximum current that can be driven into the load is  
If it is necessary to drive more power into the antenna a  
possible way to accomplish this is to perform an impedance  
transformation to the antenna.  
Theantennaalsoactsasafilterforunwanted, outofband,  
harmonic spurii. The use of a balanced output suppresses the  
2nd harmonic (and other even order harmonics). The 3rd  
harmonic of the fundamental is not automatically suppressed.  
However even a Q as low as 10 will reduce the 3rd harmonic  
by a further 32dB relative to the fundamental.  
1.7mA (peak–peak at the fundamental) and the external  
power control resistor should be set accordingly.  
Rr  
Ct  
Rs  
Rp  
Lant  
Ct  
Lant  
Figure 5 Loop antenna  
VCC  
C4  
X1  
C5  
1
14  
R1  
13  
VEE1  
VEE1  
ANTENNA  
2
3
4
5
6
7
L1  
L2  
12  
C2  
ASK MODULATION  
C1  
11  
10  
C3  
R2  
POWER UP  
9
8
VCCPA  
VEE2  
VCC  
Figure 6 Application diagram  
Note: The above application diagram is provided to assist the customer in using the IC and no guarantee can be made as to  
its correctness.  
6
KESTX01  
COMPONENT LIST at 433.92MHz  
COMPONENTS  
FUNCTION  
VALUE  
UNITS  
R1  
R2  
C1  
OUTPUT POWER CONTROL  
PLL LOOP FILTER  
2.0  
kΩ  
kΩ  
pF  
4.7  
ANTENNA TUNING  
APPLICATION  
DEPENDENT  
L1 and L2  
ANTENNA TUNING  
APPLICATION  
nH  
DEPENDENT  
C2  
C3  
X1  
C4  
C5  
PLL LOOP FILTER  
PLL LOOP FILTER  
220  
10  
pF  
nF  
PARALLEL RESONANT CRYSTAL  
CRYSTAL OSCILLATOR  
CRYSTAL OSCILLATOR  
6.78  
18  
MHz  
pF  
18  
pF  
Note: The value of C1 is split between two capacitors to aid in balancing the antenna loop reducing the level of the second  
harmonic  
TESTABILITY REQUIREMENTS  
This section is a summary of the observability and control-  
lability requirements identified to simplify the production test  
requirements of the device.  
1.AbilitytodirectlydrivetheXTALoscillatorfromthetester(no  
crystal).TheXTAL2pinallowsdirectdriveoftheoscillatorwith  
an external clock source as shown in Figure 7. Typically a  
200mVpk clock signal is AC coupled to produce differential  
output on OP and OPb. (C=10nF, R s (Source) <5k)  
C
OP  
CLK  
Rs  
XTAL2  
OPb  
XTAL1  
Figure 7 Direct drive of crystal oscillator  
2.  
Control of the VCO frequency is obtained via the LF1  
3.  
DC operation of the power amplifier is observed by  
signal pin. The output of the dividers is tested by measuring  
the DC current output of the charge pump (with XTAL2 held  
at VCC ).  
measuringthecurrentthroughtheopencollectoroutputsOUT  
and OUTB. The VCO input to the power amplifier is disabled  
with VCOTST tied to VCC and the bias current being measured  
with DATA tied to VCC . Toggling DATA input will modulate the  
bias current in the power amplifier.  
7
For more information about all Zarlink products  
visit our Web Site at  
www.zarlink.com  
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.  
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such  
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or  
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual  
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in  
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.  
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part  
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other  
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the  
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute  
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and  
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does  
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in  
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.  
2
2
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Purchase of Zarlink’s I C components conveys a licence under the Philips I C Patent rights to use these components in and I C System, provided that the system  
2
conforms to the I C Standard Specification as defined by Philips.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright Zarlink Semiconductor Inc. All Rights Reserved.  
TECHNICAL DOCUMENTATION - NOT FOR RESALE  
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