CMOS ASYNCHRONOUS FIFO IDT7203
2048 x 9, 4096 x 9, IDT7204
8192 x 9 and 16384 x 9 IDT7205
IDT7206
Integrated Device Technology, Inc.
FEATURES: DESCRIPTION:
First-In/First-Out Dual-Port memory The IDT7203/7204/7205/7206 are dual-port memory buff-
2048 x 9 organization (IDT7203) ers with internal pointers that load and empty data on a first-
4096 x 9 organization (IDT7204) in/first-out basis. The device uses Full and Empty flags to
8192 x 9 organization (IDT7205) prevent data overflow and underflow and expansion logic to
16384 x 9 organization (IDT7206) allow for unlimited expansion capability in both word size and
High-speed: 12ns access time depth.
Low power consumption
W R Data is toggled in and out of the device through the use of
-- Active: 770mW (max.)
-- Power-down: 44mW (max.) the Write ( ) and Read ( ) pins.
Asynchronous and simultaneous read and write The devices 9-bit width provides a bit for a control or parity
Fully expandable in both word depth and width
Pin and functionally compatible with IDT720X family RT at the user's option. It also features a Retransmit ( ) capa-
Status Flags: Empty, Half-Full, Full
Retransmit capability bility that allows the read pointer to be reset to its initial position
High-performance CMOS technology
Military product compliant to MIL-STD-883, Class B RT when is pulsed LOW. A Half-Full Flag is available in the
Standard Military Drawing for #5962-88669 (IDT7203),
5962-89567 (IDT7203), and 5962-89568 (IDT7204) are single device and width expansion modes.
listed on this function The IDT7203/7204/7205/7206 are fabricated using IDT's
Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications high-speed CMOS technology. They are designed for appli-
. cations requiring asynchronous and simultaneous read/writes
in multiprocessing, rate buffering, and other applications.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(D0 D8)
W WRITE
CONTROL
WRITE RAM ARRAY READ
POINTER 2048 x 9 POINTER
4096 x 9
8192 x 9
16384 x 9
THREE- RS
STATE
BUFFERS RESET
LOGIC
READ DATA OUTPUTS
(Q 0 Q8 ) / FL RT
R CONTROL
FLAG EF
LOGIC FF
EXPANSION
XI LOGIC / XO HF 2661 drw 01
The IDT logo is a registered trademark of Integrated Device Techology, Inc. DECEMBER 1996
MILITARY AND COMMERCIAL TEMPERATURE RANGES DSC-2661/9
1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 1
5.04
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO MILITARY AND COMMERCIAL TEMPERATURE RANGES
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
PIN CONFIGURATIONS
W 1 28 Vcc INDEX 4 D3 3 D8 2W NC 32 Vcc 31 D 4 30 D 5
D4
D8 2 27 D5 D2 5
D3 D6 D1 6
D2 3 26 D7 D0 7 1 29 D 6
D1 28 D 7
D0 4 P28-1 25 FL/RT XI 8 27 NC
5 P28-2 FF 9 26 / FL RT
XI 6 D28-1 24 RS J32-1
23 Q0 10 & 25 RS
FF EF Q1 11
7 D28-3 22 NC 12 L32-1 24 EF
Q0 8 SO28-3 21 XO/HF Q2 13
Q1 9 20 23 / XO HF
Q2 Q7 22 Q 7
Q3 10 19 Q6 21 Q6
Q8 Q5
GND 11 18 Q4 Q 3 14
R Q8 15
12 17 GND 16
NC 17
13 16 R 18
Q4 19
14 15 Q5 20
2661 drw 02b
2661 drw 02a PLCC/LCC
TOP VIEW
DIP
TOP VIEW
NOTES:
1. The THINDIPs P28-2 and D28-3 are only available for the 7203/7204/
7205.
2. The small outline package SO28-3 is only available for the 7204.
3. Consult factory for CERPACK pinout.
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED DC OPERATING
CONDITIONS
Symbol Rating Commercial Military Unit
VTERM 0.5 to + 7.0 0.5 to +7.0 V Symbol Parameter Min. Typ. Max. Unit
Terminal VCCM Military Supply 4.5 5.0
TA Voltage with 0 to +70 55 to +125 C Voltage 4.5 5.0 5.5 V
TBIAS Respect to 55 to +125 65 to +135 C VCCC Commercial Supply 0 0
TSTG GND 55 to + 125 65 to +155 C Voltage 2.0 -- 5.5 V
IOUT mA GND Supply Voltage
Operating 50 50 VIH(1) 2.2 -- 0 V
Temperature Input High Voltage
VIH(1) Commercial -- -- -- V
Temperature
Under Bias VIL(1) Input High Voltage -- V
Military
Storage 0.8 V
Temperature Input Low Voltage
Commercial and
DC Output Military
Current
NOTE: 2661 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating NOTE: 2661 tbl 02
1. 1.5V undershoots are allowed for 10ns once per cycle.
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
5.04 2
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO MILITARY AND COMMERCIAL TEMPERATURE RANGES
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
DC ELECTRICAL CHARACTERISTICS FOR THE 7203 AND 7204
(Commercial: VCC = 5.0V10%, TA = 0C to +70C; Military: VCC = 5.0V10%, TA = 55C to +125C)
IDT7203/7204 IDT7203/7204
Commercial Military(1)
tA = 12, 15, 20, 25, 35, 50 ns
tA = 20, 30, 40, 50, 65, 80, 120 ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
ILI(2) Input Leakage Current (Any Input) 1 -- 1 1 --
ILO(3) Output Leakage Current 10 -- 10 10 -- 1 A
10 A
VOH Output Logic "1" Voltage IOH = 2mA 2.4 -- -- 2.4 -- -- V
VOL Output Logic "0" Voltage IOL = 8mA -- -- 0.4 -- -- 0.4 V
ICC1(4) Active Power Supply Current -- -- 120(5) -- -- 150(5) mA
ICC2(4) Standby Current (R=W=RS=FL/RT=VIH) -- -- 12 -- -- 25 mA
ICC3(L)(4) Power Down Current (All Input = VCC - 0.2V) -- -- 2 -- -- 4 mA
ICC3(S)(4) Power Down Current (All Input = VCC - 0.2V) -- -- 8 -- -- 12 mA
NOTES: 2661 tbl 03
1. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.
2. Measurements with 0.4 VIN VCC.
3. R VIH, 0.4 VOUT VCC.
4. ICC measurements are made with outputs open (only capacitive loading).
5. Tested at f = 20MHz.
DC ELECTRICAL CHARACTERISTICS FOR THE 7205 AND 7206
(Commercial: VCC = 5.0V10%, TA = 0C to +70C; Military: VCC = 5.0V10%, TA = 55C to +125C)
IDT7205/7206 IDT7205/7206
Commercial Military
tA = 15, 20, 25, 35, 50 ns
tA = 20, 30, 50 ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
ILI(1) Input Leakage Current (Any Input) 1 -- 1 1 -- 1 A
ILO(2) Output Leakage Current 10 -- 10 10 -- 10 A
V
VOH Output Logic "1" Voltage IOH = 2mA 2.4 -- -- 2.4 -- -- V
mA
VOL Output Logic "0" Voltage IOL = 8mA -- -- 0.4 -- -- 0.4 mA
mA
ICC1(3) Active Power Supply Current -- -- 120(4) -- -- 150(4)
2661 tbl 04
ICC2(3) Standby Current (R=W=RS=FL/RT=VIH) -- -- 12 -- -- 25
ICC3(L)(3) Power Down Current (All Input = VCC - 0.2V) -- -- 8 -- -- 12
NOTES:
1. Measurements with 0.4 VIN VCC.
2. R VIH, 0.4 VOUT VCC.
3. ICC measurements are made with outputs open (only capacitive loading).
4. Tested at f = 20MHz.
5.04 3
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO MILITARY AND COMMERCIAL TEMPERATURE RANGES
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V 10%, TA = 0C to +70C; Military: VCC = 5V 10%, TA = 55C to +125C)
Commercial Com'l & Mil. Com'l Military Com'l
7203S/L12 7203S/L15 7203S/L20 7203S/L25 7203S/L30 7203S/L35
7204S/L12 7204S/L15 7204S/L20 7204S/L25 7204S/L30 7204S/L35
7205L15 7205L20 7205L25 7205L30 7205L35
7206L15 7206L20 7206L25 7206L30 7206L35
Symbol Parameters Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS Shift Frequency -- 50 -- 40 -- 33.3 -- 28.5 -- 25 -- 22.2 MHz
tRC Read Cycle Time 20 -- 25 -- 30 -- 35 -- 40 -- 45 -- ns
tA Access Time -- 12 -- 15 -- 20 -- 25 -- 30 -- 35 ns
tRR Read Recovery Time 8 -- 10 -- 10 -- 10 -- 10 -- 10 -- ns
tRPW Read Pulse Width(2) 12 -- 15 -- 20 -- 25 -- 30 -- 35 -- ns
tRLZ Read LOW to Data Bus LOW(3) 3 -- 5 -- 5 -- 5 -- 5 -- 5 -- ns
tWLZ Write HIGH to Data Bus Low-Z(3, 4) 3 -- 5 -- 5 -- 5 -- 5 -- 10 -- ns
tDV Data Valid from Read HIGH 5 -- 5 -- 5 -- 5 -- 5 -- 5 -- ns
tRHZ Read HIGH to Data Bus High-Z(3) -- 12 -- 15 -- 15 -- 18 -- 20 -- 20 ns
tWC Write Cycle Time 20 -- 25 -- 30 -- 35 -- 40 -- 45 -- ns
tWPW Write Pulse Width(2) 12 -- 15 -- 20 -- 25 -- 30 -- 35 -- ns
tWR Write Recovery Time 8 -- 10 -- 10 -- 10 -- 10 -- 10 -- ns
tDS Data Set-up Time 9 -- 11 -- 12 -- 15 -- 18 -- 18 -- ns
tDH Data Hold Time 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- ns
tRSC Reset Cycle Time 20 -- 25 -- 30 -- 35 -- 40 -- 45 -- ns
tRS Reset Pulse Width(2) 12 -- 15 -- 20 -- 25 -- 30 -- 35 -- ns
tRSS Reset Set-up Time(3) 12 -- 15 -- 20 -- 25 -- 30 -- 35 -- ns
tRTR Reset Recovery Time 8 -- 10 -- 10 -- 10 -- 10 -- 10 -- ns
tRTC Retransmit Cycle Time 20 -- 25 -- 30 -- 35 -- 40 -- 45 -- ns
tRT Retransmit Pulse Width(2) 12 -- 15 -- 20 -- 25 -- 30 -- 35 -- ns
tRTS Retransmit Set-up Time(3) 12 -- 15 -- 20 -- 25 -- 30 -- 35 -- ns
tRSR Retransmit Recovery Time 8 -- 10 -- 10 -- 10 -- 10 -- 10 -- ns
tEFL Reset to EF LOW -- 12 -- 25 -- 30 -- 35 -- 40 -- 45 ns
tHFH, tFFH Reset to HF and FF HIGH -- 17 -- 25 -- 30 -- 35 -- 40 -- 45 ns
tRTF Retransmit LOW to Flags Valid -- 20 -- 25 -- 30 -- 35 -- 40 -- 45 ns
tREF Read LOW to EF LOW -- 12 -- 15 -- 20 -- 25 -- 30 -- 30 ns
tRFF Read HIGH to FF HIGH -- 14 -- 15 -- 20 -- 25 -- 30 -- 30 ns
tRPE Read Pulse Width after EF HIGH 12 -- 15 -- 20 -- 25 -- 30 -- 35 -- ns
tWEF Write HIGH to EF HIGH -- 12 -- 15 -- 20 -- 25 -- 30 -- 30 ns
tWFF Write LOW to FF LOW -- 14 -- 15 -- 20 -- 25 -- 30 -- 30 ns
tWHF Write LOW to HF Flag LOW -- 17 -- 25 -- 30 -- 35 -- 40 -- 45 ns
tRHF Read HIGH to HF Flag HIGH -- 17 -- 25 -- 30 -- 35 -- 40 -- 45 ns
tWPF Write Pulse Width after FF HIGH 12 -- 15 -- 20 -- 25 -- 30 -- 35 -- ns
tXOL Read/Write LOW to XO LOW -- 12 -- 15 -- 20 -- 25 -- 30 -- 35 ns
tXOH Read/Write HIGH to XO HIGH -- 12 -- 15 -- 20 -- 25 -- 30 -- 35 ns
tXI XI Pulse Width(2) 12 -- 15 -- 20 -- 25 -- 30 -- 35 -- ns
tXIR XI Recovery Time 8 -- 10 -- 10 -- 10 -- 10 -- 10 -- ns
tXIS XI Set-up Time 8 -- 10 -- 10 -- 10 -- 10 -- 15 -- ns
NOTES: 2661 tbl 05
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
5.04 4
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO MILITARY AND COMMERCIAL TEMPERATURE RANGES
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
AC ELECTRICAL CHARACTERISTICS(1) (Continued)
(Commercial: VCC = 5V 10%, TA = 0C to +70C; Military: VCC = 5V 10%, TA = 55C to +125C)
Military Com'l & Mil. Military(2)
7203S/L40 7203S/L50 7203S/L65 7203S/L80 7203S/L120
7204S/L40 7204S/L50 7204S/L65 7204S/L80 7204S/L120
7205L50
7206L50
Symbol Parameters Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS Shift Frequency -- 20 -- 15 -- 12.5 -- 10 -- 7 MHz
tRC Read Cycle Time 50 -- 65 -- 80 -- 100 -- 140 -- ns
tA Access Time -- 40 -- 50 -- 65 -- 80 -- 120 ns
tRR Read Recovery Time 10 -- 15 -- 15 -- 20 -- 20 -- ns
tRPW Read Pulse Width(3) 40 -- 50 -- 65 -- 80 -- 120 -- ns
tRLZ Read LOW to Data Bus LOW(4) 5 -- 10 -- 10 -- 10 -- 10 -- ns
tWLZ Write HIGH to Data Bus Low-Z(4, 5) 10 -- 15 -- 15 -- 20 -- 20 -- ns
tDV Data Valid from Read HIGH 5 --5 --5 --5 --5 -- ns
tRHZ Read HIGH to Data Bus High-Z(4) -- 25 -- 30 -- 30 -- 30 -- 35 ns
tWC Write Cycle Time 50 -- 65 -- 80 -- 100 -- 140 -- ns
tWPW Write Pulse Width(3) 40 -- 50 -- 65 -- 80 -- 120 -- ns
tWR Write Recovery Time 10 -- 15 -- 15 -- 20 -- 20 -- ns
tDS Data Set-up Time 20 -- 30 -- 30 -- 40 -- 40 -- ns
tDH Data Hold Time 0 --5 -- 10 -- 10 -- 10 -- ns
tRSC Reset Cycle Time 50 -- 65 -- 80 -- 100 -- 140 -- ns
tRS Reset Pulse Width(3) 40 -- 50 -- 65 -- 80 -- 120 -- ns
tRSS Reset Set-up Time(4) 40 -- 50 -- 65 -- 80 -- 120 -- ns
tRSR Reset Recovery Time 10 -- 15 -- 15 -- 20 -- 20 -- ns
tRTC Retransmit Cycle Time 50 -- 65 -- 80 -- 100 -- 140 -- ns
tRT Retransmit Pulse Width(3) 40 -- 50 -- 65 -- 80 -- 120 -- ns
tRTS Retransmit Set-up Time(4) 40 -- 50 -- 65 -- 80 -- 120 -- ns
tRSR Retransmit Recovery Time 10 -- 15 -- 15 -- 20 -- 20 -- ns
tEFL Reset to EF LOW -- 50 -- 65 -- 80 -- 100 -- 140 ns
tHFH, tFFH Reset to HF and FF HIGH -- 50 -- 65 -- 80 -- 100 -- 140 ns
tRTF Retransmit LOW to Flags Valid -- 50 -- 65 -- 80 -- 100 -- 140 ns
tREF Read LOW to EF Flag LOW -- 35 -- 45 -- 60 -- 60 -- 60 ns
tRFF Read HIGH to FF HIGH -- 35 -- 45 -- 60 -- 60 -- 60 ns
tRPE Read Pulse Width after EF HIGH 40 -- 50 -- 65 -- 80 -- 120 -- ns
tWEF Write HIGH to EF HIGH -- 35 -- 45 -- 60 -- 60 -- 60 ns
tWFF Write LOW to FF LOW -- 35 -- 45 -- 60 -- 60 -- 60 ns
tWHF Write LOW to HF LOW -- 50 -- 65 -- 80 -- 100 -- 140 ns
tRHF Read HIGH to HF HIGH -- 50 -- 65 -- 80 -- 100 -- 140 ns
tWPF Write Pulse Width after FF HIGH 40 -- 50 -- 65 -- 80 -- 120 -- ns
tXOL Read/Write LOW to XO LOW -- 40 -- 50 -- 65 -- 80 -- 120 ns
tXOH Read/Write HIGH to XO HIGH -- 40 -- 50 -- 65 -- 80 -- 120 ns
tXI XI Pulse Width(3) 40 -- 50 -- 65 -- 80 -- 120 -- ns
tXIR XI Recovery Time 10 -- 10 -- 10 -- 10 -- 10 -- ns
tXIS XI Set-up Time 15 -- 15 -- 15 -- 15 -- 15 -- ns
NOTES: 2661 tbl 06
1. Timings referenced as in AC Test Conditions.
2. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.
3. Pulse widths less than minimum are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
5.04 5
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO MILITARY AND COMMERCIAL TEMPERATURE RANGES
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
5V
AC TEST CONDITIONS
GND to 3.0V D.U.T. 1.1K
Input Pulse Levels 5ns 680 30pF*
Input Rise/Fall Times 1.5V
Input Timing Reference Levels 1.5V
Output Reference Levels
Output Load See Figure 1
2661 tbl 07
CAPACITANCE(1) (TA = +25C, f = 1.0 MHz)
Symbol Parameter Condition Max. Unit 2661 drw 03
10 pF
CIN(1) Input Capacitance VIN = 0V 10 pF OR EQUIVALENT CIRCUIT
Figure 1. Output Load
COUT(1,2) Output Capacitance VOUT = 0V 2661 tbl 08 *Includes jig and scope capacitances.
NOTES:
1. This parameter is sampled and not 100% tested.
2. With output deselected.
SIGNAL DESCRIPTIONS READ ENABLE (R) -- A read cycle is initiated on the falling
edge of the Read Enable (R), provided the Empty Flag (EF) is not
Inputs: set. The data is accessed on a First-In/First-Out basis, inde-
pendent of any ongoing write operations. After Read Enable (R)
DATA IN (D0D8) -- Data inputs for 9-bit wide data. goes HIGH, the Data Outputs (Q0 through Q8) will return to a
high-impedance condition until the next Read operation. When
Controls: all the data has been read from the FIFO, the Empty Flag (EF)
will go LOW, allowing the "final" read cycle but inhibiting further
RESET (RS) -- Reset is accomplished whenever the Reset read operations, with the data outputs remaining in a high-
(RS) input is taken to a LOW state. During reset, both internal impedance state. Once a valid write operation has been accom-
read and write pointers are set to the first location. A reset is plished, the Empty Flag (EF) will go HIGH after tWEF and a valid
required after power-up before a write operation can take place. Read can then begin. When the FIFO is empty, the internal read
Both the Read Enable (R) and Write Enable (W) inputs must pointer is blocked from R so external changes will not affect the
be in the HIGH state during the window shown in Figure 2 FIFO when it is empty.
(i.e. tRSS before the rising edge of RS) and should not
change until tRSR after the rising edge of RS. FIRST LOAD/RETRANSMIT (FL/RT) -- This is a dual-
purpose input. In the Depth Expansion Mode, this pin is
WRITE ENABLE (W) -- A write cycle is initiated on the falling grounded to indicate that it is the first device loaded (see
edge of this input if the Full Flag (FF) is not set. Data set-up and Operating Modes). The Single Device Mode is initiated by
hold times must be adhered-to, with respect to the rising edge grounding the Expansion In (XI).
of the Write Enable (W). Data is stored in the RAM array
sequentially and independently of any on-going read operation. The IDT7203/7204/7205/7206 can be made to retransmit
data when the Retransmit Enable Control (RT) input is pulsed
After half of the memory is filled, and at the falling edge of the LOW. A retransmit operation will set the internal read pointer to
next write operation, the Half-Full Flag (HF) will be set to LOW, the first location and will not affect the write pointer. The status
and will remain set until the difference between the write pointer of the Flags will change depending on the relative locations of
and read pointer is less-than or equal to one-half of the total the read and write pointers. Read Enable (R) and Write Enable
memory of the device. The Half-Full Flag (HF) is reset by the (W) must be in the HIGH state during retransmit. This feature is
rising edge of the read operation. useful when less than 2048/4096/8192/16384 writes are per-
formed between resets. The retransmit feature is not compat-
To prevent data overflow, the Full Flag (FF) will go LOW on ible with the Depth Expansion Mode.
the falling edge of the last write signal, which inhibits further write
operations. Upon the completion of a valid read operation, the EXPANSION IN (XI) -- This input is a dual-purpose pin.
Full Flag (FF) will go HIGH after tRFF, allowing a new valid write Expansion In (XI) is grounded to indicate an operation in the
to begin. When the FIFO is full, the internal write pointer is single device mode. Expansion In (XI) is connected to Expan-
blocked from W, so external changes in W will not affect the FIFO sion Out (XO) of the previous device in the Depth Expansion or
when it is full. Daisy-Chain Mode.
5.04 6
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO MILITARY AND COMMERCIAL TEMPERATURE RANGES
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
Outputs: and will remain set until the difference between the write pointer
and read pointer is less than or equal to one half of the total
FULL FLAG (FF) -- The Full Flag (FF) will go LOW, inhibiting memory of the device. The Half-Full Flag (HF) is then reset by
further write operations, when the device is full. If the read the rising edge of the read operation.
pointer is not moved after Reset (RS), the Full Flag (FF) will go
LOW after 2048/4096/8192/16384 writes. In the Depth Expansion Mode, Expansion In (XI) is con-
nected to Expansion Out (XO) of the previous device. This
EMPTY FLAG (EF) -- The Empty Flag (EF) will go LOW, output acts as a signal to the next device in the Daisy Chain by
inhibiting further read operations, when the read pointer is equal providing a pulse to the next device when the previous device
to the write pointer, indicating that the device is empty. reaches the last location of memory. There will be an XO pulse
when the Write pointer reaches the last location of memory, and
EXPANSION OUT/HALF-FULL FLAG (XO/HF) -- This is a an additional XO pulse when the Read pointer reaches the last
dual-purpose output. In the single device mode, when Expan- location of memory.
sion In (XI) is grounded, this output acts as an indication of a half-
full memory. DATA OUTPUTS (Q0-Q8) -- Q0-Q8 are data outputs for 9-
bit wide data. These outputs are in a high-impedance condition
After half of the memory is filled, and at the falling edge of the whenever Read (R) is in a HIGH state.
next write operation, the Half-Full Flag (HF) will be set to LOW
RS t RSC t RSR
t RS
W 2661 drw 04
t RSS
R t RSS
EF t EFL
t HFH, t FFH
, HF FF
Figure 2. Reset
NOTE:
1. W and R = VIH around the rising edge of RS.
t RC t RPW
tA t RR
tA
R t RLZ t DV t RHZ
DATAOUT VALID DATAOUT VALID
Q0Q8
t WC
t WPW t WR
W t DS t DH
D0D8 DATA IN VALID DATA IN VALID
2661 drw 05
Figure 3. Asynchronous Write and Read Operation
5.04 7
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO MILITARY AND COMMERCIAL TEMPERATURE RANGES
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
LAST WRITE IGNORED FIRST READ
WRITE
R
W t RFF
t WFF 2661 drw 06
FF
Figure 4. Full FlagTiming From Last Write to First Read
LAST READ IGNORED FIRST WRITE
READ
W t REF t WEF
R
EF tA
VALID
DATA OUT
2661 drw 07
Figure 5. Empty Flag Timing From Last Read to First Write
RT t RTC t RTR
t RT
W,R FLAG VALID
HF, EF, FF t RTS
2661 drw 08
RTF
NOTE:
1. EF, FF and HF may change status during Retransmit, but flags will be valid at tRTC.
Figure 6. Retransmit
5.04 8
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO MILITARY AND COMMERCIAL TEMPERATURE RANGES
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
W
t WEF
EF
t RPE
R
2661 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.
R
t RFF
FF
t WPF
W
2661 drw 10
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.
W
t RHF
R
t WHF
HF HALF-FULL OR LESS MORE THAN HALF-FULL HALF-FULL OR LESS
2661 drw 11
Figure 9. Half-Full Flag Timing
WRITE TO
LAST PHYSICAL
W LOCATION
R t XOH READ FROM
LAST PHYSICAL
t XOL t XOH
LOCATION
XO
t XOL
2661 drw 12
Figure 10. Expansion Out
5.04 9
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO MILITARY AND COMMERCIAL TEMPERATURE RANGES
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
t XI t XIR
XI
t XIS WRITE TO
W FIRST PHYSICAL
LOCATION t XIS
R READ FROM
FIRST PHYSICAL
LOCATION
2661 drw 11
Figure 11. Expansion In
OPERATING MODES: USAGE MODES:
Care must be taken to assure that the appropriate flag is Width Expansion
monitored by each system (i.e. FF is monitored on the device Word width may be increased simply by connecting the
where W is used; EF is monitored on the device where R is
used). For additional information, refer to Tech Note 8: Oper- corresponding input control signals of multiple devices. Sta-
ating FIFOs on Full and Empty Boundary Conditions and tus flags (EF, FF and HF) can be detected from any one device.
Tech Note 6: Designing with FIFOs. Figure 13 demonstrates an 18-bit word width by using two
IDT7203/7204/7205/7206s. Any word width can be attained
Single Device Mode by adding additional IDT7203/7204/7205/7206s (Figure 13).
A single IDT7203/7204/7205/7206 may be used when the
Bidirectional Operation
application requirements are for 2048/4096/8192/16384 words Applications which require data buffering between two
or less. The IDT7203/7204/7205/7206 is in a Single Device
Configuration when the Expansion In (XI) control input is systems (each system capable of Read and Write operations)
grounded (see Figure 12). can be achieved by pairing IDT7203/7204/7205/7206s as
shown in Figure 16. Both Depth Expansion and Width Expan-
Depth Expansion sion may be used in this mode.
The IDT7203/7204/7205/7206 can easily be adapted to
Data Flow-Through
applications when the requirements are for greater than 2048/ Two types of flow-through modes are permitted, a read
4096/8192/16384 words. Figure 14 demonstrates Depth Ex-
pansion using three IDT7203/7204/7205/7206s. Any depth flow-through and write flow-through mode. For the read flow-
can be attained by adding additional IDT7203/7204/7205/ through mode (Figure 17), the FIFO permits a reading of a
7206s. The IDT7203/7204/7205/7206 operates in the Depth single word after writing one word of data into an empty FIFO.
Expansion mode when the following conditions are met: The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge, and it remains on the bus
1. The first device must be designated by grounding the First until the R line is raised from LOW-to-HIGH, after which the
Load (FL) control input. bus would go into a three-state mode after tRHZ ns. The EF line
would have a pulse showing temporary deassertion and then
2. All other devices must have FL in the HIGH state. would be asserted.
3. The Expansion Out (XO) pin of each device must be tied to
In the write flow-through mode (Figure 18), the FIFO
the Expansion In (XI) pin of the next device. See Figure 14. permits the writing of a single word of data immediately after
4. External logic is needed to generate a composite Full Flag reading one word of data from a full FIFO. The R line causes
the FF to be deasserted but the W line being LOW causes it to
(FF) and Empty Flag (EF). This requires the ORing of all be asserted again in anticipation of a new data word. On the
EFs and ORing of all FFs (i.e. all must be set to generate the rising edge of W, the new word is loaded in the FIFO. The W
correct composite FF or EF). See Figure 14. line must be toggled when FF is not asserted to write new data
5. The Retransmit (RT) function and Half-Full Flag (HF) are in the FIFO and to increment the write pointer.
not available in the Depth Expansion Mode.
Compound Expansion
For additional information, refer to Tech Note 9: Cascading The two expansion techniques described above can be
FIFOs or FIFO Modules.
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).
5.04 10
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO MILITARY AND COMMERCIAL TEMPERATURE RANGES
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
READ (R)
(HALFFULL FLAG) (HF) 9
WRITE (W) IDT DATA OUT (Q)
9 7203/ EMPTY FLAG (EF)
7204/ RETRANSMIT (RT)
DATA IN (D) 7205/
FULL FLAG (FF) 7206
RESET (RS)
EXPANSION IN (XI)
2661 drw 14
Figure 12. Block Diagram of 2048 x 9/4096 x 9/8192 x 9/16384 x 9 FIFO Used in Single Device Mode
18 9 HF HF
DATA IN (D) 9 IDT
7203/
WRITE (W) IDT 7204/
7203/ 7205/
FULL FLAG (FF) 7204/ 7206 READ (R)
7205/ EMPTY FLAG (EF)
RESET (RS) 7206 9 RETRANSMIT (RT)
9
XI XI
18
DATA OUT (Q)
2661 drw 15
NOTE:
1. Flag detection is accomplished by monitoring the FF, EF and HF signals on either (any) device used in the width expansion configuration.
Do not connect any output signals together.
Figure 13. Block Diagram of 2048 x 18/4096 x 18/8192 x 18/16384 x 18 FIFO Memory Used in Width Expansion Mode
5.04 11
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO MILITARY AND COMMERCIAL TEMPERATURE RANGES
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
TRUTH TABLES
TABLE I RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs Internal Status Outputs
Mode RS RT XI Read Pointer Write Pointer EF FF HF
Reset 0 X 0 Location Zero Location Zero 0 1 1
X
Retransmit 1 0 0 Location Zero Unchanged X X X
Read/Write 1 1 0 Increment (1) Increment (1) X X 2661 tbl 09
NOTE:
1. Pointer will Increment if flag is HIGH.
TABLE II RESET AND FIRST LOAD
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs Internal Status Outputs
Mode RS FL XI Read Pointer Write Pointer EF FF
Reset First Device 0 0 (1) Location Zero Location Zero 0 1
Reset all Other Devices 0 1 (1) Location Zero Location Zero 0 1
Read/Write 1 X (1) X X X X
NOTES: 2661 tbl 10
1. XI is connected to XO of previous device. See Figure 14.
2. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output
XO
W IDT R
FF 7203/ EF
D 9 9 7204/ 9 Q
FF 7205/
9 7206 FL
FF VCC
9 XI
XO
IDT EF
FULL 7203/ EMPTY
7204/
7205/ FL
7206
XI
XO
IDT EF
7203/
7204/
7205/
RS 7206
FL
XI
2661 drw 16
Figure 14. Block Diagram of 6149 x 9/12298 x 9/24596 x 9/49152 x 9 FIFO Memory (Depth Expansion)
5.04 12
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO MILITARY AND COMMERCIAL TEMPERATURE RANGES
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
Q 0 Q 8 Q 9 Q 17 Q (N-8) -Q N
Q 0 Q 8
Q (N-8) -Q N
Q 9 Q 17
IDT7203/
IDT7203/ IDT7203/ IDT7204/
IDT7204/ IDT7205/
IDT7205/ IDT7204/ IDT7206
IDT7206 DEPTH
DEPTH IDT7205/ EXPANSION
EXPANSION BLOCK
R, W, RS BLOCK IDT7206
DEPTH D (N-8)-D N
EXPANSION
BLOCK
D 0 -D 8 D 9 -D 17 D (N-8)-D N 2661 drw 17
D 0 D N
D 9 -D N D 18 -D N
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure 15. Compound FIFO Expansion
WA IDT RB
FFA 77772ID22200001T345A/// EF B
HFB
DA 0-8 7206
QB 0-8
SYSTEM A SYSTEM B
QA 0-8 IDT DB 0-8 2661 drw 18
7203/
RA 7204/ WB
HFA 7205/ FFB
EF A 7206
Figure 16. Bidirectional FIFO Operation
DATA IN t RPE
W t WLZ t WEF t REF
R tA DATA VALID OUT
EF
2661 drw 19
DATA OUT
Figure 17. Read Data Flow-Through Mode
5.04 13
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO MILITARY AND COMMERCIAL TEMPERATURE RANGES
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
R t WPF
W
FF t RFF t WFF t DH
DATA IN tA DATA IN VALID
DATA OUT DATA OUT VALID
t DS
Figure 18. Write Data Flow-Through Mode
2661 drw 20
ORDERING INFORMATION
IDT XXXX X XX X X
DeviceType Power Speed Package Process/
Temperature
Range
Blank Commercial (0C to +70C)
B Military (55C to +125C)
Compliant to MIL-STD-883, Class B
P Plastic DIP
TP Plastic THINDIP
Ceramic DIP
D
TD Ceramic THINDIP (all except 7206)
Plastic Leaded Chip Carrier
J
Leadless Chip Carrier (Military only)
L
SO Small Outline IC (7204 only)
12 Commercial 7203/04 Only Access Time (tA)
15 Commercial Only Speed in ns
20
25 Commercial Only
30 Military Only
35 Commercial Only
40 Military 7203/04 Only
50
65
80 Military 7203/04DB Only
120
S Standard Power (7203/7204 only) 2661 drw 21
L Low Power
7203 2048 x 9 FIFO
7204 4096 x 9 FIFO
7205 8192 x 9 FIFO
7206 16384 x 9 FIFO
5.04 14
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