ICM-20602
High Performance 6-Axis MEMS MotionTracking™ Device
General Description Applications
The ICM-20602 is a 6-axis MotionTracking device that Smartphones and Tablets
combines a 3-axis gyroscope, 3-axis accelerometer, in a small Wearable Sensors
3 mm x 3 mm x 0.75 mm (16-pin LGA) package. IoT Applications
Motion-based game controllers
High performance specs 3D remote controls for Internet connected DTVs and
o Gyroscope sensitivity error: ±1% set top boxes, 3D mice
o Gyroscope noise: ±4 mdps/Hz
o Accelerometer noise: 100 µg/Hz Features
Includes 1 KB FIFO to reduce traffic on the serial bus 3-Axis Gyroscope with Programmable FSR of ±250
interface, and reduce power consumption by allowing the dps, ±500 dps, ±1000 dps, and ±2000 dps
system processor to burst read sensor data and then go 3-Axis Accelerometer with Programmable FSR of ±2g,
into a low-power mode ±4g, ±8g, and ±16g
EIS FSYNC support User-programmable interrupts
ICM-20602 includes on-chip 16-bit ADCs, programmable Wake-on-motion interrupt for low power operation
digital filters, an embedded temperature sensor, and of applications processor
programmable interrupts. The device features an operating 1 KB FIFO buffer enables the applications processor to
voltage range down to 1.71V. Communication ports include I2C read the data in bursts
and high speed SPI at 10 MHz. On-Chip 16-bit ADCs and Programmable Filters
Host interface: 10 MHz SPI or 400 kHz Fast Mode I2C
Ordering Information Digital-output temperature sensor
VDD operating range of 1.71V to 3.45V
PART TEMP RANGE PACKAGE MEMS structure hermetically sealed and bonded at
wafer level
ICM-20602† −40°C to +85°C 16-Pin LGA RoHS and Green compliant
†Denotes RoHS and Green-Compliant Package
Typical Operating Circuit
Block Diagram 1.71 – 3.45VDC
C2, 0.1 mF C4, 2.2 VDD RESV
mF
REGOUT
16 15 14
AP/HUB C1, 0.1 mF
M 1.71 – 3.45 VDC VDDIO 1 13 GND
C3, 10 nF SCL SCL/SPC 2 12 RESV
SPI/I2C SDA/SDI ICM-20602 RESV
SDA 3 11
S AD0 SA0/SDO 4 10 RESV
VDDIO CS RESV
5 9
ICM-20602 FSYNC for EIS
6 7 8
INT RESV FSYNC
Main PCB
InvenSense reserves the right to change the detail InvenSense Inc. Document Number: DS-000176
specifications as may be required to permit 1745 Technology Drive, San Jose, CA 95110 U.S.A Revision: 1.0
improvements in the design of its products. +1(408) 988–7339 Revision Date: 10/03/2016
www.invensense.com
ICM-20602
TABLE OF CONTENTS
General Description ............................................................................................................................................. 1
Ordering Information...........................................................................................................................................1
Block Diagram ...................................................................................................................................................... 1
Applications ......................................................................................................................................................... 1
Features ............................................................................................................................................................... 1
Typical Operating Circuit......................................................................................................................................1
1 Introduction ......................................................................................................................................................... 7
1.1 Purpose and Scope....................................................................................................................................7
1.2 Product Overview...................................................................................................................................... 7
1.3 Applications............................................................................................................................................... 7
2 Features ............................................................................................................................................................... 8
2.1 Gyroscope Features .................................................................................................................................. 8
2.2 Accelerometer Features............................................................................................................................ 8
2.3 Additional Features ................................................................................................................................... 8
3 Electrical Characteristics ...................................................................................................................................... 9
3.1 Gyroscope Specifications .......................................................................................................................... 9
3.2 Accelerometer Specifications.................................................................................................................. 10
3.3 Electrical Specifications........................................................................................................................... 11
3.4 I2C Timing Characterization ..................................................................................................................... 14
3.5 SPI Timing Characterization .................................................................................................................... 15
3.6 Absolute Maximum Ratings .................................................................................................................... 16
4 Applications Information ................................................................................................................................... 17
4.1 Pin Out Diagram and Signal Description ................................................................................................. 17
4.2 Typical Operating Circuit ......................................................................................................................... 18
4.3 Bill of Materials for External Components .............................................................................................. 18
4.4 Block Diagram ......................................................................................................................................... 19
4.5 Overview ................................................................................................................................................. 19
4.6 Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning ............................................... 20
4.7 Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning.........................................20
4.8 I2C and SPI Serial Communication Interfaces .......................................................................................... 20
4.9 Self-Test................................................................................................................................................... 21
4.10 Clocking............................................................................................................................................... 21
4.11 Sensor Data Registers ......................................................................................................................... 21
4.12 FIFO..................................................................................................................................................... 22
4.13 Interrupts ............................................................................................................................................ 22
4.14 Digital-Output Temperature Sensor ................................................................................................... 22
4.15 Bias and LDOs ..................................................................................................................................... 22
4.16 Charge Pump ...................................................................................................................................... 22
Document Number: DS-000176 Page 2 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
4.17 Standard Power Modes – Update the Power Modes ......................................................................... 22
5 Programmable Interrupts .................................................................................................................................. 23
5.1 Wake-on-Motion Interrupt ..................................................................................................................... 23
6 Digital Interface ................................................................................................................................................. 24
6.1 I2C and SPI Serial Interfaces .................................................................................................................... 24
6.2 I2C Interface............................................................................................................................................. 24
6.3 I2C Communications Protocol ................................................................................................................. 24
6.4 I2C Terms ................................................................................................................................................. 26
6.5 SPI Interface ............................................................................................................................................ 26
7 Serial Interface Considerations .......................................................................................................................... 28
7.1 ICM-20602 Supported Interfaces ............................................................................................................ 28
8 Register Map...................................................................................................................................................... 29
9 Register Descriptions ......................................................................................................................................... 32
9.1 Register Descriptions .............................................................................................................................. 32
9.2 Register 04 – Gyroscope Low Noise to Low Power Offset Shift and Gyroscope Offset Temperature Compensation (TC) Register32
9.3 Register 05 – Gyroscope Low Noise to Low Power Offset Shift and Gyroscope Offset Temperature Compensation (TC) Register32
9.4 Register 07 – Gyroscope Low Noise to Low Power Offset Shift and Gyroscope Offset Temperature Compensation (TC) Register32
9.5 Register 08 – Gyroscope Low Noise to Low Power Offset Shift and Gyroscope Offset Temperature Compensation (TC) Register33
9.6 Register 10 – Gyroscope Low Noise to Low Power Offset Shift and Gyroscope Offset Temperature Compensation (TC) Register33
9.7 Register 11 – Gyroscope Low Noise to Low Power Offset Shift and Gyroscope Offset Temperature Compensation (TC) Register33
9.8 Registers 13 to 15 Accelerometer Self-Test Registers ............................................................................ 34
9.9 Register 19 – X-Gyro Offset Adjustment Register: High Byte ................................................................. 34
9.10 Register 20 – X-Gyro Offset Adjustment Register: Low Byte .............................................................. 34
9.11 Register 21 – Y-Gyro Offset Adjustment Register: High Byte ............................................................. 35
9.12 Register 22 – Y-Gyro Offset Adjustment Register: Low Byte .............................................................. 35
9.13 Register 23 – Z-Gyro Offset Adjustment Register: High Byte ............................................................. 35
9.14 Register 24 – Z-Gyro Offset Adjustment Register: Low Byte .............................................................. 35
9.15 Register 25 – Sample Rate Divider......................................................................................................36
9.16 Register 26 – Configuration ................................................................................................................ 36
9.17 Register 27 – Gyroscope Configuration .............................................................................................. 37
9.18 Register 28 – Accelerometer Configuration ....................................................................................... 37
9.19 Register 29 – Accelerometer Configuration 2..................................................................................... 38
9.20 Register 30 – Gyroscope Low Power Mode Configuration ................................................................. 39
9.21 Register 32 – Wake-on Motion Threshold: X-Axis Accelerometer ..................................................... 40
9.22 Register 33 – Wake-on Motion Threshold: Y-Axis Accelerometer...................................................... 40
9.23 Register 34 – Wake-on Motion Threshold: Z-Axis Accelerometer...................................................... 40
9.24 Register 35 – FIFO Enable ................................................................................................................... 41
9.25 Register 54 – FSYNC Interrupt Status.................................................................................................. 41
9.26 Register 55 – INT/DRDY Pin / Bypass Enable Configuration ............................................................... 41
Document Number: DS-000176 Page 3 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9.27 Register 57 – FIFO Watermark Interrupt Status ................................................................................. 42
9.28 Register 58 – Interrupt Status............................................................................................................. 42
9.29 Registers 59 to 64 – Accelerometer Measurements: X-Axis High Byte .............................................. 42
9.30 Registers 65 to 66 – Temperature Measurement............................................................................... 43
9.31 Registers 67 to 72 – Gyroscope Measurement................................................................................... 43
9.32 Register 80 to 82 – Gyroscope Self-Test Registers ............................................................................. 44
9.33 Register 96 to 97 – FIFO Watermark Threshold in Number of Bytes ................................................. 45
9.34 Register 104 – Signal Path Reset.........................................................................................................45
9.35 Register 105 – Accelerometer Intelligence Control ............................................................................ 45
9.36 Register 106 – User Control ................................................................................................................ 46
9.37 Register 107 – Power Management 1 ................................................................................................ 46
9.38 Register 108 – Power Management 2 ................................................................................................ 47
9.39 Register 112 – I2C Interface ................................................................................................................ 47
9.40 Register 114 and 115 – FIFO Count Registers ..................................................................................... 47
9.41 Register 116 – FIFO Read Write .......................................................................................................... 48
9.42 Register 117 – Who Am I .................................................................................................................... 48
9.43 Registers 119, 120, 122, 123, 125, 126 – Accelerometer Offset Registers ......................................... 49
10 Use Notes........................................................................................................................................................... 50
10.1 Temperature Sensor Data................................................................................................................... 50
10.2 Accelerometer-Only Low-Noise Mode ............................................................................................... 50
10.3 Accelerometer Low-Power Mode.......................................................................................................50
10.4 Sensor Mode Change .......................................................................................................................... 50
10.5 Temp Sensor during Gyroscope Standby Mode ................................................................................. 50
10.6 Gyroscope Mode Change.................................................................................................................... 50
10.7 Power Management 1 Register Setting .............................................................................................. 50
10.8 Unlisted Register Locations ................................................................................................................ 50
10.9 Clock Transition When Gyroscope is Turned Off ................................................................................ 50
10.10 Sleep Mode ......................................................................................................................................... 50
10.11 No special operation needed for FIFO read in low power mode........................................................ 50
10.12 Gyroscope Standby Procedure ........................................................................................................... 51
11 Assembly ............................................................................................................................................................ 52
11.1 Orientation of Axes............................................................................................................................. 52
12.1 Package Dimensions ........................................................................................................................... 53
13 Part Number Package Marking .......................................................................................................................... 55
14 Revision History ................................................................................................................................................. 56
15 Environmental Compliance................................................................................................................................ 57
Document Number: DS-000176 Page 4 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
LIST OF FIGURES
Figure 1. I2C Bus Timing Diagram ............................................................................................................................................................. 14
Figure 2. SPI Bus Timing Diagram.............................................................................................................................................................15
Figure 3. Pin out Diagram for ICM-20602 3 mm x 3 mm x 0.75 mm LGA ................................................................................................ 17
Figure 4. ICM-20602 Application Schematic ............................................................................................................................................ 18
Figure 5. ICM-20602 Block Diagram.........................................................................................................................................................19
Figure 6. ICM-20602 Solution Using I2C Interface....................................................................................................................................20
Figure 7. ICM-20602 Solution Using SPI Interface ................................................................................................................................... 21
Figure 8. START and STOP Conditions......................................................................................................................................................24
Figure 9. Acknowledge on the I2C Bus ..................................................................................................................................................... 25
Figure 10. Complete I2C Data Transfer.....................................................................................................................................................25
Figure 11. Typical SPI Master/Slave Configuration .................................................................................................................................. 27
Figure 11. I/O Levels and Connections.....................................................................................................................................................28
Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation .................................................................................................... 52
Figure 14. Package Dimensions................................................................................................................................................................ 53
Figure 15. Part Number Package Marking ............................................................................................................................................... 55
Document Number: DS-000176 Page 5 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
LIST OF TABLES
Table 1. Gyroscope Specifications ............................................................................................................................................................. 9
Table 2. Accelerometer Specifications.....................................................................................................................................................10
Table 4. D.C. Electrical Characteristics ..................................................................................................................................................... 11
Table 5. A.C. Electrical Characteristics ..................................................................................................................................................... 12
Table 6. Other Electrical Specifications....................................................................................................................................................13
Table 7. I2C Timing Characteristics ........................................................................................................................................................... 14
Table 7. SPI Timing Characteristics (10 MHz Operation) ......................................................................................................................... 15
Table 8. Absolute Maximum Ratings ....................................................................................................................................................... 16
Table 9. Signal Descriptions ..................................................................................................................................................................... 17
Table 10. Bill of Materials ........................................................................................................................................................................ 18
Table 11. Standard Power Modes for ICM-20602.................................................................................................................................... 22
Table 12. Table of Interrupt Sources........................................................................................................................................................23
Table 13. Serial Interface ......................................................................................................................................................................... 24
Table 14. I2C Terms .................................................................................................................................................................................. 26
Table 15. Register Map ............................................................................................................................................................................ 30
Table 16. Package Dimensions Table ....................................................................................................................................................... 54
Document Number: DS-000176 Page 6 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
1 INTRODUCTION
1.1 PURPOSE AND SCOPE
This document is a product specification, providing a description, specifications, and design related information on the ICM-20602™
MotionTracking device. The device is housed in a small 3 mm x 3 mm x 0.75 mm 16-pin LGA package.
1.2 PRODUCT OVERVIEW
The ICM-20602 is a 6-axis MotionTracking device that combines a 3-axis gyroscope, 3-axis accelerometer, in a small
3 mm x 3 mm x 0.75 mm (16-pin LGA) package. It also features a 1 KB FIFO that can lower the traffic on the serial bus interface, and
reduce power consumption by allowing the system processor to burst read sensor data and then go into a low-power mode. ICM-
20602, with its 6-axis integration, enables manufacturers to eliminate the costly and complex selection, qualification, and system
level integration of discrete devices, guaranteeing optimal motion performance for consumers.
The gyroscope has a programmable full-scale range of ±250 dps, ±500 dps, ±1000 dps, and ±2000 dps. The accelerometer has a user-
programmable accelerometer full-scale range of ±2g, ±4g, ±8g, and ±16g. Factory-calibrated initial sensitivity of both sensors
reduces production-line calibration requirements.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and
programmable interrupts. The device features I2C and SPI serial interfaces,, a VDD operating range of 1.71V to 3.45V, and a separate
digital IO supply, VDDIO from 1.71V to 3.45V.
Communication with all registers of the device is performed using either I2C at 400 kHz or SPI at 10 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion
CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a footprint and thickness of 3 mm x
3 mm x 0.75 mm (16-pin LGA), to provide a very small yet high performance low cost package. The device provides high robustness
by supporting 20,000g shock reliability.
1.3 APPLICATIONS
Smartphones and Tablets
Wearable Sensors
Document Number: DS-000176 Page 7 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
2 FEATURES
2.1 GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the ICM-20602 includes a wide range of features:
Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with a user-programmable full-scale range of ±250 dps,
±500 dps, ±1000 dps, and ±2000 dps and integrated 16-bit ADCs
Digitally-programmable low-pass filter
Low-power gyroscope operation
Factory calibrated sensitivity scale factor
Self-test
2.2 ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in ICM-20602 includes a wide range of features:
Digital-output X-, Y-, and Z-axis accelerometer with a programmable full scale range of ±2g, ±4g, ±8g, and ±16g and integrated
16-bit ADCs
User-programmable interrupts
Wake-on-motion interrupt for low power operation of applications processor
Self-test
2.3 ADDITIONAL FEATURES
The ICM-20602 includes the following additional features:
Smallest and thinnest LGA package for portable devices: 3 mm x 3 mm x 0.75 mm (16-pin LGA)
Minimal cross-axis sensitivity between the accelerometer and gyroscope axes
1 KB FIFO buffer enables the applications processor to read the data in bursts
Digital-output temperature sensor
User-programmable digital filters for gyroscope, accelerometer, and temp sensor
20,000 g shock tolerant
400 kHz Fast Mode I2C for communicating with all registers
10 MHz SPI serial interface for communicating with all registers
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
Document Number: DS-000176 Page 8 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
3 ELECTRICAL CHARACTERISTICS
3.1 GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
GYROSCOPE SENSITIVITY
Full-Scale Range FS_SEL=0 ±250 dps 3
FS_SEL=1 ±500 dps 3
FS_SEL=2 ±1000 dps 3
FS_SEL=3 ±2000 dps 3
Gyroscope ADC Word Length 16 bits 3
Sensitivity Scale Factor FS_SEL=0 131 LSB/(dps) 3
FS_SEL=1 65.5 LSB/(dps) 3
FS_SEL=2 32.8 LSB/(dps) 3
FS_SEL=3 16.4 LSB/(dps) 3
Sensitivity Scale Factor Initial Tolerance 25°C ±1 % 1
Sensitivity Scale Factor Variation Over -40°C to +85°C ±2 % 1
Temperature
Nonlinearity Best fit straight line; 25°C ±0.1 % 1
Cross-Axis Sensitivity ±1 % 1
ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance 25°C ±1 dps 1
ZRO Variation vs. Temperature -40°C to +85°C ±0.01 dps/ºC 1
OTHER PARAMETERS
Rate Noise Spectral Density @ 10 Hz 0.004 dps /√Hz 1, 4
Total RMS Noise Bandwidth = 100 Hz 0.04 dps -rms 1, 4
Gyroscope Mechanical Frequencies 25 27 29 KHz 2
Low Pass Filter Response Programmable Range 5 250 Hz 3
Gyroscope Start-Up Time Time from gyro enable to gyro drive ready 35 100 ms 1
Output Data Rate Low-Noise mode 3.91 8000 Hz 3
Low Power Mode 3.91 333.33 Hz 3
Table 1. Gyroscope Specifications
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Tested in production.
3. Guaranteed by design.
4. Noise specifications shown are for low-noise mode.
Document Number: DS-000176 Page 9 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
3.2 ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
ACCELEROMETER SENSITIVITY
Full-Scale Range AFS_SEL=0 ±2 g 2
AFS_SEL=1 ±4 g 2
AFS_SEL=2 ±8 g 2
AFS_SEL=3 ±16 g 2
ADC Word Length Output in two’s complement format 16 bits 2
Sensitivity Scale Factor AFS_SEL=0 16,384 LSB/g 2
AFS_SEL=1 8,192 LSB/g 2
AFS_SEL=2 4,096 LSB/g 2
AFS_SEL=3 2,048 LSB/g 2
Sensitivity Scale Factor Initial Tolerance Component-level ±1 % 1
Sensitivity Change vs. Temperature -40°C to +85°C ±1.5 % 1
Nonlinearity Best Fit Straight Line ±0.3 % 1
Cross-Axis Sensitivity ±1 % 1
ZERO-G OUTPUT
Initial Tolerance Component-level, all axes ±25 mg 1
Board-level, all axes ±40 mg 1
Zero-G Level Change vs. Temperature -40°C to +85°C X and Y axes ±0.5 mg/ºC 1
Z axis ±1 mg/ºC 1
OTHER PARAMETERS
Power Spectral Density @ 10 Hz 100 µg/√Hz 1, 3
RMS Noise Bandwidth = 100 Hz 1.0 mg-rms 1, 3
Low-Pass Filter Response Programmable Range 5 218 Hz 2
Accelerometer Startup Time From sleep mode to valid data 10 20 ms 2
Output Data Rate Low-Noise mode 3.91 4000 Hz 2
Low Power Mode 3.91 500 Hz
Table 2. Accelerometer Specifications
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Guaranteed by design.
3. Noise specifications shown are for low-noise mode.
Document Number: DS-000176 Page 10 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
3.3 ELECTRICAL SPECIFICATIONS
D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
SUPPLY VOLTAGES
VDD 1.71 1.8 3.45 V 1
VDDIO 1.71 1.8 3.45 V 1
SUPPLY CURRENTS
Low-Noise Mode 6-Axis Gyroscope + Accelerometer 2.79 mA 1
3-Axis Accelerometer 321 µA 1
3-Axis Gyroscope 2.55 mA 1
Accelerometer Low -Power Mode 100 Hz ODR, 1x averaging µA 1
(Gyroscope disabled) 40
Gyroscope Low-Power Mode 100 Hz ODR, 1x averaging 1.08 mA 1
(Accelerometer disabled)
6-Axis Low-Power Mode (Gyroscope
Low-Power Mode; Accelerometer Low- 100 Hz ODR, 1x averaging 1.33 mA 1
Noise Mode)
Full-Chip Sleep Mode At 25ºC 6 µA 1
Specified Temperature Range Performance parameters are not applicable -40 +85 °C 1
beyond Specified Temperature Range
Table 3. D.C. Electrical Characteristics
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
Document Number: DS-000176 Page 11 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
SUPPLIES
Supply Ramp Time Monotonic ramp. Ramp rate is 10% to 90% of 0.01 3 ms
the final value 1
Power Supply Noise 10 mV peak- 1
peak
TEMPERATURE SENSOR
Operating Range Ambient -40 85 °C 1
25°C Output 0 LSB 3
ADC Resolution 16 bits 2
ODR Without Filter 8000 Hz 2
With Filter 3.91 1000 Hz 2
Room Temperature Offset 25°C -15 15 °C 3
Stabilization Time 14000 µs 2
Sensitivity Untrimmed 326.8 LSB/°C 1
Sensitivity Error -2.5 +2.5 % 1
Power-On RESET
Start-up time for register read/write From power-up 2 ms 1
I2C ADDRESS
I2C ADDRESS SA0 = 0 1101000
SA0 = 1 1101001
DIGITAL INPUTS (FSYNC, SA0, SPC, SDI, CS)
VIH, High Level Input Voltage 0.7*VDDIO V
VIL, Low Level Input Voltage 0.3*VDDIO V 1
CI, Input Capacitance < 10 pF
DIGITAL OUTPUT (SDO, INT, DRDY)
VOH, High Level Output Voltage RLOAD=1MΩ; 0.9*VDDIO V
VOL1, LOW-Level Output Voltage RLOAD=1MΩ; 0.1*VDDIO V
VOL.INT, INT Low-Level Output Voltage OPEN=1, 0.3mA sink 0.1 V 1
Current
Output Leakage Current OPEN=1 100 nA
tINT, INT Pulse Width LATCH_INT_EN=0 50 µs
I2C I/O (SCL, SDA)
VIL, LOW Level Input Voltage -0.5V 0.3*VDDIO V
VIH, HIGH-Level Input Voltage 0.7*VDDIO VDDIO + 0.5V V
Vhys, Hysteresis 0.1*VDDIO V
VOL, LOW-Level Output Voltage 3mA sink current 0 0.4 V 1
IOL, LOW-Level Output Current VOL=0.4V 3 mA
VOL=0.6V 6 mA
Output Leakage Current 100 nA
tof, Output Fall Time from VIHmax to VILmax Cb bus capacitance in pf 20+0.1Cb 300 ns
INTERNAL CLOCK SOURCE
FCHOICE_B=1,2,3; SMPLRT_DIV=0 32 kHz 2
FCHOICE_B=0;
DLPFCFG=0 or 7 8 kHz 2
Sample Rate SMPLRT_DIV=0
FCHOICE_B=0;
DLPFCFG=1,2,3,4,5,6; 1 kHz 2
SMPLRT_DIV=0
Clock Frequency Initial Tolerance CLK_SEL=0, 6 or gyro inactive; 25°C -3 +3 % 1
CLK_SEL=1,2,3,4,5 and gyro active; 25°C -1 +1 % 1
Frequency Variation over Temperature CLK_SEL=0,6 or gyro inactive. (-40°C to +85°C) ±2 % 1
CLK_SEL=1,2,3,4,5 and gyro active ±2 % 1
Table 4. A.C. Electrical Characteristics
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. Guaranteed by design.
3. Production tested.
Document Number: DS-000176 Page 12 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
Other Electrical Specifications
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
SERIAL INTERFACE
SPI Operating Frequency, All Registers Low Speed Characterization 100 100 ±10% kHz 1,3
Read/Write High Speed Characterization 0.2 1 10 MHz 1, 2, 3
SPI Modes 0 and 3
I2C Operating Frequency All registers, Fast-mode 100 400 kHz 1
All registers, Standard-mode 100 kHz 1
Table 5. Other Electrical Specifications
Notes:
1. Derived from validation or characterization of parts, not guaranteed in production.
2. SPI clock duty cycle between 45% and 55% should be used for 10-MHz operation.
3. Minimum SPI/I2C clock rate is dependent on ODR. If ODR is below 4 kHz, minimum clock rate is 100 kHz. If ODR is greater than 4 kHz, minimum clock rate is
200 kHz.
Document Number: DS-000176 Page 13 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
3.4 I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
Parameters Conditions Min Typical Max Units Notes
I2C TIMING I2C FAST-MODE
fSCL, SCL Clock Frequency 100 400 kHz 1
tHD.STA, (Repeated) START Condition Hold Time 0.6 µs 1
tLOW, SCL Low Period 1.3 µs 1
tHIGH, SCL High Period 0.6 µs 1
tSU.STA, Repeated START Condition Setup Time 0.6 µs 1
tHD.DAT, SDA Data Hold Time 0 µs 1
tSU.DAT, SDA Data Setup Time 100 ns 1
tr, SDA and SCL Rise Time Cb bus cap. from 10 to 400 pF 20+0.1Cb 300 ns 1
tf, SDA and SCL Fall Time Cb bus cap. from 10 to 400 pF 20+0.1Cb 300 ns 1
tSU.STO, STOP Condition Setup Time 0.6 µs 1
tBUF, Bus Free Time Between STOP and START 1.3 µs 1
Condition
Cb, Capacitive Load for each Bus Line < 400 pF 1
tVD.DAT, Data Valid Time 0.9 µs 1
tVD.ACK, Data Valid Acknowledge Time 0.9 µs 1
Table 6. I2C Timing Characteristics
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
tf tr tSU.DAT
SDA 70% 70%
30% 30%
tf continued below at A
tr tVD.DAT
SCL 70% tHD.DAT 70%
30% 30%
tHD.STA 1/fSCL tLOW 9th clock cycle
S 1st clock cycle tHIGH
tBUF
SDA 70%
A 30%
tSU.STA tHD.STA tVD.ACK tSU.STO
SCL 70%
30%
Sr 9th clock cycle P S
Figure 1. I2C Bus Timing Diagram
Document Number: DS-000176 Page 14 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
3.5 SPI TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
Parameter Conditions Min Typ Max Units Notes
SPI TIMING
fSPC, SPC Clock Frequency 10 MHz 1
tLOW, SPC Low Period 45 ns 1
tHIGH, SPC High Period 45 ns 1
tSU.CS, CS Setup Time 2 ns 1
tHD.CS, CS Hold Time 63 ns 1
tSU.SDI, SDI Setup Time 3 ns 1
tHD.SDI, SDI Hold Time 7 ns 1
tVD.SDO, SDO Valid Time Cload = 20pF 40 ns 1
tDIS.SDO, SDO Output Disable Time 20 ns 1
Table 7. SPI Timing Characteristics (10 MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
CS 70%
30%
tSU;CS tHIGH 1/fCLK tHD;CS
SCLK 70%
30%
tSU;SDI tHD;SDI tLOW
SDI 70% MSB IN LSB IN
30%
tVD;SDO tDIS;SDO
SDO MSB OUT 70% LSB OUT
30%
Figure 2. SPI Bus Timing Diagram
Document Number: DS-000176 Page 15 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
3.6 ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for
extended periods may affect device reliability.
Parameter Rating
Supply Voltage, VDD -0.5V to +4V
Supply Voltage, VDDIO -0.5V to +4V
REGOUT -0.5V to 2V
Input Voltage Level (SA0, FSYNC, SCL, SDA) -0.5V to VDDIO + 0.5V
Acceleration (Any Axis, unpowered) 20,000g for 0.2 ms
Operating Temperature Range -40°C to +85°C
Storage Temperature Range -40°C to +125°C
Electrostatic Discharge (ESD) Protection 2 kV (HBM);
250V (MM)
Latch-up JEDEC Class II (2),125°C
±100 mA
Table 8. Absolute Maximum Ratings
Document Number: DS-000176 Page 16 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
4 APPLICATIONS INFORMATION
4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
Pin Number Pin Name Pin Description
1 VDDIO Digital I/O supply voltage
2 SCL/SPC I2C serial clock (SCL); SPI serial clock (SPC)
3 SDA/SDI I2C serial data (SDA); SPI serial data input (SDI)
4 SA0/SDO I2C slave address LSB (SA0); SPI serial data output (SDO)
5 CS Chip select (0 = SPI mode; 1 = I2C mode)
6 INT Interrupt digital output (totem pole or open-drain)
7 RESV Reserved. Do not connect.
8 FSYNC Synchronization digital input (optional). Connect to GND if unused.
9 RESV Reserved. Connect to GND.
10 RESV Reserved. Connect to GND.
11 RESV Reserved. Connect to GND.
12 RESV Reserved. Connect to GND.
13 GND Connect to GND
14 REGOUT Regulator filter capacitor connection
15 RESV Reserved. Connect to GND.
16 VDD Power Supply
Table 9. Signal Descriptions
Note: Power up with SCL/SPC and CS pins held low is not a supported use case. In case this power up approach is used, software reset is required using the
PWR_MGMT_1 register, prior to initialization.
VDD RESV REGOUT
16 15 14
VDDIO 1 13 GND
+Z
SCL/SPC 2 12 RESV
SDA/SDI 3 ICM-20602 11 RESV ICM-20602
SA0/SDO 4 10 RESV
CS 5 9 RESV
6 7 8 +Y +X
INT RESV FSYNC
LGA Package (Top View)
16-pin, 3mm x 3mm x 0.75mm Orientation of Axes of Sensitivity and Polarity of Rotation
Typical Footprint and thickness
Figure 3. Pin out Diagram for ICM-20602 3 mm x 3 mm x 0.75 mm LGA
Document Number: DS-000176 Page 17 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
4.2 TYPICAL OPERATING CIRCUIT
1.711.–8 3–.435.3VVDDCC
C2, 0.1 mF C4, 2.2 VDD RESV
mF
REGOUT
16 15 14
C1, 0.1 mF
1.711.8––3.34.53VVDDCC VDDIO 1 13 GND
C3, 10 nF SCL SCL/SPC 2 12 RESV
SDA SDA/SDI 3 ICM-20602 11 RESV
AD0 SA0/SDO 4 10 RESV
VDDIO CS RESV
5 9
6 7 8
INT RESV FSYNC
Figure 4. ICM-20602 Application Schematic
Note: I2C lines are open drain and pullup resistors (e.g. 10 kΩ) are required.
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS
Component Label Specification Quantity
REGOUT Capacitor C1 X7R, 0.1 µF ±10% 1
VDD Bypass Capacitors C2 X7R, 0.1 µF ±10% 1
C4 X7R, 2.2 µF ±10% 1
VDDIO Bypass Capacitor C3 X7R, 10 nF ±10% 1
Table 10. Bill of Materials
Document Number: DS-000176 Page 18 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
4.4 BLOCK DIAGRAM
ICM-20602
INT
Self X Accel ADC
test Interrupt
Status
Register
CS
Self Y Accel ADC Slave I2C and
test SA0 / SDO
FIFO SPI Serial
Interface SCL / SPC
Self SDA / SDI
test Z Accel ADC User & Config
Signal Conditioning Registers
FSYNC
Self X Gyro ADC
test Sensor
Registers
Self Y Gyro ADC
test
Self Z Gyro ADC
test
Temp Sensor ADC
Charge Bias & LDOs
Pump
VDD GND REGOUT
Figure 5. ICM-20602 Block Diagram
4.5 OVERVIEW
The ICM-20602 is comprised of the following key blocks and functions:
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
I2C and SPI serial communications interface
Self-Test
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes
Document Number: DS-000176 Page 19 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
4.6 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-20602 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the X-, Y-, and Z- Axes.
When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff.
The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage
is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro
sensors may be digitally programmed to ±250, ±500, ±1000, or ±2000 degrees per second (dps). The ADC sample rate is
programmable from 8,000 samples per second, down to 3.9 samples per second, and user-selectable low-pass filters enable a wide
range of cut-off frequencies.
4.7 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-20602’s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular axis induces
displacement on the corresponding proof mass, and capacitive sensors detect the displacement differentially. The ICM-20602’s
architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed
on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The accelerometers’ scale factor is calibrated at the
factory and is nominally independent of supply voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs.
The full scale range of the digital output can be adjusted to ±2g, ±4g, ±8g, or ±16g.
4.8 I2C AND SPI SERIAL COMMUNICATION INTERFACES
The ICM-20602 communicates to a system processor using either a SPI or an I2C serial interface. The ICM-20602 always acts as a
slave when communicating to the system processor. The LSB of the I2C slave address is set by pin 4 (SA0).
ICM-20602 Solution Using I2C Interface
In Figure 6, the system processor is an I2C master to the ICM-20602.
Interrupt I2C Processor Bus: for reading all
Status INT sensor data from MPU
Register
ICM-20602 SA0 VDDIO or GND
Slave I2C
or SPI SCL SCL
Serial System
Interface SDA SDA Processor
FIFO
User & Config
Registers
Sensor
Register
Factory
Calibration
Bias & LDOs
VDD GND REGOUT
Figure 6. ICM-20602 Solution Using I2C Interface
Document Number: DS-000176 Page 20 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
ICM-20602 Solution Using SPI Interface
In the figure below, the system processor is an SPI master to the ICM-20602. Pins 2, 3, 4, and 5 are used to support the SPC, SDI,
SDO, and CS signals for SPI communications.
Processor SPI Bus: for reading all
data from MPU and for configuring
MPU
Interrupt
Status INT
Register
CS nCS
ICM-20602 SDO SDI
Slave SPI System
Serial SPC SPC Processor
Interface SDI SDO
FIFO
Config
Register
Sensor
Register
Factory
Calibration
Bias & LDOs
VDD GND REGOUT
Figure 7. ICM-20602 Solution Using SPI Interface
4.9 SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can
be activated by means of the gyroscope and accelerometer self-test registers (registers 27 and 28).
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is
used to observe the self-test response.
The self-test response is defined as follows:
SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITH SELF-TEST DISABLED
The self-test response for each gyroscope axis is defined in the gyroscope specification table, while that for each accelerometer axis
is defined in the accelerometer specification table.
When the value of the self-test response is within the specified min/max limits of the product specification, the part has passed self-
test. When the self-test response exceeds the min/max values, the part is deemed to have failed self-test.
For further information on Self-Test please refer to sections 8 and 9 of this document.
4.10 CLOCKING
The ICM-20602 has a flexible clocking scheme, allowing a variety of internal clock sources to be used for the internal synchronous
circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various control circuits and registers. An on-chip
PLL provides flexibility in the allowable inputs for generating this clock.
Allowable internal sources for generating the internal clock are:
a) An internal relaxation oscillator
b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available source
The only setting supporting specified performance in all modes is option b). It is recommended that option b) be used.
4.11 SENSOR DATA REGISTERS
The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They are read-only
registers, and are accessed via the serial interface. Data from these registers may be read anytime.
Document Number: DS-000176 Page 21 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
4.12 FIFO
The ICM-20602 contains a 1 KB FIFO (FIFO depth 1008 bytes) register that is accessible via the Serial Interface. The FIFO
configuration register determines which data is written into the FIFO. Possible choices include gyro data, accelerometer data,
temperature readings, and FSYNC input. A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. The
FIFO register supports burst reads. The interrupt function may be used to determine when new data is available.
The ICM-20602 allows FIFO read in low-power accelerometer mode. A programmable FIFO watermark is included, with data-ready
interrupt triggered when the watermark is reached.
4.13 INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the INT and DRDY
pins configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can trigger an interrupt are
(1) Clock generator locked to new reference oscillator (used when switching clock sources); (2) new data is available to be read (from
the FIFO and Data registers); (3) accelerometer event interrupts; (4) FIFO watermark; (5) FIFO overflow. The interrupt status can be
read from the Interrupt Status register.
For further information regarding interrupts, please refer to sections 8 and 9 of this document.
4.14 DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the ICM-20602 die temperature. The readings from the ADC can be
read from the FIFO or the Sensor Data registers.
4.15 BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the ICM-20602. Its two
inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output is bypassed by a capacitor at REGOUT.
For further details on the capacitor, please refer to the Bill of Materials for External Components.
4.16 CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
4.17 STANDARD POWER MODES – UPDATE THE POWER MODES
The following table lists the user-accessible power modes for ICM-20602.
Mode Name Gyro Accel
1 Sleep Mode Off Off
2 Standby Mode Drive On Off
3 Accelerometer Low-Power Mode Off Duty-Cycled
4 Accelerometer Low-Noise Mode Off On
5 Gyroscope Low-Power Mode Duty-Cycled Off
6 Gyroscope Low-Noise Mode On Off
7 6-Axis Low-Noise Mode On On
8 6-Axis Low-Power Mode Duty-Cycled On
Table 11. Standard Power Modes for ICM-20602
Notes: Power consumption for individual modes can be found in section 0
Document Number: DS-000176 Page 22 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
5 PROGRAMMABLE INTERRUPTS
The ICM-20602 has a programmable interrupt system which can generate an interrupt signal on the INT and DRDY pins. Status flags
indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually.
Interrupt Name Module
Motion Detection Motion
FIFO Overflow FIFO
FIFO Watermark FIFO
Data Ready Sensor Registers
Table 12. Table of Interrupt Sources
For information regarding the interrupt enable/disable registers and flag registers, please refer to sections 11 and 12 of this
document. Some interrupt sources are explained below.
5.1 WAKE-ON-MOTION INTERRUPT
The ICM-20602 provides motion detection capability. A qualifying motion sample is one where the high passed sample from any axis
has an absolute value exceeding a user-programmable threshold. The following steps explain how to configure the Wake-on-Motion
Interrupt.
Step 1: Ensure that Accelerometer is running
In PWR_MGMT_1 register (0x6B) set CYCLE = 0, SLEEP = 0, and GYRO_STANDBY = 0
In PWR_MGMT_2 register (0x6C) set STBY_XA = STBY_YA = STBY_ZA = 0, and STBY_XG = STBY_YG = STBY_ZG = 1
Step 2: Accelerometer Configuration
In ACCEL_CONFIG2 register (0x1D) set ACCEL_FCHOICE_B = 1 and A_DLPF_CFG[2:0] = 1 (b001)
Step 3: Enable Motion Interrupt
In INT_ENABLE register (0x38) set WOM_X_INT_EN = WOM_Y_INT_EN = WOM_Z_INT_EN = 1 to enable motion interrupt for
X, Y, and Z axis
Step 4: Set Motion Threshold
Set the motion threshold for X-axis in ACCEL_WOM_X_THR register (0x20)
Set the motion threshold for Y-axis in ACCEL_WOM_Y_THR register (0x21)
Set the motion threshold for Z-axis in ACCEL_WOM_Z_THR register (0x22)
Step 5: Set Interrupt Mode
In ACCEL_INTEL_CTRL register (0x69) clear bit 0 (WOM_TH_MODE) to select the motion interrupt as an OR of the enabled
interrupts for X, Y, Z-axes and set bit 0 to make the interrupt an AND of the enabled interrupts for X, Y, Z axes
Step 6: Enable Accelerometer Hardware Intelligence
In ACCEL_INTEL_CTRL register (0x69) set ACCEL_INTEL_EN = ACCEL_INTEL_MODE = 1
Step 7: Set Frequency of Wake-Up
In SMPLRT_DIV register (0x19) set SMPLRT_DIV[7:0] = 3.9Hz – 500Hz
Step 8: Enable Cycle Mode (Accelerometer Low-Power Mode)
In PWR_MGMT_1 register (0x6B) set CYCLE = 1
Document Number: DS-000176 Page 23 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
6 DIGITAL INTERFACE
6.1 I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the ICM-20602 can be accessed using either I2C at 400 kHz or SPI at 10MHz. SPI operates in
four-wire mode.
Pin Number Pin Name Pin Description
2 SCL / SPC I2C serial clock (SCL); SPI serial clock (SPC)
3 SDA / SDI I2C serial data (SDA); SPI serial data input (SDI)
4 SA0 / SDO I2C Slave Address LSB (SA0); SPI serial data output (SDO)
5 CS Chip select (0 = SPI mode)
Table 13. Serial Interface
Note: To prevent switching into I2C mode when using SPI, the I2C interface should be disabled by setting the I2C_IF_DIS configuration bit at I2C_IF. Setting this bit
should be performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write” in Section 3.3.2. For further information
regarding the I2C_IF_DIS bit at I2C_IF register, please refer to sections 10 and 11 of this document.
6.2 I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-
directional. In a generalized I2C interface implementation, attached devices can be a master or a slave. The master device puts the
slave address on the bus, and the slave device with the matching address acknowledges the master.
The ICM-20602 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA
and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz.
The slave address of the ICM-20602 is b110100X which is 7 bits long. The LSB bit of the 7 bit address is determined by the logic level
on pin SA0. This allows two ICM-20602s to be connected to the same I2C bus. When used in this configuration, the address of one of
the devices should be b1101000 (pin SA0 is logic low) and the address of the other should be b1101001 (pin SA0 is logic high).
6.3 I2C COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW
transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP
condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S P
START condition STOP condition
Figure 8. START and STOP Conditions
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte
transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master,
while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the
acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL
LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and releases the clock line
(refer to the following figure).
Document Number: DS-000176 Page 24 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BY
RECEIVER (SDA)
acknowledge
SCL FROM 1 2 8 9
MASTER
START clock pulse for
condition acknowledgement
Figure 9. Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8th bit, the
read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the
master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be
followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of
the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line.
However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP
condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take
place when SCL is low, with the exception of start and stop conditions.
SDA
SCL 1–7 8 9 1–7 8 9 1–7 8 9
S P
START ADDRESS R/W ACK DATA ACK DATA ACK STOP
condition condition
Figure 10. Complete I2C Data Transfer
To write the internal ICM-20602 registers, the master transmits the start condition (S), followed by the I2C address and the write bit
(0). At the 9th clock cycle (when the clock is high), the ICM-20602 acknowledges the transfer. Then the master puts the register
address (RA) on the bus. After the ICM-20602 acknowledges the reception of the register address, the master puts the register data
onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple
bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the ICM-
20602 automatically increments the register address and loads the data to the appropriate register. The following figures show
single and two-byte write sequences.
Single-Byte Write Sequence
Master S AD+W RA DATA P
Slave ACK ACK ACK
Document Number: DS-000176 Page 25 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
Burst Write Sequence
Master S AD+W RA DATA DATA P
Slave ACK ACK ACK ACK
To read the internal ICM-20602 registers, the master sends a start condition, followed by the I2C address and a write bit, and then
the register address that is going to be read. Upon receiving the ACK signal from the ICM-20602, the master transmits a start signal
followed by the slave address and read bit. As a result, the ICM-20602 sends an ACK signal and the data. The communication ends
with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high
at the 9th clock cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master S AD+W RA S AD+R NACK P
Slave ACK ACK ACK DATA
Burst Read Sequence
Master S AD+W RA S AD+R ACK NACK P
Slave ACK ACK ACK DATA DATA
6.4 I2C TERMS
Signal Description
S Start Condition: SDA goes from high to low while SCL is high
AD Slave I2C address
W Write bit (0)
R Read bit (1)
ACK Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
NACK Not-Acknowledge: SDA line stays high at the 9th clock cycle
RA ICM-20602 internal register address
DATA Transmit or received data
P Stop condition: SDA going from low to high while SCL is high
Table 14. I2C Terms
6.5 SPI INTERFACE
SPI is a 4-wire synchronous serial interface that uses two control lines and two data lines. The ICM-20602 always operates as a Slave
device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SPC), the Serial Data Output (SDO) and the Serial Data Input (SDI) are shared
among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring
that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines
to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SPC
3. Data should be transitioned on the falling edge of SPC
4. The maximum frequency of SPC is 10MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the
SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit
and indicates the Read (1) or Write (0) operation. The following 7 bits contain the Register Address. In cases of multiple-
byte Read/Writes, data is two or more bytes:
SPI Address format
MSB LSB
R/W A6 A5 A4 A3 A2 A1 A0
Document Number: DS-000176 Page 26 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
SPI Data format
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
6. Supports Single or Burst Read/Writes.
SPC
SDI
SPI Master SDO SPI Slave 1
CS1 CS
CS2
SPC
SDI
SDO SPI Slave 2
CS
Figure 11. Typical SPI Master/Slave Configuration
Document Number: DS-000176 Page 27 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
7 SERIAL INTERFACE CONSIDERATIONS
7.1 ICM-20602 SUPPORTED INTERFACES
The ICM-20602 supports I2C communications on its serial interface. The ICM-20602’s I/O logic levels are set to be VDDIO.
The figure below depicts a sample circuit of ICM-20602. It shows the relevant logic levels and voltage connections.
VDDIO
(0V - VDDIO) SYSTEM BUS VDD_IO
System
VDD Processor IO
VDDIO
VDD INT (0V - VDDIO)
SDA (0V - VDDIO)
SCL (0V - VDDIO)
(0V - VDDIO) SYNC
VDDIO ICMICM-2-200763012A
VDDIO
(0V, VDDIO) AD0
Figure 12. I/O Levels and Connections
Document Number: DS-000176 Page 28 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
8 REGISTER MAP
The following table lists the register map for the ICM-20602. Note that all registers are accessible in all modes of device operation.
Addr Addr Register Name Serial Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(Hex) (Dec.) I/F
04 04 XG_OFFS_TC_H READ/ XG_OFFS_LP[5:0] XG_OFFS_TC_H [9:8]
WRITE
05 05 XG_OFFS_TC_L READ/ XG_OFFS_TC_L [7:0]
WRITE
07 07 YG_OFFS_TC_H READ/ YG_OFFS_LP[5:0] YG_OFFS_TC_H [9:8]
WRITE
08 08 YG_OFFS_TC_L READ/ YG_OFFS_TC_L [7:0]
WRITE
0A 10 ZG_OFFS_TC_H READ/ ZG_OFFS_LP[5:0] ZG_OFFS_TC_H [9:8]
WRITE
0B 11 ZG_OFFS_TC_L READ/ ZG_OFFS_TC_L [7:0]
WRITE
0D 13 SELF_TEST_X_ACCEL READ/ XA_ST_DATA[7:0]
WRITE
0E 14 SELF_TEST_Y_ACCEL READ/ YA_ST_DATA[7:0]
WRITE
0F 15 SELF_TEST_Z_ACCEL READ/ ZA_ST_DATA[7:0]
WRITE
13 19 XG_OFFS_USRH READ/ X_OFFS_USR [15:8]
WRITE
14 20 XG_OFFS_USRL READ/ X_OFFS_USR [7:0]
WRITE
15 21 YG_OFFS_USRH READ/ Y_OFFS_USR [15:8]
WRITE
16 22 YG_OFFS_USRL READ/ Y_OFFS_USR [7:0]
WRITE
17 23 ZG_OFFS_USRH READ/ Z_OFFS_USR [15:8]
WRITE
18 24 ZG_OFFS_USRL READ/ Z_OFFS_USR [7:0]
WRITE
19 25 SMPLRT_DIV READ/ SMPLRT_DIV[7:0]
WRITE
1A 26 CONFIG READ/ - FIFO_ EXT_SYNC_SET[2:0] DLPF_CFG[2:0]
WRITE MODE
1B 27 GYRO_CONFIG READ/ XG_ST YG_ST ZG_ST FS_SEL [1:0] - FCHOICE_B[1:0]
WRITE
1C 28 ACCEL_CONFIG READ/ XA_ST YA_ST ZA_ST ACCEL_FS_SEL[1:0] -
WRITE
1D 29 ACCEL_CONFIG 2 READ/ - DEC2_CFG ACCEL_FCH A_DLPF_CFG
WRITE OICE_B
1E 30 LP_MODE_CFG READ/ GYRO_CYC G_AVGCFG[2:0] -
WRITE LE
20 32 ACCEL_WOM_X_THR READ/ WOM_X_TH[7:0]
WRITE
21 33 ACCEL_WOM_Y_THR READ/ WOM_Y_TH[7:0]
WRITE
22 34 ACCEL_WOM_Z_THR READ/ WOM_Z_TH[7:0]
WRITE
23 35 FIFO_EN READ/ - GYRO_FIFO_EN ACCEL_FIF -
WRITE O_EN
36 54 FSYNC_INT READ to FSYNC_INT -
CLEAR
READ/ LATCH INT_RD FSYNC_INT FSYNC
37 55 INT_PIN_CFG WRITE INT_LEVEL INT_OPEN _INT_EN _CLEAR _LEVEL _INT_MODE -
_EN
READ/ WOM_X_I WOM_Y_INT WOM_Z_INT FIFO FSYNC_INT GDRIVE_INT DATA_RDY_IN
38 56 INT_ENABLE WRITE NT_EN _EN _EN _OFLOW _EN _EN - T_EN
_EN
39 57 FIFO_WM_INT_STATUS READ to - FIFO_WM_IN -
CLEAR T
Document Number: DS-000176 Page 29 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
Addr Addr Register Name Serial Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(Hex) (Dec.) I/F
READ to WOM_X_I FIFO DATA
3A 58 INT_STATUS CLEAR NT WOM_Y_INT WOM_Z_INT _OFLOW - GDRIVE_INT - _RDY_INT
_INT
3B 59 ACCEL_XOUT_H READ ACCEL_XOUT[15:8]
3C 60 ACCEL_XOUT_L READ ACCEL_XOUT[7:0]
3D 61 ACCEL_YOUT_H READ ACCEL_YOUT[15:8]
3E 62 ACCEL_YOUT_L READ ACCEL_YOUT[7:0]
3F 63 ACCEL_ZOUT_H READ ACCEL_ZOUT[15:8]
40 64 ACCEL_ZOUT_L READ ACCEL_ZOUT[7:0]
41 65 TEMP_OUT_H READ TEMP_OUT[15:8]
42 66 TEMP_OUT_L READ TEMP_OUT[7:0]
43 67 GYRO_XOUT_H READ GYRO_XOUT[15:8]
44 68 GYRO_XOUT_L READ GYRO_XOUT[7:0]
45 69 GYRO_YOUT_H READ GYRO_YOUT[15:8]
46 70 GYRO_YOUT_L READ GYRO_YOUT[7:0]
47 71 GYRO_ZOUT_H READ GYRO_ZOUT[15:8]
48 72 GYRO_ZOUT_L READ GYRO_ZOUT[7:0]
50 80 SELF_TEST_X_GYRO READ/ XG_ST_DATA[7:0]
WRITE
51 81 SELF_TEST_Y_GYRO READ/ YG_ST_DATA[7:0]
WRITE
52 82 SELF_TEST_Z_GYRO READ/ ZG_ST_DATA[7:0]
WRITE
60 96 FIFO_WM_TH1 READ/ - FIFO_WM_TH[9:8]
WRITE
61 97 FIFO_WM_TH2 READ/ FIFO_WM_TH[7:0]
WRITE
68 104 SIGNAL_PATH_RESET READ/ - ACCEL TEMP
WRITE _RST _RST
69 105 ACCEL_INTEL_CTRL READ/ ACCEL_INT ACCEL_INTEL - OUTPUT_LIMI WOM_TH_MO
WRITE EL_EN _MODE T DE
6A 106 USER_CTRL READ/ - FIFO_EN - FIFO - SIG_COND
WRITE _RST _RST
6B 107 PWR_MGMT_1 READ/ DEVICE_RE SLEEP CYCLE GYRO_ TEMP_DIS CLKSEL[2:0]
WRITE SET STANDBY
6C 108 PWR_MGMT_2 READ/ - STBY_XA STBY_YA STBY_ZA STBY_XG STBY_YG STBY_ZG
WRITE
70 112 I2C_IF READ/ - I2C_IF_DIS -
WRITE
72 114 FIFO_COUNTH READ FIFO_COUNT[15:8]
73 115 FIFO_COUNTL READ FIFO_COUNT[7:0]
74 116 FIFO_R_W READ/ FIFO_DATA[7:0]
WRITE
75 117 WHO_AM_I READ WHOAMI[7:0]
77 119 XA_OFFSET_H READ/ XA_OFFS [14:7]
WRITE
78 120 XA_OFFSET_L READ/ XA_OFFS [6:0] -
WRITE
7A 122 YA_OFFSET_H READ/ YA_OFFS [14:7]
WRITE
7B 123 YA_OFFSET_L READ/ YA_OFFS [6:0] -
WRITE
7D 125 ZA_OFFSET_H READ/ ZA_OFFS [14:7]
WRITE
7E 126 ZA_OFFSET_L READ/ ZA_OFFS [6:0] -
WRITE
Table 15. Register Map
Note: Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal register value.
Document Number: DS-000176 Page 30 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
The reset value is 0x00 for all registers other than the registers below, also the self-test registers contain pre-programmed values
and will not be 0x00 after reset.
Register 26 (0x80) CONFIG
Register 107 (0x41) Power Management 1
Register 117 (0x12) WHO_AM_I
Document Number: DS-000176 Page 31 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9 REGISTER DESCRIPTIONS
This section describes the function and contents of each register within the ICM-20602.
Note: The device will come up in sleep mode upon power-up.
9.1 REGISTER DESCRIPTIONS
Reset values are “0” for all registers, unless otherwise specified
9.2 REGISTER 04 – GYROSCOPE LOW NOISE TO LOW POWER OFFSET SHIFT AND GYROSCOPE OFFSET
TEMPERATURE COMPENSATION (TC) REGISTER
Register Name: XG_OFFS_TC_H
Register Type: READ/WRITE
Register Address: 04 (Decimal); 04 (Hex)
BIT NAME FUNCTION
Stores the offset shift in the gyroscope output from low noise mode to
[7:2] XG_OFFS_LP[5:0] low power mode to be implemented as a correction in the customer
software. 2’s complement digital code, 0.125 dps/LSB from +3.875dps
to -4dps.
[1:0] XG_OFFS_TC_H[9:8] Bits 9 and 8 of the 10-bit offset of X gyroscope (2’s complement)
9.3 REGISTER 05 – GYROSCOPE LOW NOISE TO LOW POWER OFFSET SHIFT AND GYROSCOPE OFFSET
TEMPERATURE COMPENSATION (TC) REGISTER
Register Name: XG_OFFS_TC_L
Type: READ/WRITE
Register Address: 05 (Decimal); 05 (Hex)
BIT NAME FUNCTION
[7:0] XG_OFFS_TC_L[7:0]] Bits 7 to 0 of the 10-bit offset of X gyroscope (2’s complement)
Description:
The temperature compensation (TC) registers are used to reduce gyro offset variation due to temperature change.
The TC feature is always enabled. However, the compensation only happens when a TC coefficient is programed
during factory trim which gets loaded into these registers at power up or after a DEVICE_RESET. If these registers
contain a value of zero, temperature compensation has no effect on the offset of the chip. The TC registers have a
10-bit magnitude and sign adjustment in all full scale modes with a resolution of 2.52 mdps/C steps.
If these registers contain a non-zero value after power up, the user may write zeros to them to see the offset values
without TC with temperature variation. Note that doing so may result in offset values that exceed data sheet “Initial
ZRO Tolerance” in other than normal ambient temperature (~25°C). The TC coefficients maybe restored by the user
with a power up or a DEVICE_RESET.
The above description also applies to registers 7-8 and 10-11.
9.4 REGISTER 07 – GYROSCOPE LOW NOISE TO LOW POWER OFFSET SHIFT AND GYROSCOPE OFFSET
TEMPERATURE COMPENSATION (TC) REGISTER
Register Name: YG_OFFS_TC_H
Register Type: READ/WRITE
Register Address: 07 (Decimal); 07 (Hex)
BIT NAME FUNCTION
Stores the offset shift in the gyroscope output from low noise mode to low power mode to be
[7:2] YG_OFFS_LP[5:0] implemented as a correction in the customer software. 2’s complement digital code,
0.125dps/LSB from +3.875dps to -4dps.
[1:0] YG_OFFS_TC_H[9:8] Bits 9 and 8 of the 10-bit offset of Y gyroscope (2’s complement)
Document Number: DS-000176 Page 32 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9.5 REGISTER 08 – GYROSCOPE LOW NOISE TO LOW POWER OFFSET SHIFT AND GYROSCOPE OFFSET
TEMPERATURE COMPENSATION (TC) REGISTER
Register Name: YG_OFFS_TC_L
Register Type: READ/WRITE
Register Address: 08 (Decimal); 08 (Hex)
BIT NAME FUNCTION
[7:0] YG_OFFS_TC_L[7:0]] Bits 7 to 0 of the 10-bit offset of Y gyroscope (2’s complement)
9.6 REGISTER 10 – GYROSCOPE LOW NOISE TO LOW POWER OFFSET SHIFT AND GYROSCOPE OFFSET
TEMPERATURE COMPENSATION (TC) REGISTER
Register Name: ZG_OFFS_TC_H
Register Type: READ/WRITE
Register Address: 10 (Decimal); 0A (Hex)
BIT NAME FUNCTION
Stores the offset shift in the gyroscope output from low noise mode to low power mode
[7:2] ZG_OFFS_LP[5:0] to be implemented as a correction in the customer software. 2’s complement digital
code, 0.125dps/LSB from +3.875dps to -4dps.
[1:0] ZG_OFFS_TC_H[9:8] Bits 9 and 8 of the 10-bit offset of Z gyroscope (2’s complement)
9.7 REGISTER 11 – GYROSCOPE LOW NOISE TO LOW POWER OFFSET SHIFT AND GYROSCOPE OFFSET
TEMPERATURE COMPENSATION (TC) REGISTER
Register Name: ZG_OFFS_TC_L
Register Type: READ/WRITE
Register Address: 11 (Decimal); 0B (Hex)
BIT NAME FUNCTION
[7:0] ZG_OFFS_TC_L[7:0]] Bits 7 to 0 of the 10-bit offset of Z gyroscope (2’s complement)
Document Number: DS-000176 Page 33 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9.8 REGISTERS 13 TO 15 ACCELEROMETER SELF-TEST REGISTERS
Register Name: SELF_TEST_X_ACCEL, SELF_TEST_Y_ACCEL, SELF_TEST_Z_ACCEL
Type: READ/WRITE
Register Address: 13, 14, 15 (Decimal); 0D, 0E, 0F (Hex)
REGISTER BIT NAME FUNCTION
The value in this register indicates the self-test output generated
SELF_TEST_X_ACCEL [7:0] XA_ST_DATA[7:0] during manufacturing tests. This value is to be used to check
against subsequent self-test outputs performed by the end user.
The value in this register indicates the self-test output generated
SELF_TEST_Y_ACCEL [7:0] YA_ST_DATA[7:0] during manufacturing tests. This value is to be used to check
against subsequent self-test outputs performed by the end user.
The value in this register indicates the self-test output generated
SELF_TEST_Z_ACCEL [7:0] ZA_ST_DATA[7:0] during manufacturing tests. This value is to be used to check
against subsequent self-test outputs performed by the end user.
The equation to convert self-test codes in OTP to factory self-test measurement is:
ST _ OTP (2620 / 2FS ) *1.01(ST _code1) (lsb)
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the Self-Test value
(ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following equation:
ST _ code round(log( ST _ FAC /(2620 / 2FS ))) 1
log(1.01)
9.9 REGISTER 19 – X-GYRO OFFSET ADJUSTMENT REGISTER: HIGH BYTE
Register Name: XG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 19 (Decimal); 13 (Hex)
BIT NAME FUNCTION
Bits 15 to 8 of the 16-bit offset of X gyroscope (2’s complement). This register is used to
[7:0] X_OFFS_USR[15:8] remove DC bias from the sensor output. The value in this register is added to the
gyroscope sensor value before going into the sensor register.
9.10 REGISTER 20 – X-GYRO OFFSET ADJUSTMENT REGISTER: LOW BYTE
Register Name: XG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 20 (Decimal); 14 (Hex)
BIT NAME FUNCTION
Bits 7 to 0 of the 16-bit offset of X gyroscope (2’s complement). This register is used to
[7:0] X_OFFS_USR[7:0] remove DC bias from the sensor output. The value in this register is added to the
gyroscope sensor value before going into the sensor register.
Document Number: DS-000176 Page 34 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9.11 REGISTER 21 – Y-GYRO OFFSET ADJUSTMENT REGISTER: HIGH BYTE
Register Name: YG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 21 (Decimal); 15 (Hex)
BIT NAME FUNCTION
Bits 15 to 8 of the 16-bit offset of Y gyroscope (2’s complement). This register is
[7:0] Y_OFFS_USR[15:8] used to remove DC bias from the sensor output. The value in this register is added
to the gyroscope sensor value before going into the sensor register.
9.12 REGISTER 22 – Y-GYRO OFFSET ADJUSTMENT REGISTER: LOW BYTE
Register Name: YG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 22 (Decimal); 16 (Hex)
BIT NAME FUNCTION
Bits 7 to 0 of the 16-bit offset of Y gyroscope (2’s complement). This
[7:0] Y_OFFS_USR[7:0] register is used to remove DC bias from the sensor output. The value
in this register is added to the gyroscope sensor value before going
into the sensor register.
9.13 REGISTER 23 – Z-GYRO OFFSET ADJUSTMENT REGISTER: HIGH BYTE
Register Name: ZG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 23 (Decimal); 17 (Hex)
BIT NAME FUNCTION
Bits 15 to 8 of the 16-bit offset of Z gyroscope (2’s complement). This
[7:0] Z_OFFS_USR[15:8] register is used to remove DC bias from the sensor output. The value
in this register is added to the gyroscope sensor value before going
into the sensor register.
9.14 REGISTER 24 – Z-GYRO OFFSET ADJUSTMENT REGISTER: LOW BYTE
Register Name: ZG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 24 (Decimal); 18 (Hex)
BIT NAME FUNCTION
Bits 7 to 0 of the 16-bit offset of Z gyroscope (2’s
complement). This register is used to remove DC bias from
[7:0] Z_OFFS_USR[7:0] the sensor output. The value in this register is added to the
gyroscope sensor value before going into the sensor
register.
Document Number: DS-000176 Page 35 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9.15 REGISTER 25 – SAMPLE RATE DIVIDER
Register Name: SMPLRT_DIV
Register Type: READ/WRITE
Register Address: 25 (Decimal); 19 (Hex)
BIT NAME FUNCTION
Divides the internal sample rate (see register CONFIG) to generate the
sample rate that controls sensor data output rate, FIFO sample rate.
NOTE: This register is only effective when FCHOICE_B register bits are 2’b00, and
[7:0] SMPLRT_DIV[7:0] (0 < DLPF_CFG < 7).
This is the update rate of the sensor register:
SAMPLE_RATE = INTERNAL_SAMPLE_RATE / (1 + SMPLRT_DIV)
Where INTERNAL_SAMPLE_RATE = 1 kHz
9.16 REGISTER 26 – CONFIGURATION
Register Name: CONFIG
Register Type: READ/WRITE
Register Address: 26 (Decimal); 1A (Hex)
BIT NAME FUNCTION
[7] - Default configuration value is 1. User should set it to 0.
[6] FIFO_MODE When set to ‘1’, when the FIFO is full, additional writes will not be
written to FIFO.
When set to ‘0’, when the FIFO is full, additional writes will be written
to the FIFO, replacing the oldest data.
[5:3] EXT_SYNC_SET[2:0] Enables the FSYNC pin data to be sampled.
EXT_SYNC_SET FSYNC bit location
0 function disabled
1 TEMP_OUT_L[0]
2 GYRO_XOUT_L[0]
3 GYRO_YOUT_L[0]
4 GYRO_ZOUT_L[0]
5 ACCEL_XOUT_L[0]
6 ACCEL_YOUT_L[0]
7 ACCEL_ZOUT_L[0]
FSYNC will be latched to capture short strobes. This will be done such
that if FSYNC toggles, the latched value toggles, but won’t toggle again
until the new latched value is captured by the sample rate strobe.
[2:0] DLPF_CFG[2:0] For the DLPF to be used, FCHOICE_B[1:0] is 2’b00.
See the table below.
The DLPF is configured by DLPF_CFG, when FCHOICE_B [1:0] = 2b’00. The gyroscope and temperature sensor are filtered
according to the value of DLPF_CFG and FCHOICE_B as shown in the table below.
Document Number: DS-000176 Page 36 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
FCHOICE_B Gyroscope Temperature
DLPF_CFG Sensor
3-dB BW Noise BW Rate 3-dB BW (Hz)
(Hz) (Hz) (kHz)
X 1 X 8173 8595.1 32 4000
1 0 X 3281 3451.0 32 4000
0 0 0 250 306.6 8 4000
0 0 1 176 177.0 1 188
0 0 2 92 108.6 1 98
0 0 3 41 59.0 1 42
0 0 4 20 30.5 1 20
0 0 5 10 15.6 1 10
0 0 6 5 8.0 1 5
0 0 7 3281 3451.0 8 4000
9.17 REGISTER 27 – GYROSCOPE CONFIGURATION
Register Name: GYRO_CONFIG
Register Type: READ/WRITE
Register Address: 27 (Decimal); 1B (Hex)
BIT NAME FUNCTION
[7] XG_ST X Gyro self-test
[6] YG_ST Y Gyro self-test
[5] ZG_ST Z Gyro self-test
Gyro Full Scale Select:
00 = ±250 dps
[4:3] FS_SEL[1:0] 01= ±500 dps
10 = ±1000 dps
11 = ±2000 dps
[2] - Reserved
[1:0] FCHOICE_B[1:0] Used to bypass DLPF as shown in table 1 above.
9.18 REGISTER 28 – ACCELEROMETER CONFIGURATION
Register Name: ACCEL_CONFIG
Register Type: READ/WRITE
Register Address: 28 (Decimal); 1C (Hex)
BIT NAME FUNCTION
[7] XA_ST X Accel self-test
[6] YA_ST Y Accel self-test
[5] ZA_ST Z Accel self-test
[4:3] ACCEL_FS_SEL[1:0] Accel Full Scale Select:
±2g (00), ±4g (01), ±8g (10), ±16g (11)
[2:0] - Reserved
Document Number: DS-000176 Page 37 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9.19 REGISTER 29 – ACCELEROMETER CONFIGURATION 2
Register Name: ACCEL_CONFIG2
Register Type: READ/WRITE
Register Address: 29 (Decimal); 1D (Hex)
BIT NAME FUNCTION
Averaging filter settings for Low Power Accelerometer mode:
0 = Average 4 samples
[5:4] DEC2_CFG[1:0] 1 = Average 8 samples
2 = Average 16 samples
3 = Average 32 samples
[3] ACCEL_FCHOICE_B Used to bypass DLPF as shown in the table below.
[2:0] A_DLPF_CFG Accelerometer low pass filter setting as shown in table 2 below.
Accelerometer Data Rates and Bandwidths (Low-Noise Mode)
Accelerometer
ACCEL_FCHOICE_B A_DLPF_CFG 3-dB BW Noise BW Rate
(Hz) (Hz) (kHz)
1 X 1046.0 1100.0 4
0 0 218.1 235.0 1
0 1 218.1 235.0 1
0 2 99.0 121.3 1
0 3 44.8 61.5 1
0 4 21.2 31.0 1
0 5 10.2 15.5 1
0 6 5.1 7.8 1
0 7 420.0 441.6 1
The data output rate of the DLPF filter block can be further reduced by a factor of 1/(1+SMPLRT_DIV), where SMPLRT_DIV is an 8-bit
integer. Following is a small subset of ODRs that are configurable for the accelerometer in the low-noise mode in this manner (Hz):
3.91, 7.81, 15.63, 31.25, 62.50, 125, 250, 500, 1K
The following table lists the approximate accelerometer filter bandwidths available in the low-power mode of operation for some
example ODRs.
In the low-power mode of operation, the accelerometer is duty-cycled. The following table shows some example configurations for
accelerometer low power mode.
Document Number: DS-000176 Page 38 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
Averages 1x 4x 8x 16x 32x
ACCEL_FCHOICE_B 1 0 0 0 0
DEC2_CFG X 0 1 2 3
A_DLPF_CFG X 7 7 7 7
Ton (ms) 1.084 1.84 2.84 4.84 8.84
NBW (Hz) 1100 442 236 122 62
3-dB BW (Hz) 1046 420 219 111 56
Noise TYP 3.3 2.1 1.5 1.1 0.79
(mg-rms)
SMPLRT_DIV ODR Low-Power Accelerometer Mode Current Consumption (µA)
(Hz)
255 3.91 9.4 10.2 11.5 13.8 18.5
127 7.81 10.7 12.4 14.7 19.6 28.9
99 10 11.4 13.7 16.6 22.6 34.7
63 15.63 13.3 16.7 21.5 30.8 49.7
31 31.25 18.3 25.4 34.8 53.6 91.2
19 50 24.4 35.8 50.8 80.8 141.1
15 62.5 28.4 42.7 61.5 99.0 174.3
9 100 40.7 63.5 93.6 153.7 303.3
7 125 48.8 77.4 114.8 190.1 N/A
4 200 73.4 118.8 178.9 299.3
3 250 89.6 146.5 221.6 N/A
1 500 171.1 284.9 N/A
9.20 REGISTER 30 – GYROSCOPE LOW POWER MODE CONFIGURATION
Register Name: LP_MODE_CFG
Register Type: READ/WRITE
Register Address: 30 (Decimal); 1E (Hex)
BIT NAME FUNCTION
[7] GYRO_CYCLE When set to ‘1’ low-power gyroscope mode is enabled. Default setting is ‘0’
[6:4] G_AVGCFG[2:0] Averaging filter configuration for low-power gyroscope mode. Default setting is ‘000’
[3:0] - Reserved
To operate in gyroscope low-power mode or 6-axis low-power mode, GYRO_CYCLE should be set to ‘1.’ Gyroscope filter
configuration is determined by G_AVGCFG[2:0] that sets the averaging filter configuration. It is not dependent on DLPF_CFG[2:0].
The following table shows some example configurations for gyroscope low power mode.
Document Number: DS-000176 Page 39 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
Averages 1x 2x 4x 8x 16x 32x 64x 128x
G_AVGCFG 0 1 2 3 4 5 6 7
NBW (Hz) 650.8 407.1 224.2 117.4 60.2 30.6 15.6 8.0
3-dB BW (Hz) 622 391 211 108 54 27 14 7
Noise TYP
(dps-rms) 0.10 0.08 0.06 0.04 0.03 0.02 0.016 0.011
SMPLRT_DIV ODR (Hz) Low-Power Gyroscope Mode Current Consumption (mA)
255 3.9 0.79 0.80 0.80 0.82 0.85 0.90 1.01 1.23
99 10.0 0.81 0.82 0.84 0.87 0.95 1.09 1.37 1.94
65 15.2 0.83 0.84 0.87 0.92 1.03 1.24 1.67 2.53
64 15.4 0.83 0.84 0.87 0.92 1.03 1.25 1.69 N/A
33 29.4 0.87 0.90 0.95 1.05 1.26 1.68 2.51 N/A
32 30.3 0.87 0.90 0.95 1.06 1.28 1.70 N/A N/A
19 50.0 0.93 0.98 1.06 1.24 1.60 2.30 N/A N/A
17 55.6 0.95 1.00 1.10 1.29 1.69 2.47 N/A N/A
16 58.8 0.96 1.01 1.11 1.32 1.74 N/A N/A N/A
9 100.0 1.08 1.17 1.35 1.70 2.41 N/A N/A N/A
7 125.0 1.16 1.27 1.49 1.93 N/A N/A N/A N/A
6 142.9 1.21 1.34 1.59 2.09 N/A N/A N/A N/A
4 200.0 1.38 1.56 1.91 N/A N/A N/A N/A N/A
3 250.0 1.53 1.75 2.19 N/A N/A N/A N/A N/A
2 333.3 1.78 2.07 N/A N/A N/A N/A N/A N/A
9.21 REGISTER 32 – WAKE-ON MOTION THRESHOLD: X-AXIS ACCELEROMETER
Register Name: ACCEL_WOM_X_THR
Register Type: READ/WRITE
Register Address: 32 (Decimal); 20 (Hex)
BIT NAME FUNCTION
[7:0] WOM_X_TH[7:0] This register holds the threshold value for the Wake on Motion Interrupt for X-axis
accelerometer.
9.22 REGISTER 33 – WAKE-ON MOTION THRESHOLD: Y-AXIS ACCELEROMETER
Register Name: ACCEL_WOM_Y_THR
Register Type: READ/WRITE
Register Address: 33 (Decimal); 21 (Hex)
BIT NAME FUNCTION
[7:0] WOM_Y_TH[7:0] This register holds the threshold value for the Wake on Motion Interrupt for Y-axis
accelerometer.
9.23 REGISTER 34 – WAKE-ON MOTION THRESHOLD: Z-AXIS ACCELEROMETER
Register Name: ACCEL_WOM_Z_THR
Register Type: READ/WRITE
Register Address: 34 (Decimal); 22 (Hex)
BIT NAME FUNCTION
[7:0] WOM_Z_TH[7:0] This register holds the threshold value for the Wake on Motion Interrupt for Z-axis
accelerometer.
Document Number: DS-000176 Page 40 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9.24 REGISTER 35 – FIFO ENABLE
Register Name: FIFO_EN
Register Type: READ/WRITE
Register Address: 35 (Decimal); 23 (Hex)
BIT NAME FUNCTION
[7:5] - Reserved
1 – write TEMP_OUT_H, TEMP_OUT_L, GYRO_XOUT_H, GYRO_XOUT_L, GYRO_YOUT_H,
[4] GYRO_FIFO_EN GYRO_YOUT_L, GYRO_ZOUT_H, and GYRO_ZOUT_L to the FIFO at the sample rate; If
enabled, buffering of data occurs even if data path is in standby.
0 – function is disabled
1 – write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L,
[3] ACCEL_FIFO_EN ACCEL_ZOUT_H, ACCEL_ZOUT_L, TEMP_OUT_H, and TEMP_OUT_L to the FIFO at the
sample rate;
0 – function is disabled
[2:0] - Reserved
NOTE: If both GYRO_FIFO_EN And ACCEL_FIFO_EN are 1, write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L, ACCEL_ZOUT_H, ACCEL_ZOUT_L,
TEMP_OUT_H, TEMP_OUT_L, GYRO_XOUT_H, GYRO_XOUT_L, GYRO_YOUT_H, GYRO_YOUT_L, GYRO_ZOUT_H, and GYRO_ZOUT_L to the FIFO at the sample rate.
9.25 REGISTER 54 – FSYNC INTERRUPT STATUS
Register Name: FSYNC_INT
Register Type: READ to CLEAR
Register Address: 54 (Decimal); 36 (Hex)
BIT NAME FUNCTION
[7] FSYNC_INT This bit automatically sets to 1 when a FSYNC interrupt has been generated. The bit clears
to 0 after the register has been read.
9.26 REGISTER 55 – INT/DRDY PIN / BYPASS ENABLE CONFIGURATION
Register Name: INT_PIN_CFG
Register Type: READ/WRITE
Register Address: 55 (Decimal); 37 (Hex)
BIT NAME FUNCTION
[7] INT_LEVEL 1 – The logic level for INT/DRDY pin is active low.
0 – The logic level for INT/DRDY pin is active high.
[6] INT_OPEN 1 – INT/DRDY pin is configured as open drain.
0 – INT/DRDY pin is configured as push-pull.
[5] LATCH_INT_EN 1 – INT/DRDY pin level held until interrupt status is cleared.
0 – INT/DRDY pin indicates interrupt pulse’s width is 50us.
[4] INT_RD_CLEAR 1 – Interrupt status is cleared if any read operation is performed.
0 – Interrupt status is cleared only by reading INT_STATUS register
[3] FSYNC_INT_LEVEL 1 – The logic level for the FSYNC pin as an interrupt is active low.
0 – The logic level for the FSYNC pin as an interrupt is active high.
When this bit is equal to 1, the FSYNC pin will trigger an interrupt when it transitions to the
[2] FSYNC_INT_MODE_EN level specified by FSYNC_INT_LEVEL. When this bit is equal to 0, the FSYNC pin is disabled
from causing an interrupt.
[1:0] - Reserved.
Document Number: DS-000176 Page 41 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9.27 REGISTER 57 – FIFO WATERMARK INTERRUPT STATUS
Register Name: FIFO_WM_INT_STATUS
Register Type: READ to CLEAR
Register Address: 57 (Decimal); 39 (Hex)
BIT NAME FUNCTION
[6] FIFO_WM_INT FIFO Watermark interrupt status. Cleared on Read.
9.28 REGISTER 58 – INTERRUPT STATUS
Register Name: INT_STATUS
Register Type: READ to CLEAR
Register Address: 58 (Decimal); 3A (Hex)
BIT NAME FUNCTION
[7] WOM_X_INT X-axis accelerometer WoM interrupt status. Cleared on Read.
[6] WOM_Y_INT Y-axis accelerometer WoM interrupt status. Cleared on Read.
[5] WOM_Z_INT Z-axis accelerometer WoM interrupt status. Cleared on Read.
[4] FIFO_OFLOW_INT This bit automatically sets to 1 when a FIFO buffer overflow has been generated. The bit
clears to 0 after the register has been read.
[3] - Reserved.
[2] GDRIVE_INT Gyroscope Drive System Ready interrupt
[1] - Reserved
[0] DATA_RDY_INT This bit automatically sets to 1 when a Data Ready interrupt is generated. The bit clears to
0 after the register has been read.
9.29 REGISTERS 59 TO 64 – ACCELEROMETER MEASUREMENTS: X-AXIS HIGH BYTE
Register Name: ACCEL_XOUT_H
Register Type: READ only
Register Address: 59 (Decimal); 3B (Hex)
BIT NAME FUNCTION
[7:0] ACCEL_XOUT[15:8] High byte of accelerometer x-axis data.
Register Name: ACCEL_XOUT_L
Register Type: READ only
Register Address: 60 (Decimal); 3C (Hex)
BIT NAME FUNCTION
[7:0] ACCEL_XOUT[7:0] Low byte of accelerometer x-axis data.
Register Name: ACCEL_YOUT_H
Register Type: READ only
Register Address: 61 (Decimal); 3D (Hex)
BIT NAME FUNCTION
[7:0] ACCEL_YOUT[15:8] High byte of accelerometer y-axis data.
Register Name: ACCEL_YOUT_L
Register Type: READ only
Register Address: 62 (Decimal); 3E (Hex)
BIT NAME FUNCTION
[7:0] ACCEL_YOUT[7:0] Low byte of accelerometer y-axis data.
Document Number: DS-000176 Page 42 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
Register Name: ACCEL_ZOUT_H
Register Type: READ only
Register Address: 63 (Decimal); 3F (Hex)
BIT NAME FUNCTION
[7:0] ACCEL_ZOUT[15:8] High byte of accelerometer z-axis data.
Register Name: ACCEL_ZOUT_L
Register Type: READ only
Register Address: 64 (Decimal); 40 (Hex)
BIT NAME FUNCTION
[7:0] ACCEL_ZOUT[7:0] Low byte of accelerometer z-axis data.
9.30 REGISTERS 65 TO 66 – TEMPERATURE MEASUREMENT
Register Name: TEMP_OUT_H
Register Type: READ only
Register Address: 65 (Decimal); 41 (Hex)
BIT NAME FUNCTION
[7:0] TEMP_OUT[15:8] Low byte of the temperature sensor output
Register Name: TEMP_OUT_L
Register Type: READ only
Register Address: 66 (Decimal); 42 (Hex)
BIT NAME FUNCTION
High byte of the temperature sensor output
TEMP_degC = (TEMP_OUT[15:0]/Temp_Sensitivity) +
[7:0] TEMP_OUT[7:0] RoomTemp_Offset
where Temp_Sensitivity = 326.8 LSB/ºC and
RoomTemp_Offset = 25ºC
9.31 REGISTERS 67 TO 72 – GYROSCOPE MEASUREMENT
Register Name: GYRO_XOUT_H
Register Type: READ only
Register Address: 67 (Decimal); 43 (Hex)
BIT NAME FUNCTION
[7:0] GYRO_XOUT[15:8] High byte of the X-Axis gyroscope output
Register Name: GYRO_XOUT_L
Register Type: READ only
Register Address: 68 (Decimal); 44 (Hex)
BIT NAME FUNCTION
Low byte of the X-Axis gyroscope output
[7:0] GYRO_XOUT[7:0] GYRO_XOUT = Gyro_Sensitivity * X_angular_rate
Nominal FS_SEL = 0
Conditions Gyro_Sensitivity = 131 LSB/(º/s)
Register Name: GYRO_YOUT_H
Register Type: READ only
Register Address: 69 (Decimal); 45 (Hex)
BIT NAME FUNCTION
[7:0] GYRO_YOUT[15:8] High byte of the Y-Axis gyroscope output
Document Number: DS-000176 Page 43 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
Register Name: GYRO_YOUT_L
Register Type: READ only
Register Address: 70 (Decimal); 46 (Hex)
BIT NAME FUNCTION
Low byte of the Y-Axis gyroscope output
[7:0] GYRO_YOUT[7:0] GYRO_YOUT = Gyro_Sensitivity * Y_angular_rate
Nominal FS_SEL = 0
Conditions Gyro_Sensitivity = 131 LSB/(º/s)
Register Name: GYRO_ZOUT_H
Register Type: READ only
Register Address: 71 (Decimal); 47 (Hex)
BIT NAME FUNCTION
[7:0] GYRO_ZOUT[15:8] High byte of the Z-Axis gyroscope output
Register Name: GYRO_ZOUT_L
Register Type: READ only
Register Address: 72 (Decimal); 48 (Hex)
BIT NAME FUNCTION
Low byte of the Z-Axis gyroscope output
[7:0] GYRO_ZOUT[7:0] GYRO_ZOUT = Gyro_Sensitivity * Z_angular_rate
Nominal FS_SEL = 0
Conditions Gyro_Sensitivity = 131 LSB/(º/s)
9.32 REGISTER 80 TO 82 – GYROSCOPE SELF-TEST REGISTERS
Register Name: SELF_TEST_X_GYRO, SELF_TEST_Y_GYRO, SELF_TEST_Z_GYRO
Type: READ/WRITE
Register Address: 80, 81, 82 (Decimal); 50, 51, 52 (Hex)
REGISTER BIT NAME FUNCTION
The value in this register indicates the self-test output generated during
SELF_TEST_X_GYRO [7:0] XG_ST_DATA[7:0] manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
The value in this register indicates the self-test output generated during
SELF_TEST_Y_GYRO [7:0] YG_ST_DATA[7:0] manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
The value in this register indicates the self-test output generated during
SELF_TEST_Z_GYRO [7:0] ZG_ST_DATA[7:0] manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
The equation to convert self-test codes in OTP to factory self-test measurement is:
ST _ OTP (2620 / 2FS ) *1.01(ST _code1) (lsb)
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the Self-Test value
(ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following equation:
ST _ code round(log( ST _ FAC /(2620 / 2FS ))) 1
log(1.01)
Document Number: DS-000176 Page 44 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9.33 REGISTER 96 TO 97 – FIFO WATERMARK THRESHOLD IN NUMBER OF BYTES
Register Name: FIFO_WM_TH1
Register Type: READ/WRITE
Register Address: 96 (Decimal); 60 (Hex)
BIT NAME FUNCTION
[1:0] FIFO_WM_TH[9:8] FIFO watermark threshold in number of bytes. Watermark interrupt is
disabled if the threshold is set to “0”. Default value is 00000000.
Register Name: FIFO_WM_TH2
Register Type: READ/WRITE
Register Address: 97 (Decimal); 61 (Hex)
BIT NAME FUNCTION
[7:0] FIFO_WM_TH[7:0] FIFO watermark threshold in number of bytes. Watermark interrupt is
disabled if the threshold is set to “0”. Default value is 00000000.
The register FIFO_WM_TH[9:0] sets the FIFO watermark threshold level (0 - 1023). User should ensure that bit 7 of register 0x1A is
set to 0 before using this feature. When the FIFO count is at or above the watermark level (FIFO_COUNT[15:0] ≥ FIFO_WM_TH[9:0])
and the system is not in the middle of a FIFO read, an interrupt is triggered. The interrupt will set the FIFO watermark interrupt
status register field FIFO_WM_INT = 1, and the INT pin will issue a pulse if configured in pulse mode, or set to the active level if
configured in latch mode. Register bit FIFO_WM_INT is not read-to-clear, unlike the other interrupts. Rather, whenever FIFO_R_W
register is read, FIFO_WM_INT status bit is cleared automatically. At the same time, the INT pin will be cleared as well if it is
configured in latch mode.
The FIFO watermark interrupt and the INT pin are cleared upon the first read (and only the first read) of the FIFO. If, at the end of
the FIFO read, the FIFO count is at or above the watermark level, the interrupt status bit and INT pin will again be set. If the INT pin is
configured for latched operation, it will wait until the host completes the read to set to the active level.
9.34 REGISTER 104 – SIGNAL PATH RESET
Register Name: SIGNAL_PATH_RESET
Register Type: READ/WRITE
Register Address: 104 (Decimal); 68 (Hex)
BIT NAME FUNCTION
[7:2] - Reserved
[1] ACCEL_RST Reset accel digital signal path. NOTE: Sensor registers are not cleared. Use SIG_COND_RST to
clear sensor registers.
[0] TEMP_RST Reset temp digital signal path. NOTE: Sensor registers are not cleared. Use SIG_COND_RST to
clear sensor registers.
9.35 REGISTER 105 – ACCELEROMETER INTELLIGENCE CONTROL
Register Name: ACCEL_INTEL_CTRL
Register Type: READ/WRITE
Register Address: 105 (Decimal); 69 (Hex)
BIT NAME FUNCTION
[7] ACCEL_INTEL_EN This bit enables the Wake-on-Motion detection logic
[6] ACCEL_INTEL_MODE 0 – Do not use
1 – Compare the current sample with the previous sample
[5:2] - Reserved
[1] OUTPUT_LIMIT To avoid limiting sensor output to less than 0x7FFF, set this bit to 1. This should be done
every time the ICM-20602 is powered up.
0 – Set WoM interrupt on the OR of all enabled accelerometer thresholds
[0] WOM_TH_MODE 1 – Set WoM interrupt on the AND of all enabled accelerometer threshold
Default setting is 0
Document Number: DS-000176 Page 45 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9.36 REGISTER 106 – USER CONTROL
Register Name: USER_CTRL
Register Type: READ/WRITE
Register Address: 106 (Decimal); 6A (Hex)
BIT NAME FUNCTION
[7] - Reserved
[6] FIFO_EN 1 – Enable FIFO operation mode.
0 – Disable FIFO access from serial interface.
[5] - Reserved
[4] - Reserved
[3] - Reserved
[2] FIFO_RST 1 – Reset FIFO module. Reset is asynchronous. This bit auto clears after one clock cycle of
the internal 20 MHz clock.
[1] - Reserved
[0] SIG_COND_RST 1 – Reset all gyro digital signal path, accel digital signal path, and temp digital signal path.
This bit also clears all the sensor registers.
9.37 REGISTER 107 – POWER MANAGEMENT 1
Register Name: PWR_MGMT_1
Register Type: READ/WRITE
Register Address: 107 (Decimal); 6B (Hex)
BIT NAME FUNCTION
[7] DEVICE_RESET 1 – Reset the internal registers and restores the default settings. The bit automatically clears
to 0 once the reset is done.
[6] SLEEP When set to 1, the chip is set to sleep mode.
When set to 1, and SLEEP and STANDBY are not set to 1, the chip will cycle between sleep
and taking a single accelerometer sample at a rate determined by SMPLRT_DIV
[5] CYCLE NOTE: When all accelerometer axes are disabled via PWR_MGMT_2 register bits and cycle is enabled,
the chip will wake up at the rate determined by the respective registers above, but will not take any
samples.
[4] GYRO_STANDBY When set, the gyro drive and pll circuitry are enabled, but the sense paths are disabled. This
is a low power mode that allows quick enabling of the gyros.
[3] TEMP_DIS When set to 1, this bit disables the temperature sensor.
Code Clock Source
0 Internal 20 MHz oscillator
1 Auto selects the best available clock source – PLL if ready, else use the Internal
oscillator
2 Auto selects the best available clock source – PLL if ready, else use the Internal
oscillator
[2:0] CLKSEL[2:0] 3 Auto selects the best available clock source – PLL if ready, else use the Internal
oscillator
4 Auto selects the best available clock source – PLL if ready, else use the Internal
oscillator
5 Auto selects the best available clock source – PLL if ready, else use the Internal
oscillator
6 Internal 20 MHz oscillator
7 Stops the clock and keeps timing generator in reset
NOTE: The default value of CLKSEL[2:0] is 001. It is required that CLKSEL[2:0] be set to 001 to achieve full gyroscope performance.
Document Number: DS-000176 Page 46 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9.38 REGISTER 108 – POWER MANAGEMENT 2
Register Name: PWR_MGMT_2
Register Type: READ/WRITE
Register Address: 108 (Decimal); 6C (Hex)
BIT NAME FUNCTION
[7] - Reserved
[6] - Reserved
[5] STBY_XA 1 – X accelerometer is disabled
0 – X accelerometer is on
[4] STBY_YA 1 – Y accelerometer is disabled
0 – Y accelerometer is on
[3] STBY_ZA 1 – Z accelerometer is disabled
0 – Z accelerometer is on
[2] STBY_XG 1 – X gyro is disabled
0 – X gyro is on
[1] STBY_YG 1 – Y gyro is disabled
0 – Y gyro is on
[0] STBY_ZG 1 – Z gyro is disabled
0 – Z gyro is on
9.39 REGISTER 112 – I2C INTERFACE
Register Name: I2C_IF
Register Type: READ/WRITE
Register Address: 112 (Decimal); 70 (Hex)
BIT NAME FUNCTION
[7] - Reserved
[6] I2C_IF_DIS 1 – Disable I2C Slave module and put the serial interface in SPI mode only.
[5:0] - Reserved
9.40 REGISTER 114 AND 115 – FIFO COUNT REGISTERS
Register Name: FIFO_COUNTH
Register Type: READ Only
Register Address: 114 (Decimal); 72 (Hex)
BIT NAME FUNCTION
[7:0] FIFO_COUNT[15:8] High Bits, count indicates the number of written bytes in the FIFO.
Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL.
Register Name: FIFO_COUNTL
Register Type: READ Only
Register Address: 115 (Decimal); 73 (Hex)
BIT NAME FUNCTION
[7:0] FIFO_COUNT[7:0] Low Bits, count indicates the number of written bytes in the FIFO. NOTE: Must read
FIFO_COUNTL to latch new data for both FIFO_COUNTH and FIFO_COUNTL.
Document Number: DS-000176 Page 47 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9.41 REGISTER 116 – FIFO READ WRITE
Register Name: FIFO_R_W
Register Type: READ/WRITE
Register Address: 116 (Decimal); 74 (Hex)
BIT NAME FUNCTION
[7:0] FIFO_DATA[7:0] Read/Write command provides Read or Write operation for the FIFO.
Description:
This register is used to read and write data from the FIFO buffer.
Data is written to the FIFO in order of register number (from lowest to highest). If all the FIFO enable flags (see below) are enabled,
the contents of registers 59 through 72 will be written in order at the Sample Rate.
The contents of the sensor data registers (Registers 59 to 72) are written into the FIFO buffer when their corresponding FIFO enable
flags are set to 1 in FIFO_EN (Register 35).
If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is automatically set to 1. This bit is located in INT_STATUS
(Register 58). When the FIFO buffer has overflowed, the oldest data will be lost and new data will be written to the FIFO unless
register 26 CONFIG, bit[6] FIFO_MODE = 1.
If the FIFO buffer is empty, reading register FIFO_DATA will return a unique value of 0xFF until new data is available. Normal data is
precluded from ever indicating 0xFF, so 0xFF gives a trustworthy indication of FIFO empty.
9.42 REGISTER 117 – WHO AM I
Register Name: WHO_AM_I
Register Type: READ only
Register Address: 117 (Decimal); 75 (Hex)
BIT NAME FUNCTION
[7:0] WHOAMI Register to indicate to user which device is being accessed.
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default value of the
register is 0x12. This is different from the I2C address of the device as seen on the slave I2C controller by the applications processor.
The I2C address of the ICM-20602 is 0x68 or 0x69 depending upon the value driven on AD0 pin.
Document Number: DS-000176 Page 48 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
9.43 REGISTERS 119, 120, 122, 123, 125, 126 – ACCELEROMETER OFFSET REGISTERS
Register Name: XA_OFFSET_H
Register Type: READ/WRITE
Register Address: 119 (Decimal); 77 (Hex)
BIT NAME FUNCTION
[7:0] XA_OFFS[14:7] Upper bits of the X accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps
Register Name: XA_OFFSET_L
Register Type: READ/WRITE
Register Address: 120 (Decimal); 78 (Hex)
BIT NAME FUNCTION
[7:1] XA_OFFS[6:0] Lower bits of the X accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps
[0] - Reserved.
Register Name: YA_OFFSET_H
Register Type: READ/WRITE
Register Address: 122 (Decimal); 7A (Hex)
BIT NAME FUNCTION
[7:0] YA_OFFS[14:7] Upper bits of the Y accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps
Register Name: YA_OFFSET_L
Register Type: READ/WRITE
Register Address: 123 (Decimal); 7B (Hex)
BIT NAME FUNCTION
[7:1] YA_OFFS[6:0] Lower bits of the Y accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps
[0] - Reserved.
Register Name: ZA_OFFSET_H
Register Type: READ/WRITE
Register Address: 125 (Decimal); 7D (Hex)
BIT NAME FUNCTION
[7:0] ZA_OFFS[14:7] Upper bits of the Z accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps
Register Name: ZA_OFFSET_L
Register Type: READ/WRITE
Register Address: 126 (Decimal); 7E (Hex)
BIT NAME FUNCTION
[7:1] ZA_OFFS[6:0] Lower bits of the Z accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps
[0] - Reserved.
Document Number: DS-000176 Page 49 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
10 USE NOTES
10.1 TEMPERATURE SENSOR DATA
Temperature sensor data goes into the FIFO whenever the FIFO is enabled and there is a sensor active unless the temperature is
explicitly disabled.
10.2 ACCELEROMETER-ONLY LOW-NOISE MODE
The first output sample in Accelerometer-Only Low-Noise Mode after wake up from sleep always has 1 ms delay, independent of
ODR.
10.3 ACCELEROMETER LOW-POWER MODE
Changing the value of SMPLRT_DIV register in Accelerometer Low-Power mode will take effect after up to one sample at the old
ODR.
10.4 SENSOR MODE CHANGE
When switching from low-power modes to low-noise modes, unsettled output samples may be observed at the gyroscope or
accelerometer outputs due to filter switching and settling. The number of unsettled output samples depends on the filter and ODR
settings. The number of unsettled output samples is minimized by selecting the widest low-noise-mode filter bandwidth consistent
with the chosen ODR.
10.5 TEMP SENSOR DURING GYROSCOPE STANDBY MODE
During transition from Gyro Low power mode (GYRO_CYCLE=1), to Gyro Standby mode, in addition to the Gyro axis (axes) being
turned off, the Temp Sensor will also be turned off if the Accel is disabled. In order to keep the temp sensor on during Gyroscope
standby mode when Accel is disabled, the following procedure should be followed:
Set GYRO_CYCLE = 0 at least one ODR cycle prior to entering Standby mode
At least one of the Gyro axis is ON prior to entering Standby mode
Set GYRO_STANDBY = 1
10.6 GYROSCOPE MODE CHANGE
Gyroscope will take one ODR clock period to switch from Low-Noise to Low-Power mode after GYRO_CYCLE bit is set.
If GYRO_CYCLE is set to 1 prior to turning on the gyroscope, the first sample will be from low-noise mode, which may not be a
settled value. It is therefore recommended to ignore the first reading in this case.
10.7 POWER MANAGEMENT 1 REGISTER SETTING
It is required to set CLKSEL[2:0] to 001 (auto-select) for full performance.
10.8 UNLISTED REGISTER LOCATIONS
Do not read unlisted register locations in Sleep mode as this may cause the device to hang up, requiring power cycle to restore
operation.
10.9 CLOCK TRANSITION WHEN GYROSCOPE IS TURNED OFF
When the gyroscope is on, the on-chip master clock source will be the gyroscope clock (assuming CLKSEL[2:0] = 001 for auto-select
mode); otherwise, the master clock source will be the internal oscillator as long as the part is not in Sleep mode. During a power
mode transition, whenever the gyroscope is disabled and the part enters a mode other than Sleep, the on-chip master clock source
will transition from the gyroscope clock to the internal oscillator. It will take about 20 µs for this transition to complete.
10.10 SLEEP MODE
The part will only enter Sleep mode when the SLEEP bit in PWR_MGMT_2 is set to ‘1’. If SLEEP bit is ‘0’ and bit STBY_[X,Y,Z]A and
STBY_[X,Y,Z]G are all set to ‘1’, accelerometer and gyroscope will be turned off, but the on-chip master clock will still be running and
consuming power.
10.11 NO SPECIAL OPERATION NEEDED FOR FIFO READ IN LOW POWER MODE
The use of FIFO is enabled in all modes including low power mode.
Document Number: DS-000176 Page 50 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
10.12 GYROSCOPE STANDBY PROCEDURE
The follow precaution and procedure must be followed while using the Gyroscope Standby mode:
Precaution to follow while entering Standby Mode:
The user will ensure that at least one gyro axis is ON when setting gyro_standby = 1.
Procedure to transition from Gyro Standby to Gyro off:
The user should set gyro_standby = 0 first
Next, turn off gyro x/y/z.
Document Number: DS-000176 Page 51 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
11 ASSEMBLY
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS) gyros packaged in
LGA package.
11.1 ORIENTATION OF AXES
The diagram below shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier (•) in the
Figure 13.
+Z
+Z +Y
ICM-20602 +Y
+X +X
12
Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation
Document Number: DS-000176 Page 52 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
12.1 PACKAGE DIMENSIONS
16 Lead LGA (3x3x0.75) mm NiAu pad finish
Figure 14. Package Dimensions
Document Number: DS-000176 Page 53 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
DIMENSIONS IN MILLIMETERS
SYMBOLS MIN NOM MAX
Total Thickness A 0.7 0.75 0.8
Substrate Thickness A1 0.105 REF
Mold Thickness A2 0.63 REF
Body Size D 2.9 3 3.1
E 2.9 3 3.1
Lead Width W 0.2 0.25 0.3
Lead Length L 0.3 0.35 0.4
Lead Pitch e 0.5 BSC
Lead Count n 16
Edge Ball Center to Center D1 2 BSC
E1 1 BSC
Body Center to Contact Ball SD ---
SE ---
Ball Width b --- --- ---
Ball Diameter ---
Ball Opening ---
Ball Pitch e1 ---
Ball Count n1 ---
Pre-Solder --- --- ---
Package Edge Tolerance aaa 0.1
Mold Flatness bbb 0.2
Coplanarity ddd 0.08
Ball Offset (Package) eee ---
Ball Offset (Ball) fff ---
Lead Edge to Package Edge M 0.05 0.1 0.15
Table 16. Package Dimensions Table
Document Number: DS-000176 Page 54 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
13 PART NUMBER PACKAGE MARKING
The part number package marking for ICM-20608 devices is summarized below:
PART NUMBER PART NUMBER PACKAGE MARKING
ICM-20602 I62
TOP VIEW
I62 Part Number
XXXX Lot Traceability Code
AWW
A = Assembly Sublot Number
WW = Work Week
Figure 15. Part Number Package Marking
Document Number: DS-000176 Page 55 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
14 REVISION HISTORY
REVISION DATE REVISION DESCRIPTION
10/03/2016 1.0 Initial Release
Document Number: DS-000176 Page 56 of 57
Revision: 1.0
Revision Date: 10/03/2016
ICM-20602
15 ENVIRONMENTAL COMPLIANCE
The ICM-20602 is RoHS and Green compliant. The ICM-20602 is in full environmental compliance as evidenced in report HS-ICM-
20602A, Materials Declaration Data Sheet.
Environmental Declaration Disclaimer:
InvenSense believes this environmental information to be correct but cannot guarantee accuracy or completeness. Conformity documents for the above component
constitutes are on file. InvenSense subcontracts manufacturing and the information contained herein is based on data received from vendors and suppliers, which has
not been validated by InvenSense.
This information furnished by InvenSense is believed to be accurate and reliable. However, no responsibility is assumed by
InvenSense for its use, or for any infringements of patents or other rights of third parties that may result from its use. Specifications
are subject to change without notice. InvenSense reserves the right to make changes to this product, including its circuits and
software, in order to improve its design and/or performance, without prior notice. InvenSense makes no warranties, neither
expressed nor implied, regarding the information and specifications contained in this document. InvenSense assumes no
responsibility for any claims or damages arising from information contained in this document, or from the use of products and
services detailed therein. This includes, but is not limited to, claims or damages based on the infringement of patents, copyrights,
mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by
implication or otherwise under any patent or patent rights of InvenSense. This publication supersedes and replaces all information
previously supplied. Trademarks that are registered trademarks are the property of their respective companies. InvenSense sensors
should not be used or sold in the development, storage, production or utilization of any conventional or mass-destructive weapons
or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment,
transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime
prevention equipment.
©2016 InvenSense, Inc. All rights reserved. InvenSense, Sensing Everything, MotionTracking, MotionProcessing, MotionProcessor,
MotionFusion, MotionApps, Digital Motion Processor, and the InvenSense logo are trademarks of InvenSense, Inc. Other company
and product names may be trademarks of the respective companies with which they are associated.
©2016 InvenSense, Inc. All rights reserved.
Document Number: DS-000176 Page 57 of 57
Revision: 1.0
Revision Date: 10/03/2016
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
TDK:
ICM-20602
京公网安备 11010802033920号
Copyright © 2005-2021 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
