September 2007
HYB18H256321BF11/12/14
HYB18H256321BF10
256-Mbit GDDR3 Graphics RAM
GDDR3 Graphics RAM
RoHS compliant
Internet Data Sheet
Rev. 0.80
Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
HYB18H256321BF11/12/14
HYB18H256321BF10
Revision History: 2007-09, Rev. 0.80
Page Subjects (major changes since last revision)
All New Internet Data Sheet
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qag_techdoc_rev411 / 3.31 QAG / 2007-01-22 2
09132007-07EM-7OYI
Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
1 Overview
This chapter lists all main features of the product family HYB18H256321BF and the ordering information.
1.1 Features
2.0 V VDDQ IO voltage HYB18H256321BF10 Data mask for write commands
2.0 V VDD core voltage HYB18H256321BF10 Single ended READ strobe (RDQS) per byte. RDQS edge-
1.8 V VDDQ IO voltage HYB18H256321BF11/12/14
1.8 V VDD core voltage HYB18H256321BF11/12/14 aligned with READ data
Organization: 2048K 32 4 banks Single ended WRITE strobe (WDQS) per byte. WDQS
4096 rows and 512 columns (128 burst start locations) per
center-aligned with WRITE data
bank DLL aligns RDQS and DQ transitions with Clock
Programmable IO interface including on chip termination
Differential clock inputs (CLK and CLK)
(ODT)
CAS latencies of 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 Autoprecharge option with concurrent auto precharge
Write latencies of 3, 4, 5, 6, 7 support
4k Refresh (32ms)
Burst sequence with length of 4, 8. Autorefresh and Self Refresh
PGTFBGA136 package (10mm 14mm)
4n pre fetch Calibrated output drive. Active termination support
RoHS Compliant Product1)
Short RAS to CAS timing for Writes
tRAS Lockout support
tWR programmable for Writes with Auto-Precharge
Part Number1) Organisation Clock (MHz) TABLE 1
1000/900/800/700
HYB18H256321BF11/12/14 32 Ordering Information
Package
PGTFBGA136
HYB18H256321BF10
1) HYB: designator for memory components
18H: VDDQ = 1.8 V
256: 256-Mbit density
32: Organization
B: Product revision
F: Lead- and Halogen-Free
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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HYB18H256321BF
256-Mbit GDDR3
1.2 Description
The Qimonda 256-Mbit GDDR3 Graphics RAM is a high speed memory device, designed for high bandwidth intensive
applications like PC graphics systems. The chip's 4 bank architecture is optimized for high speed.
HYB18H256321BF uses a double data rate interface and a 4n-pre fetch architecture. The GDDR3 interface transfers two 32
bit wide data words per clock cycle to/from the I/O pins. Corresponding to the 4n-pre fetch a single write or read access consists
of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, one-half-clock-
cycle data transfers at the I/O pins.
Single-ended unidirectional Read and Write Data strobes are transmitted simultaneously with Read and Write data respectively
in order to capture data properly at the receivers of both the Graphics SDRAM and the controller. Data strobes are organized
per byte of the 32 bit wide interface. For read commands the RDQS are edge-aligned with data, and the WDQS are center-
aligned with data for write commands.
The HYB18H256321BF operates from a differential clock (CLK and CLK). Commands (addresses and control signals) are
registered at every positive edge of CLK. Input data is registered on both edges of WDQS, and output data is referenced to
both edges of RDQS.
In this document references to "the positive edge of CLK" imply the crossing of the positive edge of CLK and the negative edge
of CLK. Similarly, the "negative edge of CLK" refers to the crossing of the negative edge of CLK and the positive edge of CLK.
References to RDQS are to be interpreted as any or all RDQS<3:0>. WDQS, DM and DQ should be interpreted in a similar
fashion.
Read and write accesses to the HYB18H256321BF are burst oriented. The burst length is fixed to 4 and 8 and the two least
significant bits of the burst address are "Don't Care" and internally set to LOW. Accesses begin with the registration of an
ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVATE command are used to select the bank and the row to be accessed. The address bits registered coincident with the
READ or WRITE command are used to select the bank and the column location for the burst access. Each of the 4 banks
consists of 4096 row locations and 512 column locations. An AUTO PRECHARGE function can be combined with READ and
WRITE to provide a self-timed row precharge that is initiated at the end of the burst access. The pipe lined, multibank
architecture of the HYB18H256321BF allows for concurrent operation, thereby providing high effective bandwidth by hiding row
precharge and activation time.
The "On Die Termination" interface (ODT) is optimized for high frequency digital data transfers and is internally controlled. The
termination resistor value can be set using an external ZQ resistor or disabled through the Extended Mode Register.
The output driver impedance can be set using the Extended Mode Register. It can either be set to ZQ / 6 (auto calibration) or
to 35, 40 or 45 Ohms.
Auto Refresh and Power Down with Self Refresh operations are supported.
An industrial standard PGTFBGA136 package is used which enables ultra high speed data transfer rates and a simple
upgrade path from former DDR Graphics SDRAM products.
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HYB18H256321BF
256-Mbit GDDR3
2 Configuration
FIGURE 1
Ballout 256-Mbit GDDR3 Graphics RAM [Top View, MF = Low ]
9''4 9'' 966 =4 $ 0) 966 9'' 9''4
9664 '4 '4 9664 % 9664 '4 '4 9664
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9''4 '4 '0 9''4 ( 9''4 '0 '4 9''4
9'' '4 '4 &$6 ) &6 '4 '4 9''
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95() $ 5$6 &.( + :( 5)0 $ 95()
966$ 5)8 5)8 9''4 - 9''4 &. &. 966$
9''$ $ $ $ . $ $ $$3 9''$
966 9664 '4 $ / $ '4 9664 966
9'' '4 '4 $ 0 $ '4 '4 9''
9''4 '4 '0 9''4 1 9''4 '0 '4 9''4
9664 :'46 5'46 9664 3 9664 5'46 :'46 9664
9''4 '4 '4 9''4 5 9''4 '4 '4 9''4
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9''4 9'' 966 1& 8 5(6(7 966 9'' 9''4
%$//287B)%*$B0
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HYB18H256321BF
256-Mbit GDDR3
2.1 Ball Definition and Description
TABLE 2
Ball Description
Ball Type Detailed Function
CLK, CLK Input Clock:
CKE Input CLK and CLK are differential clock inputs. Address and command inputs are latched on the positive
edge of CLK. Graphics SDRAM outputs (RDQS, DQs) are referenced to CLK. CLK and CLK are not
CS Input internally terminated.
RAS, CAS, Input
WE I/O Clock Enable:
DQ<0:31> Input CKE HIGH activates and CKE LOW deactivates the internal clock and input buffers. Taking CKE
DM<0:3> Output LOW provides Power Down. If all banks are precharged, this mode is called Precharge Power Down
RDQS<0:3> Input and Self Refresh mode is entered if a Auto Refresh command is issued. If at least one bank is open,
WDQS<0:3> Input Active Power Down mode is entered and no Self Refresh is allowed. All input receivers except CLK,
BA<0:1> CLK and CKE are disabled during Power Down. In Self Refresh mode the clock receivers are
disabled too. Self Refresh Exit is performed by setting CKE asynchronously HIGH. Exit of Power
Down without Self Refresh is accomplished by setting CKE HIGH with a positive edge of CLK.
The value of CKE is latched asynchronously by Reset during Power On to determine the value of the
termination resistor of the address and command inputs.
CKE is not allowed to go LOW during a RD, a WR or a snoop burst.
Chip Select:
CS enables the command decoder when low and disables it when high. When the command decoder
is disabled, new commands with the exception of DTERDIS are ignored, but internal operations
continue. CS is one of the four command balls.
Command Inputs:
Sampled at the positive edge of CLK, CAS, RAS, and WE define (together with CS) the command
to be executed.
Data Input/Output:
The DQ signals form the 32 bit data bus. During READs the balls are outputs and during WRITEs
they are inputs. Data is transferred at both edges of RDQS.
Input Data Mask:
The DM signals are input mask signals for WRITE data. Data is masked when DM is sampled HIGH
with the WRITE data. DM is sampled on both edges of WDQS. DM0 is for DQ<0:7>, DM1 is for
DQ<8:15>, DM2 is for DQ<16:23> and DM3 is for DQ<24:31>. Although DM balls are input-only,
their loading is designed to match the DQ and WDQS balls.
Read Data Strobes:
RDQSx are unidirectional strobe signals. During READs the RDQSx are transmitted by the Graphics
SDRAM and edge-aligned with data. RDQS have preamble and postamble requirements. RDQS0 is
for DQ<0:7>, RDQS1 for DQ<8:15>, RDQS2 for DQ<16:23> and RDQS3 for DQ<24:31>.
Write Data Strobes: WDQSx are unidirectional strobe signals. During WRITEs the WDQSx are
generated by the controller and center aligned with data. WDQS have preamble and postamble
requirements. WDQS0 is for DQ<0:7>, WDQS1 for DQ<8:15>, WDQS2 for DQ<16:23> and WDQS3
for DQ<24:31>.
Bank Address Inputs:
BA select to which internal bank an ACTIVATE, READ, WRITE or PRECHARGE command is being
applied. BA are also used to distinguish between the MODE REGISTER SET and EXTENDED
MODE REGISTER SET commands.
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HYB18H256321BF
256-Mbit GDDR3
Ball Type Detailed Function
A<0:11>
Input Address Inputs:
ZQ During ACTIVATE, A0-A11 defines the row address. For READ/WRITE, A2-A7 and A9 defines the
RESET column address, and A8 defines the auto precharge bit. If A8 is HIGH, the accessed bank is
precharged after execution of the column access. If A8 is LOW, AUTO PRECHARGE is disabled and
MF the bank remains active. Sampled with PRECHARGE, A8 determines whether one bank is
precharged (selected by BA<0:1>, A8 LOW) or all 4 banks are precharged (A8 HIGH). During
SEN (EXTENDED) MODE REGISTER SET the address inputs define the register settings. A<0:11> are
VREF sampled with the positive edge of CLK.
VDD, VSS
VDDQ, VSSQ - ODT Impedance Reference:
NC, RFU
RFM The ZQ ball is used to control the ODT impedance.
Input Reset pin:
The RES pin is a VDDQ CMOS input. RES is not internally terminated. When RES is at LOW state the
chip goes into full reset. The chip stays in full reset until RES goes to HIGH state. The Low to High
transition of the RES signal is used to latch the CKE value to set the value of the termination resistors
of the address and command inputs. After exiting the full reset a complete initialization is required
since the full reset sets the internal settings to default.
Input Mirror function pin:
The MF pin is a VDDQ CMOS input. This pin must be hardwired on board either to a power or to a
ground plane. With MF set to HIGH, the command and address pins are reassigned in order to allow
for an easier routing on board for a back to back memory arrangement.
Input Enables Boundary Scan Functionality:
If Boundary Scan is not used PIN should be constantly connected to GND.
Supply Voltage Reference:
Supply VREF is the reference voltage input.
Power Supply:
Power and Ground for the internal logic.
Supply I/O Power Supply:
Isolated Power and Ground for the output buffers to provide improved noise immunity.
- Please do not connect No Connect and Reserved for Future Use balls.
- When the MF ball is tied LOW, RFM receiver is disabled and it recommended to be driven to a static
LOW state. However, either static HIGH or floating state on this pin will not cause any problem for
the GDDR3 SGRAM. When the MF ball is tied HIGH, RAS(H3) becomes RFM due to mirror function
and the receiver is disabled. It is recommended to be driven to a static LOW state. However, either
static HIGH or floating state on this pin will not cause any problem for the GDDR3 SGRAM.
2.2 Mirror Function
The GDDR3 Graphics RAM provides a ball mirroring feature that is enabled by applying a logic HIGH on ball MF. This function
allows for efficient routing in a clam shell configuration.
Depending of the logic state applied on MF, the command and address signals will be assigned to different balls. The default
ball configuration corresponds to MF = LOW.
The DC level (HIGH or LOW) must be applied on the MF pin at power up and is not allowed to change after that.
Table 3 shows the ball assignment as a function of the logic state applied on MF.
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LOW MF Logic State Internet Data Sheet
H3 HIGH HYB18H256321BF
F4 256-Mbit GDDR3
H9 H10
F9 F9 TABLE 3
H4 H4
K4 F4 Ball Assignment with Mirror
H2 H9 Signal
K3 K9
M4 H11 RAS
K9 K10 CAS
H11 M9 WE
K10 K4 CS
L9 H2 CKE
K11 K3 A0
M9 L4 A1
K2 K2 A2
L4 M4 A3
G4 K11 A4
G9 L9 A5
G9 A6
G4 A7
A8
A9
A10
A11
BA0
BA1
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HYB18H256321BF
256-Mbit GDDR3
2.3 Truth Tables
2.3.1 Function Truth Table for more than one Activated Bank
If there is more than one bank activated in the Graphics SDRAM, some commands can be performed in parallel due to the
chip's multibank architecture. The following table defines for which commands such a scheme is possible. All other transitions
are illegal. Notes 1-11 define the start and end of the actions belonging to a submitted command. This table is based on the
assumption that there are no other actions ongoing on bank n or bank m. If there are any actions ongoing on a third bank tRRD,
tRTW and tWTR have to be taken always into account.
TABLE 4
Function Truth Table I
Current State Ongoing action on bank n Possible action in parallel on bank m
ACTIVE ACTIVATE1) ACT, PRE, WRITE, WRITE/A, READ, READ/A2)
WRITE3) ACT, PRE, WRITE, WRITE/A, READ, READ/A4)
WRITE/A5) ACT, PRE, WRITE, WRITE/A, READ6)
READ7) ACT, PRE, WRITE, WRITE/A, READ, READ/A8)
READ/A9) ACT, PRE, WRITE, WRITE/A, READ, READ/A 8)
PRECHARGE10) ACT, PRE, WRITE, WRITE/A, READ, READ/A11)
PRECHARGE ALL 10) -
POWER DOWN ENTRY12) -
IDLE ACTIVATE 1) ACT
POWER DOWN ENTRY 12) -
AUTO REFRESH13) -
SELF REFRESH ENTRY 12) -
MODE REGISTER SET (MRS)14) -
EXTENDED MRS 14) -
POWER DOWN POWER DOWN EXIT15) -
SELF REFRESH SELF REFRESH EXIT16) -
1) Action ACTIVATE starts with issuing the command and ends after tRCD.
2) During action ACTIVATE an ACT command on another bank is allowed considering tRRD, a PRE command on another bank is allowed
any time. WR, WR/A, RD and RD/A are always allowed.
3) Action WRITE starts with issuing the command and ends tWR after the first pos. edge of CLK following the last falling WDQS edge.
4) During action WRITE an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank
must be separated by at least one NOP from the ongoing WRITE. RD or RD/A are not allowed before tWTR is met.
5) Action WRITE/A starts with issuing the command and ends tWR after the first positive edge of CLK following the last falling WDQS edge.
6) During action WRITE/A an ACT or a PRE command on another bank is allowed any time. A new WR or WR/A command on another bank
has to be separated by at least one NOP from the ongoing command. RD is not allowed before or tWTR is met. RD/A is not allowed during
an ongoing WRITE/A action.
7) Action READ starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS.
8) During action READ and READ/A an ACT or a PRE command on another bank is allowed any time. A new RD or RD/A command on
another bank has to be separated by at least one NOP from the ongoing command. A WR or WR/A command on another bank has to
meet tRTW.
9) Action READ/A starts with issuing the command and ends with the first positive edge of CLK following the last falling edge of RDQS.
10) Action PRECHARGE and PRECHARGE ALL start with issuing the command and ends after tRP.
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HYB18H256321BF
256-Mbit GDDR3
11) During Action ACTIVE an ACT command on another banks is allowed considering tRRD . A PRE command on another bank is allowed any
time. WR, WR/A, RD and RD/A are always allowed.
12) During POWER DOWN and SELF REFRESH only the EXIT commands are allowed.
13) AUTO REFRESH starts with issuing the command and ends after tRFC.
14) Actions MODE REGISTER SET and EXTENDED MODE REGISTER SET start with issuing the command and ends after tMRD.
15) Action POWER DOWN EXIT starts with issuing the command and ends after tXPN.
16) Action SELF REFRESH EXIT starts with issuing the command and ends after tXSC.
2.4 Function Truth Table for CKE
CKE CKE CURRENT STATE COMMAND TABLE 5
N-1 n
L L Power Down X Function Truth Table II (CKE Table)
Self Refresh X ACTION
L H Power Down DESEL or NOP
Self Refresh DESEL or NOP Stay in Power Down
H L All Banks Idle DESEL or NOP Stay in Self Refresh
Bank(s) Active DESEL or NOP Exit Power Down
All Banks Idle Auto Refresh Exit Self Refresh 5
Entry Precharge Power Down
Entry Active Power Down
Entry Self Refresh
Notes
1. CKEn is the logic step at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the GDDR3 Graphics RAM immediately prior to clock edge n.
3. COMMAND is the command registered at clock edge n, and ACTION is a result of COMMAND.
4. All states and sequences not shown are illegal or reserved.
5. DESEL or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of 1000 clock
cycles is required before applying any other valid command.
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HYB18H256321BF
256-Mbit GDDR3
3 Functional Description
3.1 Mode Register Set Command (MRS)
FIGURE 2 The Mode Register stores the data for controlling the
operation modes of the memory. It programs CAS latency,
Mode Register Set Command test mode, DLL Reset , the value of the Write Latency and the
Burst length. The Mode Register must be written after power
&/. up to operate the SGRAM. During a ModeRegister Set
&/. command the address inputs are sampled and stored in the
&.( Mode Register. The Mode Register content can only be set or
&6 changed when the chip is in Idle state. For non-READ
commands following a Mode Register Set a delay of tMRD
5$6 must be met.
&$6
:( The Mode Register Bitmap is supported in two configurations.
$$ The first configuration is intended to support the Mid-Range-
Speed application. The second configuration supports higher
%$ clock cycles for CAS latency and is therefore prepared to
%$ support high-speed application. The selected configuration is
defined by Bit0 of EMRS2.
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Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
FIGURE 3
Mode Register Bitmap for Mid-Range-Speed Application
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HYB18H256321BF
256-Mbit GDDR3
FIGURE 4
Mode Register Bitmap for High-Speed Application
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FIGURE 5
Mode Register Set Timing
CLK#
CLK
Com. PA NOP MRS NOP NOP A.C. NOP RD
tRP tMRD
tMRDR MRS: MRS command
PA: PREALL command
A.C.: Any other command as READ
RD: READ command
Don't Care
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HYB18H256321BF
256-Mbit GDDR3
3.1.1 Burst length
Read and Write accesses to the GDDR3 Graphics RAM are burst oriented with burst length of 4 and 8. This value must be
programmed using the Mode Register Set command (A0 .. A2). The burst length determines the number of column locations
that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses
for that burst take place within this block if a boundary is reached. The starting location within this block is determined by the
two least significant bits A0 and A1 which are set internally to the fixed value of zero each.Reserved states should not be used,
as unknown operation or incompatibility with future versions may result.
3.1.2 Burst type
Accesses within a given bank must be programmed to be sequential. This is done using the Mode Register Set command (A3).
This device does not support the burst interleave mode.
TABLE 6
Burst Definition
Burst Length Starting Column Address Order of Accesses within a Burst
(Type = sequential)
4 A2 A1 A0
8 --X X 0-1-2-3
0 XX 0-1-2-3-4-5-6-7
1 XX 4-5-6-7-0-1-2-3
The value applied at the balls A0 and A1 for the column address is "Don't care".
3.1.3 CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit
of output data.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident
with clock edge n+m.
The two Mode Register setups support different CAS Latencies in terms of clock cycles. The mid-range-speed Mode Register
supports latencies from 7 to 14. The high-speed Mode Register supports latencies from 10 to 17. The active Mode Register
setup is selected by Bit0 of EMRS2.
3.1.4 Write Latency
The WRITE latency, WL, is the delay, in clock cycles, between the registration of a WRITE command and the availability of the
first bit of input data.
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Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
WL TABLE 7
3-4
5-6-7 ON/OFF mode of DQ/DM receivers
DQ/DM-Receivers
Receivers are always on
Receivers are off and will be switched on by Write command and will be switched off again after
WL+BL
The ON/OFF state of the DQ/DM receivers depends on the Write Latency. The dependence is given in Table 7.
3.1.5 Test mode
The normal operating mode is selected by issuing a Mode Register Set command with bit A7 set to zero and bits A0-A6 and
A8-A11 set to the desired value.
3.1.6 DLL Reset
The normal operating mode is selected by issuing a Mode Register Set command with bit A8 set to zero and bits A0-A7 and
A9-A11 set to the desired values. A DLL Reset is initiated by issuing a Mode Register Set command with bit A8 set to one and
bits A0-A7 and A9-A11 set to the desired values. The GDDR3 Graphics RAM returns automatically in the normal mode of
operations once the DLL reset is completed.
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Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
3.2 Extended Mode Register Set Command (EMRS1)
FIGURE 6 The Extended Mode Register is used to set the output driver
impedance value, the termination impedance value, the Write
Extended Mode Register Set Command Recovery time value for Write with Autoprecharge. It is used
as well to enable/disable the DLL, to issue the Vendor ID and
&/. to enable/disable the Low Power mode. There is no default
&/. value for the Extended Mode Register. Therefore it must be
&.( written after power up to operate the GDDR3 Graphics RAM.
&6 The Extended Mode Register can be programmed by
performing a normal Mode Register Set operation and setting
5$6 the BA0 bit to HIGH and BA1 bits to LOW. All other bits of the
EMR register are reserved and should be set to LOW.
&$6
The Extended Mode Register must be loaded when all banks
are idle and no burst are in progress. The controller must wait
the specified time tMRD before initiating any subsequent
operation (Figure 9).
The timing of the EMRS command operation is equivalent to
the timing of the MRS command operation.
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Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
FIGURE 7
Extended Mode Register Bitmap for Mid-Range-Speed Application
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There are two bitmaps for the Extended Mode Register. One bitmap shown in Figure 7 is supposed to support Mid-Speed
applications. The other bitmap shown in Figure 8 is more focused on the high-range-speed application. Both bitmaps
distinguish different numbers in supported Write Recovery clock cycles. The mid-range bit map provides WR cycles from 4 to
11.The high-speed bitmap supports WR from 7 to 13.
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HYB18H256321BF
256-Mbit GDDR3
FIGURE 8
Extended Mode Register Bitmap for High-Speed Application
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Notes option implemented in the device) or no action is taken by
1. These settings are for debugging purposes only. the device (if option not implemented).
2. Default termination values at Power Up.
3. The ODT disable function disables all terminators on the 5. WR (write recovery time for auto precharge) in clock
device. cycles is calculated by dividing tWR (in ns) and rounding up
4. If the user activates bits in the extended mode register in to the next integer (WR[cycles] = tWR[ns] / tCK[ns]). The
mode register must be programmed to this value.
an optional field, either the optional field is activated (if
FIGURE 9
Extended Mode Register Set Timing
CLK#
CLK
Command PA NOP EMRS NOP NOP A.C.
tRP
tMRD
A.C.: Any command EMRS: Extended MRS command
Don't Care PA: PREALL command
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HYB18H256321BF
256-Mbit GDDR3
3.2.1 DLL enable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to
normal operation after having disabled the DLL. (When the device exits self-refresh mode, the DLL is enabled automatically).
Anytime the DLL is enabled, 1000 cycles must occur before a READ command can be issued.
3.2.2 WR
The WR parameter is programmed using the register bits A4, A5 and A7. This integer parameter defines as a number of clock
cycles the Write Recovery time in a Write with Autoprecharge operation.
The following inequality has to be complied with: WR * tCK tWR, where tCK is the clock cycle time. The high-speed bitmap
supports WR from 7 to 13. The mid-range bitmap provides WR cycles from 4 to 11.
3.2.3 Termination Rtt
The data termination, Rtt, is used to set the value of the internal termination resistors. The GDDR3 DRAM supports ZQ / 4 and
ZQ / 2 termination values. The termination may also be disabled for testing and other purposes.
3.2.4 Output Driver Impedance
The Output Driver Impedance extended mode register is used to set the value of the data output driver impedance. When the
auto calibration is used, the output driver impedance is set nominally to ZQ / 6.
If the Output Driver Impendance is changed to 30, 40 or 45 Ohms the user needs to issue 16 AREF commands separated by
tRFC consecutively to make the change effective. The user must be aware that the Command bus needs to be stable for a time
of tKO after each AREF.
3.2.5 Vendor Code and Revision Identification
The Manufacturer Vendor Code is selected by issuing an Extended Mode Register Set command with bit A10 set to 1 and bits
A0-A9 and A11 set to the desired value. When the Vendor Code function is enabled the GDDR3 DRAM will provide the
Qimonda vendor code on DQ[3:0] and the revision identification on DQ[7:4]. The code will be driven onto the DQ bus after
tRIDon following the EMRS command that sets A10 to 1. The Vendor Code and Revision ID will be driven on DQ[7:0] until a
new EMRS command is issued with A10 set back to 0. After tRDoff following the second EMRS command, the data bus is driven
back to HIGH. This second EMRS command must be issued before initiating any subsequent operation. Violating this
requirement will result in unspecified operation.
Revision Identification TABLE 8
DQ[7:4]
0011 Revision ID and Vendor Code
Qimonda Vendor Code
DQ[3:0]
0010
Note: Please refer to Revision Release Note for Revision ID value.
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HYB18H256321BF
256-Mbit GDDR3
FIGURE 10
Timing of Vendor Code and Revision ID Generation on DQ[7:0]
0 1 2 3 4 5 6 7 8 9 10
CLK#
CLK
Com. EMRS N/D N/D N/D N/D N/D EMRS N/D N/D N/D N/D
A[9:0], Add Add
A11
A10
t RIDon t RIDoff
RDQS
DQ[7:0]
Vendor Code and Revision ID
EMRS: Extended Mode Register Set Command
Add: Address
N/D: NOP or Deselect
Don't Care
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HYB18H256321BF
256-Mbit GDDR3
3.3 Extended Mode Register 2 Set Command (EMRS2)
FIGURE 11 The Extended Mode Register 2 is used to define the active
bitmap of the Mode Register and the Extended Mode
Extended Mode Register 2 Set Command Register. The Extended Mode Register 2 must be written
after power up to operate the GDDR3 Graphics RAM. The
&/. Extended Mode Register 2 can be programmed by
&/. performing a normal Mode Register Set operation and setting
&.( the BA1 bit to HIGH and BA0 bits to LOW. All bits defined as
RFU in the bitmap are reserved and must be set to LOW. The
&6 Extended Mode Register 2 must be loaded when all banks
are idle and no burst are in progress. The controller must wait
5$6 the specified time tMRD before initiating any subsequent
operation. The timing of the EMRS2 command operation is
equivalent to the timing of the MRS command operation.
&$6
:(
$$ &2'
%$
%$ &2'&RGHWREHORDGHGLQWR
WKHUHJLVWHU
'RQ
W&DUH
FIGURE 12
Extended Mode Register 2 Bitmap
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HYB18H256321BF
256-Mbit GDDR3
3.3.1 App Mode
The GDDR3 Graphics RAM provides two bitmaps for the Mode Register and the Extended Mode Register respectively. The
Bitmaps are shown in the MRS and EMRS chapters.
The Bit0 of the Extended Mode Regsiter 2 defines which one of the two bitmaps is active. Bit0 set to LOW enables the mid-
range bitmap and Bit0 set to HIGH enables the High-Speed bitmap.
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HYB18H256321BF
256-Mbit GDDR3
4 Electrical Characteristics
4.1 Absolute Maximum Ratings and Operation Conditions
TABLE 9
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Power Supply Voltage VDD Min. Max.
Power Supply Voltage for Output Buffer VDDQ
Input Voltage VIN -0.5 2.5 V
Output Voltage VOUT -0.5
Storage Temperature TSTG -0.5 2.5 V
Junction Temperature TJ -0.5
Short Circuit Output Current IOUT -55 2.5 V
--
-- 2.5 V
+150 C
+125 C
50 mA
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
4.2 DC Operation Conditions
4.2.1 Recommended Power & DC Operation Conditions
TABLE 10
Power & DC Operation Conditions (0 C Tc 85 C)
Parameter Symbol Limit Values Unit Note
Power Supply Voltage VDD, VDDA Min. Typ. Max. V 1)2)
Power Supply Voltage for I/O Buffer VDDQ 1.9 2.0 2.1
1.9 2.0 2.1 V 1)2)
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HYB18H256321BF
256-Mbit GDDR3
Parameter Symbol Limit Values Unit Note
Min. Typ. Max.
Power Supply Voltage VDD, VDDA 1.7 1.8 1.9 V 1)3)
Power Supply Voltage for I/O Buffer VDDQ 1.7 1.8 1.9 V 1)3)
Reference Voltage VREF 0.69*VDDQ -- 0.71*VDDQ V 4)
Output Low Voltage VOL(DC) -- -- 0.8 V
Input leakage current IIL 5.0 -- +5.0 5)
CLK Input leakage current IILC 5.0 -- +5.0
Output leakage current IOL 5.0 -- +5.0 5)
1) VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
2) HYB18H256321BF11/12/14
3) HYB18H256321BF10
4) VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise
on VREF may not exceed 2% VREF (DC). Thus, from 70% of VDDQ, VREF is allowed 19mV for DC error and an additional 27mV for AC
noise.
5) IIL and IOL are measured with ODT disabled.
4.3 DC & AC Logic Input Levels
TABLE 11
DC & AC Logic Input Levels (0 C Tc 85 C)
Parameter Symbol Limit Values Unit Note
Min. Max.
Input logic high voltage, DC VIH(DC) VREF + 0.15 -- V 1)
Input logic low voltage, DC VIL(DC) -- VREF -0.15 V 1)
Input logic high voltage, AC VIH(AC) VREF + 0.25 -- V 2)3)
Input logic low voltage, AC VIL(AC) -- VREF - 0.25 V 2)3)
Input logic high, DC, RESET pin VIHR(DC) 0.65 VDDQ VDDQ + 0.3 V
Input logic low, DC, RESET pin VILR(DC) -0.3 0.35 VDDQ V
Input Logic High, DC, MF pin VIHMF(DC) VDD VDD + 0.3 V 4)
Input Logic Low,DC, MF pin VILMF(DC) 0.3 0 V
1) The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to
maintain a valid level.
2) Input slew rate = 3 V/ns. If the input slew rate is less than 3 V/ns, input timing may be compromised. All slew rates are measured between
VIL(DC) and VIH(DC).
3) VIH overshoot: VIH(max) = VDDQ+0.5V for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. VIL
undershoot: VIL(min) = 0 V for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate.
4) The MF pin must be hard-wired on board to either VDD or VSS.
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HYB18H256321BF
256-Mbit GDDR3
4.4 Differential Clock DC and AC Levels
TABLE 12
Differential Clock DC and AC Input conditions (0 C Tc 85 C)
Parameter Symbol Limit Values Unit Note
Min. Max.
Clock Input Mid-Point Voltage, CLK and CLK VMP(DC) 0.7 VDDQ 0.10 0.7 VDDQ + 0.10 V 1)
Clock Input Voltage Level, CLK and CLK VIN(DC) 0.42
Clock DC Input Differential Voltage, CLK and VID(DC) 0.3 VDDQ + 0.3 V 1)
CLK
VDDQ V 1)
Clock AC Input Differential Voltage, CLK and CLK VID(AC) 0.5 VDDQ + 0.5 V 1)2)
AC Differential Crossing Point Input Voltage VIX(AC) 0.7 VDDQ 0.15 0.7 VDDQ + 0.15 V 1)3)
1) All voltages referenced to VSS.
2) VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
3) The value of VIX is expected to equal 0.7 VDDQ of the transmitting device and must track variations in the DC level of the same.
4.5 Output Test Conditions
FIGURE 13
Output Test Circuit
DQ V
DQS DDQ
60 Ohm
Test point
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HYB18H256321BF
256-Mbit GDDR3
4.6 Pin Capacitances
TABLE 13
Pin Capacitances (VDDQ = 1.8 V, TA = 25C, f = 1 MHz)
Parameter Symbol Min. Max. Unit Note
Input capacitance: CI,CCK 1.0 2.5 pF
A0-A11, BA0-1, CKE, CS, CAS, RAS, WE, CKE, RES,CLK,CLK
Input capacitance: CIO 2.0 3.0 pF
DQ0-DQ31, RDQS0-RDQS3, WDQS0-WDQS3, DM0-DM3
4.7 Driver current characteristics
4.7.1 Driver IV characteristics at 40 Ohms
Figure 14 represents the driver Pull-Down and Pull-Up IV characteristics under process, voltage and temperature best and
worst case conditions. The actual Driver Pull-Down and Pull-Up current must lie between these two bounding curves. The value
of the external ZQ resistor is 240 , setting the nominal driver output impedance to 40 .
FIGURE 14
40 Ohm Driver Pull-Down and Pull-Up Characteristics
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9''49RXW9
9RXW9
Table 14 lists the numerical values of the minimum and maximum allowed values of the output driver Pull-Down and Pull-Up
IV characteristics.
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HYB18H256321BF
256-Mbit GDDR3
Voltage (V) Pull-Down Current (mA) TABLE 14
0.1 Programmed Driver IV Characteristics at 40 Ohm
0.2
0.3 Pull-Up Current (mA)
0.4
0.5 Minimum Maximum Minimum Maximum
0.6
0.7 2.32 3.04 -2.44 -3.27
0.8 4.56 5.98 -4.79 -6.42
0.9 6.69 8.82 -7.03 -9.45
1.0 8.74 11.56 -9.18 -12.37
1.1 10.70 14.19 -11.23 -15.17
1.2 12.56 16.72 -13.17 -17.83
1.3 14.34 19.14 -15.01 -20.37
1.4 16.01 21.44 -16.74 -22.78
1.5 17.61 23.61 -18.37 -25.04
1.6 19.11 26.10 -19.90 -27.17
1.7 20.53 28.45 .21.34 -29.17
1.8 21.92 30.45 -22.72 -31.25
1.9 23.29 32.73 -24.07 -33.00
2.0 24.65 34.95 -25.40 -35.00
26.00 37.10 -26.73 -37.00
27.35 39.15 -28.06 -39.14
28.70 41.01 -29.37 -41.25
30.08 42.53 -30.66 -43.29
-- 43.71 -- -45.23
-- 44.89 -- -47.07
4.7.2 Termination IV Characteristic at 60 Ohms
Figure 15 represents the DQ termination Pull-Up IV characteristic under process, voltage and temperature best and worst case
conditions. The actual DQ termination Pull-Up current must lie between these two bounding curves. The value of the external
ZQ resistor is 240 , setting the nominal DQ termination impedance to 60 . (Extended Mode Register programmed to ZQ/4).
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HYB18H256321BF
256-Mbit GDDR3
FIGURE 15
60 Ohm Active Termination Characteristic
2KP7HUPLQDWLRQ&KDUDFWHUVWLFV
,RXWP$
9''49RXW9
Table 15 lists the numerical values of the minimum and maximum allowed values of the output driver termination IV
characteristic.
TABLE 15
Programmed Terminator Characteristics at 60 Ohm
Voltage (V) Terminator Pull-Up Current (mA) Voltage (V) Terminator Pull-Up Current (mA)
0.1 Minimum Maximum Minimum Maximum
0.2
0.3 -1.63 -2.18 1.1 -14.23 -19.45
0.4 -3.19 -4.28
0.5 -4.69 -6.30 1.2 -15.14 -20.83
0.6 -6.12 -8.25
0.7 -7.49 -10.11 1.3 -16.04 -22.00
0.8 -8.78 -11.89
0.9 -10.01 -13.58 1.4 -16.94 -23.33
1.0 -11.16 -15.19
-12.25 -16.69 1.5 -17.82 -24.67
-13.27 -18.11
1.6 -18.70 -26.09
1.7 -19.58 -27.50
1.8 -20.44 -28.86
1.9 -- -30.15
2.0 -- -31.38
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HYB18H256321BF
256-Mbit GDDR3
4.8 Termination IV Characteristic at 120 Ohms
Figure 16 represents the DQ or ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature best
and worst case conditions. The actual termination Pull-Up current must lie between these two bounding curves. The value of
the external ZQ resistor is 240 , setting the nominal termination impedance to 120 . (Extended Mode Register programmed
to ZQ/2 for DQ terminations or CKE = 0 at the RES transition during Power-Up for ADD/CMD terminations).
FIGURE 16
120 Ohm Active Termination Characteristic
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,RXWP$
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Table 16 lists the numerical values of the minimum and maximum allowed values of the termination IV characteristic.
TABLE 16
Programmed Terminator Characteristics of 120 Ohm
Voltage (V) Terminator Pull-Up Current (mA) Voltage (V) Terminator Pull-Up Current (mA)
0.1 Minimum Maximum Minimum Maximum
0.2
0.3 -0.81 -1.09 1.1 -7.11 -9.72
0.4 -1.60 -2.14
0.5 -2.34 -3.15 1.2 -7.57 -10.42
0.6 -3.06 -4.12
0.7 -3.74 -5.06 1.3 -8.02 -11.00
0.8 -4.39 -5.94
0.9 -5.00 -6.79 1.4 -8.47 -11.67
1.0 -5.58 -7.59
-6.12 -8.35 1.5 -8.91 -12.33
-6.63 -9.06
1.6 -9.35 -13.05
1.7 -9.79 -13.75
1.8 -10.22 -14.43
1.9 -- -15.08
2.0 -- -15.69
Rev. 0.80, 2007-09 29
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HYB18H256321BF
256-Mbit GDDR3
4.9 Termination IV Characteristic at 240 Ohms
Figure 17 represents the ADD/CMD termination Pull-Up IV characteristic under process, voltage and temperature best and
worst case conditions. The actual ADD/CMD termination Pull-Up current must lie between these two bounding curves. The
value of the external ZQ resistor is 240 , setting the nominal termination impedance to 240 . (CKE = 1at the RES transition
during Power-Up for ADD/CMD terminations).
FIGURE 17
240 Ohm Active Termination Characteristic
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,RXWP$
9''49RXW9
Table 17 lists the numerical values of the minimum and maximum allowed values of the ADD/CMD termination IV
characteristic.
TABLE 17
Programmed Terminator Characteristics at 240 Ohm
Voltage (V) Terminator Pull-Up Current (mA) Voltage (V) Terminator Pull-Up Current (mA)
0.1 Minimum Maximum Minimum Maximum
0.2
0.3 -0.41 -0.55 1.1 -3.56 -4.86
0.4 -0.80 -1.07
0.5 -1.17 -1.58 1.2 -3.79 -5.21
0.6 -1.53 -2.06
0.7 -1.87 -2.53 1.3 -4.01 -5.50
0.8 -2.20 -2.97
0.9 -2.50 -3.40 1.4 -4.23 -5.83
1.0 -2.79 -3.80
-3.06 -4.17 1.5 -4.46 -6.17
-3.32 -4.53
1.6 -4.68 -6.52
1.7 -4.90 -6.88
1.8 -5.11 -7.21
1.9 -- -7.54
2.0 -- -7.85
Rev. 0.80, 2007-09 30
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4.10 HYB18H256321BF
256-Mbit GDDR3
Operating Current Measurement Conditions
TABLE 18
Operating Current Measurement Conditions
Symbol Parameter/Condition
IDD0 Operating Current - One bank, Activate - Precharge
tCK=min(tCK), tRC=min(tRC)
IDD1 Databus inputs are SWITCHING; Address and control inputs are SWITCHING, CS = HIGH between valid
IDD2P commands.
IDD2F
IDD2Q Operating Current - One bank, Activate - Read - Precharge
IDD3P One bank is accessed with tCK=min(tCK), tRC=min(tRC), CL = CL(min), Address and control inputs are SWITCHING;
IDD3N CS = HIGH between valid commands. Iout=0 mA
IDD4R
IDD4W Precharge Power-Down Standby Current
IDD5B All banks idle, power-down mode, CKE is LOW, tCK=min(tCK), Data bus inputs are STABLE (HIGH).
IDD5D
IDD6 Precharge Floating Standby Current
IDD7 All banks idle; CS is HIGH, CKE is HIGH, tCK=min(tCK); Address and control inputs are SWITCHING; Data bus input
are STABLE (HIGH).
Precharge Quiet Standby Current
CS is HIGH, all banks idle, CKE is HIGH, tCK=min(tCK), Address and other control inputs STABLE (HIGH), Data
bus inputs are STABLE (HIGH).
Active Power-Down Standby Current
One bank active, CKE is LOW, Address and control inputs are STABLE (HIGH); Data bus inputs are STABLE
(HIGH); standard active power-down mode.
Active Standby Current
One bank active, CS is HIGH, CKE is HIGH, tRAS= tRAS,max, tCK=min(tCK); Address and control inputs are
SWITCHING; Data bus inputs are SWITCHING.
Operating Current - Burst Read
One bank active; Continuous read bursts, CL = CL(min); tCK=min(tCK); tRAS= tRAS,max; Address and control inputs
are SWITCHING; Iout = 0 mA.
Operating Current - Burst Write
One bank active; Continuous write bursts; tCK=min(tCK); Address and control inputs are SWITCHING; Data bus
inputs are SWITCHING.
Burst Auto Refresh Current
Refresh command at tRFC=min(tRFC); tCK=min(tCK); CKE is HIGH, CS is HIGH between all valid commands; Other
command and address inputs are SWITCHING; Data bus inputs are SWITCHING.
Distributed Auto Refresh Current
tCK=tCKmin; Refresh command every tREFI; CKE is HIGH, CS is HIGH between valid commands; Other command
and address inputs are SWITCHING; Data bus inputs are SWITCHING.
Self Refresh Current
CKE max(VIL), external clock off, CK and CK LOW; Address and control inputs are STABLE (HIGH); Data Bus
inputs are STABLE (HIGH).
Operating Bank Interleave Read Current
All banks interleaving with CL = CL(min); tRCD = tRCDRD(min); tRRD = tRRD(min); Iout=0 mA; Address and control inputs
are STABLE (HIGH) during DESELECT; Data bus inputs are SWITCHING.
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HYB18H256321BF
256-Mbit GDDR3
Notes
1. 0 C Tc 85 C
2. Data Bus consists of DQ, DM, WDQS.
3. Definitions for IDD:
LOW is defined as VIN = 0.4 VDDQ; HIGH is defined as VIN = VDDQ;
TABLE is defined as inputs are stable at a HIGH level.
SWITCHING is defined as inputs are changing between HIGH and LOW every clock cycle for address and control signals,
and inputs changing 50% of each data transfer for DQ signals.
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HYB18H256321BF
256-Mbit GDDR3
4.11 AC Timings for HYB18H256321BF
Parameter CAS latency Symbol Limit Values TABLE 19
Timing Parameters for HYB18H256321BF
Unit Note
10 11 12 14
Min. Max. Min. Max. Min. Max. Min. Max.
Clock and Clock Enable
System frequency CL=13 fCK13 -- -- -- -- ---- -- -- MHz
1000 -- -- ---- -- -- MHz 1)
CL= 12 fCK12 TBD 900 400 900 400 800 400 700 MHz 2)
800 400 800 400 700 400 650 MHz 1)
CL= 11 fCK11 400 700 400 700 400 650 400 600 MHz 1)
600 400 600 400 550 400 500 MHz 1)
CL =10 fCK10 400 550 400 550 400 500 400 450 MHz 1)
0.55 0.45 0.55 0.45 0.55 0.45 0.55
CL = 9 fCK9 400 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
-- 0.45 -- 0.45 -- 0.45 -- tCK
CL = 8 fCK8 400 tCK 3)
CL = 7 fCK7 400
Clock high level width tCH 0.45
Clock low-level width tCL 0.45
Minimum clock half period tHP 0.45
Command and Address Setup and Hold Timing
Address/Command input setup time tIS 0.24 -- 0.27 -- 0.3 -- 0.35 -- ns
0.24 -- 0.27 -- 0.3 -- 0.35 -- ns
Address/Command input hold time tIH 0.7 -- 0.7 -- 0.7 -- 0.7 -- tCK
Address/Command input pulse width tIP
Mode Register Set Timing
Mode Register Set cycle time tMRD 6 --6 --6 --6 -- tCK 4)5)
Mode Register Set to READ timing
Row Timing tMRDR 12 -- 12 -- 12 -- 12 -- tCK 3)
Row Cycle Time tRC 37 -- 35 -- 34 -- 30 -- tCK
Row Active Time tRAS tCK 6)
ACT(a) to ACT(b) Command period tRRD 23 -- 22 -- 21 -- 18 -- tCK
Row Precharge Time tRP tCK
Row to Column Delay Time for Reads tRCDRD 9 --8 --8 --7 -- tCK
Row to Column Delay Time for Writes tRCDWR tCK 7)
Column Timing 14 -- 13 -- 13 -- 12 --
13 -- 12 -- 12 -- 11 --
tRCDWR(Min) = max(tRCDRD(Min) - (WL + 1) tCK;2tCK)
CAS(a) to CAS(b) Command period tCCD 2 --2 --2 --2 -- tCK 8)
Write to Read Command Delay tWTR 7 --6 --6 --5 -- tCK 9)
Read to Write command delay tRTW tRTW(min)= (CL + BL/2 +2 -WL) tCK 10)
Write Cycle Timing Parameters for Data and Data Strobe
Write command to first WDQS latching tDQSS WL WL+ WL WL+ WL WL+ WL WL+ tCK
transition 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25
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HYB18H256321BF
256-Mbit GDDR3
Parameter CAS latency Symbol Limit Values Unit Note
10 11 12 14
Min. Max. Min. Max. Min. Max. Min. Max.
Data-in and Data Mask to WDQS Setup tDS 0.14 -- 0.15 -- 0.16 -- 0.18 -- ns
Time
Data-in and Data Mask to WDQS Hold tDH 0.14 -- 0.15 -- 0.16 -- 0.18 -- ns
Time
Data-in and DM input pulse width (each tDIPW 0.40 -- 0.40 -- 0.40 -- 0.40 -- tCK
input)
DQS input low pulse width tDQSL 0.40 -- 0.40 -- 0.40 -- 0.40 -- tCK
DQS input high pulse width tDQSH 0.40 -- 0.40 -- 0.40 -- 0.40 -- tCK
DQS Write Preamble Time tWPRE 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQS Write Postamble Time tWPST 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
Write Recovery Time tWR 13 -- 13 -- 12 -- 10 -- tCK 8)
Read Cycle Timing Parameters for Data and Data Strobe
Data Access Time from Clock tAC -0.21 0.21 -0.22 0.22 -0.22 0.22 0.25 0.25 ns
Read Preamble tRPRE 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
Read Postamble tRPST 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
Data-out high impedance time from CLK tHZ tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax ns
Data-out low impedance time from CLK tLZ tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax ns
DQS edge to Clock edge skew tDQSCK -0.21 0.21 -0.22 0.22 -0.22 0.22 0.25 0.25 ns
DQS edge to output data edge skew tDQSQ -- 0.120 -- 0.130 -- 0.140 -- 0.160 ns 11)
Data hold skew factor tQHS -- 0.120 -- 0.130 -- 0.140 -- 0.160 ns
Data output hold time from DQS tQH tHPtQHS ns
Refresh/Power Down Timing
Refresh Period (8192 cycles) tREF -- 32 -- 32 -- 32 -- 32 ms
Average periodic Auto Refresh interval tREFI 3.9 3.9 3.9 3.9 s
Delay from AREF to next ACT/ AREF tRFC 52.0 -- 52.0 -- 52.0 -- 52.0 -- ns
Self Refresh Exit time tXSC 1000 -- 1000 -- 1000 -- 1000 -- tCK
Power Down Exit time tXPN 7 --7 --7 --6 -- tCK
Other Timing Parameters
RES to CKE setup timing tATS 10 -- 10 -- 10 -- 10 -- ns
RES to CKE hold timing tATH 10 -- 10 -- 10 -- 10 -- ns
Termination update Keep Out timing tKO 10 -- 10 -- 10 -- 10 -- ns
Rev. ID EMRS to DQ on timing tRIDon -- 20 -- 20 -- 20 -- 20 ns
Rev. ID EMRS to DQ off timing tRIDoff -- 20 -- 20 -- 20 -- 20 ns
1) DLL on mode ( -10/-11/-12/-14 fCK(Min )= 400 MHz)
2) DLL on mode ( -10/-11/-12/-14 fCK(Min )= 400 MHz)
3) tHP is the lesser of tCL minimum and tCH minimum actually applied to the device CLK, CLK inputs
4) This value of tMRD applies only to the case where the "DLL reset" bit is not activated
5) tMRD is defined from MRS to any other command then READ
6) tRASmax is 8*tREF
7) tRCDWR(Min) may not drop below 2 tCK
Rev. 0.80, 2007-09 34
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Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
8) tCCD is either for gapless consecutive reads or gapless consecutive writes. BL =4
9) WTR and tWR start at the first rising edge of CLK after the last valid (falling) WDQS edge of the slowest WDQS signal
10) Please round up tRTW to the next integer of tCK
11) This parameter is defined per byte
Rev. 0.80, 2007-09 35
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Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
5 Package
5.1 Package Outline
FIGURE 18
Package Outline PG-TFBGA-136-060
-!8
X
-!8
-!8
X
"
!
-!8 # #
-). # 3%!4).' 0,!.%
X
- # ! "
- #
,EAD FREE SOLDER BALLS GREEN SOLDER BALLS &0/?0'
4&"'!??
"AD UNIT MARKING "5- LIGHT GOOD
-IDDLE OF PACKAGES EDGES
0ACKAGE ORIENTATION MARK !
3"!
FIDUCIAL SOLDER BALL ATTACH
/PENING IN SOLDER RESIST
Note: The package is conforming with JEDEC MO-207i, VAR DR-z.
Rev. 0.80, 2007-09 36
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Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
5.2 Package Thermal Characteristics
Theta_jA TABLE 20
2s0p
0 m/s PG-TFBGA-136 Package Thermal Resistances
22
Theta_jB Theta_jC
JEDEC Board 1s0p 1 m/s 3 m/s 1 m/s 3 m/s - -
Air Flow 0 m/s 32 27
K/W 40 19 17 5 2
Notes
1. Theta_jA: Junction to Ambient thermal resistance. The values have been obtained by simulation using the conditions stated
in the JEDEC JESD-51 standard.
2. Theta_jB: Junction to Board thermal resistance. The value has been obtained by simulation.
3. Theta_jC: Junction to Case thermal resistance. The value has been obtained by simulation.
Rev. 0.80, 2007-09 37
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Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
List of Illustrations
Figure 1 Ballout 256-Mbit GDDR3 Graphics RAM [Top View, MF = Low ] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2 Mode Register Set Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3 Mode Register Bitmap for Mid-Range-Speed Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4 Mode Register Bitmap for High-Speed Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5 Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6 Extended Mode Register Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7 Extended Mode Register Bitmap for Mid-Range-Speed Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8 Extended Mode Register Bitmap for High-Speed Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9 Extended Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10 Timing of Vendor Code and Revision ID Generation on DQ[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11 Extended Mode Register 2 Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12 Extended Mode Register 2 Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13 Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14 40 Ohm Driver Pull-Down and Pull-Up Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15 60 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16 120 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17 240 Ohm Active Termination Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18 Package Outline PG-TFBGA-136-060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
List of Tables
Table 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2 Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3 Ball Assignment with Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4 Function Truth Table I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 5 Function Truth Table II (CKE Table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6 Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7 ON/OFF mode of DQ/DM receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 8 Revision ID and Vendor Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10 Power & DC Operation Conditions (0 C Tc 85 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11 DC & AC Logic Input Levels (0 C Tc 85 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12 Differential Clock DC and AC Input conditions (0 C Tc 85 C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13 Pin Capacitances (VDDQ = 1.8 V, TA = 25C, f = 1 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14 Programmed Driver IV Characteristics at 40 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15 Programmed Terminator Characteristics at 60 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 16 Programmed Terminator Characteristics of 120 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 17 Programmed Terminator Characteristics at 240 Ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 18 Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 19 Timing Parameters for HYB18H256321BF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 20 PG-TFBGA-136 Package Thermal Resistances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Ball Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Mirror Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.1
2.4 Function Truth Table for more than one Activated Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Function Truth Table for CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
3.1 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.1 Mode Register Set Command (MRS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.2
3.1.3 Burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.4 Burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.5 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.6 Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.1 DLL Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 Extended Mode Register Set Command (EMRS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.3 DLL enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.4 WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.5 Termination Rtt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Output Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.1 Vendor Code and Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Extended Mode Register 2 Set Command (EMRS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 App Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1
4.2 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.1 Absolute Maximum Ratings and Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3 DC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4
4.5 Recommended Power & DC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6 DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.7 Differential Clock DC and AC Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7.1 Output Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7.2 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.8 Driver current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.9
4.10 Driver IV characteristics at 40 Ohms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.11 Termination IV Characteristic at 60 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Termination IV Characteristic at 120 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Termination IV Characteristic at 240 Ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1 Operating Current Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2 AC Timings for HYB18H256321BF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Package Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Rev. 0.80, 2007-09 40
09132007-07EM-7OYI
Internet Data Sheet
Edition 2007-09
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 Mnchen, Germany
Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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