HPL1117
1A Low Dropout Fast Response Positive Adjustable Regulator and Fixed
1.8V, 2.5V, 2.85V, 3.3V and 5V
Features General Description
Guaranteed Output Voltage Accuracy within 2% The HPL1117 is a low dropout three-terminal adjust-
able regulators with 1A output current capability. In
Fast Transient Response
order to obtain lower dropout voltage and faster tran-
Guaranteed Dropout Voltage at Multiple sient response, which is critical for low voltage ap-
plications , the HPL1117 has been optimized. The
Currents device is available in an adjustable version and fixed
Load Regulation : 0.1% Typ. output voltages of 1.8V, 2.5V, 2.85V, 3.3V and 5V.
Line Regulation : 0.03% Typ. The output available voltage range of an adjustable
version is from 1.25~10.7V with an input supply be-
Low Dropout Voltage : 1.1V Typ. at IOUT =1A low 12V. Dropout voltage is guaranteed at a maxi-
Current Limit : 1A Typ. at TJ=25C mum of 1.3V at 1A. Current limit is trimmed to ensure
specified output current and controlled short-circuit
On-Chip Thermal Limiting : 150C Typ. current. On-chip thermal limiting provides protection
Adjustable Output : 1.25~10.7V against any combination of overload that would cre-
ate excessive junction temperatures. The HPL1117
Standard 3-pin TO-220, TO-252, TO-263 and is available in the industry standard 3-pin TO-220, TO-
252, TO-263, and the low profile surface mount SOT-
SOT-223 Power Packages 223 power packages which can be used in applica-
tions where space is limited.
Applications Pin Description
Active SCSI Terminators Front View for TO-220
Low Voltage Logic Supplies
Post Regulator for Switching Power Supply 3 VIN
2 VOUT
1 ADJ/GND
Front View for TO-263
3 VIN
TAB is VOUT 2 V OUT
1 ADJ/GND
Front View for TO-252
3 VIN
TAB IS VOUT 2 VOUT
1 ADJ/GND
Copyright HIPAC Semiconductor, Inc. 1 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Pin Description (Cont.)
Front View for SOT-223
3 IN
T A B IS V O UT 2 OUT
1 A D J /G N D
Ordering and Marking Information
HPL1117- Package Code
F : TO-220 G : TO-263 U : TO-252 V : SOT-223
Lead Free Code Temp. Range
Handling Code C : 0 to 70 C
Temp. Range
Package Code Handling Code
Voltage Code
TU : Tube TR : Tape & Reel
Voltage Code
18 : 1.8V 25 : 2.5V 28 : 2.85V 33 : 3.3V
50 : 5V
Blank : Adjustable Version
Lead Free Code
L : Lead Free Device Blank : Orginal Device
HPL1117 F/G/U : HPL1117 XXXXX - Date Code HPL1117 V : HPL1117 XXXXX - Date Code
XXXXX XXXXX
18 XXXXX - Date Code HPL1117-18V : HPL1117 XXXXX - Date Code
HPL1117-18F/G/U : HPL1117 XXXXX18
XXXXX
25 XXXXX - Date Code HPL1117-25V : HPL1117 XXXXX - Date Code
HPL1117-25F/G/U : HPL1117 XXXXX25
XXXXX
28 XXXXX - Date Code HPL1117 XXXXX - Date Code
HPL1117-28F/G/U : HPL1117 HPL1117-28V : XXXXX28
XXXXX
33 XXXXX - Date Code HPL1117-33V : HPL1117 XXXXX - Date Code
HPL1117 -33F/G/U : HPL1117 XXXXX33
XXXXX
50 XXXXX - Date Code HPL1117-50V : HPL1117 XXXXX - Date Code
HPL1117 -50F/G/U : HPL1117 XXXXX50
XXXXX
Copyright HIPAC Semiconductor, Inc. 2 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Absolute Maximum Ratings
Symbol Parameter Rating(Note) Unit
VI Input Voltage HPL1117, HPL1117-50, HPL1117-33 15 V
HPL1117-25, HPL1117-18, HPL1117-28 9
TJ Operating Junction Temperature Range C
0 to 125
Control Section
Power Transistor 0 to 150
TSTG Storage Temperature Range -65 to +150 C
TL Lead Temperature (Soldering, 10 second) 260 C
Note : The values here show the absolute maximum rating, and for normal usage please refer the test condition in Electrical
Characteristics Table.
Electrical Characteristics
Unless otherwise noted , these specifications apply over CIN=10uF , COUT=10uF , and TJ=0 to 125C. Typical
values refer to TJ=25C.
Symbol Parameter Test Conditions HPL1117 Unit
Min. Typ. Max.
VREF Reference Voltage 10mA IOUT 1A, 1.4V(VIN -VOUT) 10.75V, 1.225 1.250 1.275 V
TJ =0~125C
VOUT Output Voltage
HPL1117-18 TJ =0~125C, 1.764 1.800 1.836
0 IOUT 1A, 3.1VVIN9V,
HPL1117-25 TJ =0~125C, 2.450 2.500 2.550
0 IOUT 1A, 3.8VVIN9V,
HPL1117-28 TJ =0~125C, 2.790 2.850 2.910 V
0 IOUT1A, 4.25VVIN9V,
HPL1117-33 TJ =0~125C, 3.235 3.300 3.365
0 IOUT 1A, 4.6VVIN12V,
HPL1117-50 TJ =0~125C, 4.900 5.000 5.100
0 IOUT 1A, 6.45VVIN12V,
REGLINE Line Regulation 0.03 0.2
HPL1117 IOUT=10mA, 1.5V(VIN -VOUT )10.75V (Note1)
1 6
HPL1117-18 IOUT=0A, 3.5VVIN9V (Note1)
1 6
HPL1117-25 IOUT=0A, 4VVIN9V (Note1) 6 %mV
HPL1117-28 IOUT=0A, 4.25VVIN 9V (Note1) 1
HPL1117-33 IOUT=0A, 4.75VVIN 12V (Note1)
HPL1117-50 IOUT=0A, 6.45VVIN 12V (Note1) 1 6
1 6
REGLOAD Load Regulation 0.1 0.4
HPL1117 (VIN -VOUT)=3V, 0 IOUT 1A (Note1)
1 10
HPL1117-18 VIN=3.5V, 0 IOUT 1A (Note1)
1 10
HPL1117-25 VIN =4V, 0 IOUT 1A (Note1) 10 %mV
HPL1117-28 VIN=4.25V, 0 IOUT 1A (Note1) 1
HPL1117-33 VIN=4.75V, 0 IOUT 1A (Note1)
HPL1117-50 VIN=6.45V, 0 IOUT 1A (Note1) 1 10
1 10
Copyright HIPAC Semiconductor, Inc. 3 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Electrical Characteristics (Cont.)
Symbol Parameter Test Conditions HPL1117 Unit
Min. Typ. Max.
VD Dropout Voltage IOUT=100mA (Note2) 1 1.1
IOUT=500mA (Note2)
ILIMIT Current Limit IOUT=1A (Note2) 1.05 1.2 V
IADJ Adjust Pin Current (VIN -VOUT)=5V, TJ=25C
IADJ (VIN -VOUT)=3V, IOUT=10mA 1.1 1.3
IO HPL1117
PSRR Adjust Pin Current 10mA IOUT 1A, 1000 mA
TR Change HPL1117 1.4V(VIN -VOUT) 10.75V
TS Minimum Load (VIN -VOUT)=10.75V (Note3) 60 120 A
LS Current HPL1117
VN Ripple Rejection fRIPPLE=120Hz, VRIPPLE=1VP-P, 0.2 5 A
th (VIN -VOUT)=3V
OT Thermal Regulation TJ=25C, 30ms Pulse 1.7 mA
IQ
60 75 dB
0.01 0.02 %/W
Temperature 0.5 %
Stability
0.3 %
Long -Term Stability TJ =125C,1000Hrs. %
0.003 C/ W
RMS Output Noise TJ=25C,10HzF10kHz, (% of VOUT)
15 C
Thermal Resistance Junction to Case, at Tab 50
150
Junction to Ambient
5.5 10 mA
Over Temperature 5.5 10
Point 5.5 10
5.5 10
Quiescent Current 5.5 10
HPL1117-18 VIN9V
HPL1117-25 VIN9V
HPL1117-28 VIN9V
HPL1117-33 VIN12V
HPL1117-50 VIN12V
Note 1 : See thermal regulation specifications for changes in output voltage due to heating effects. Load line regulations are mea-
sured at a constant junction temperature by low duty cycle pulse testing.
Note 2 : Dropout voltage is specified over the full output current range of the device. Dropout voltage is defined as the minimum input/output
differential measured at the specified output current. Test points and limits are also shown on the Dropout Voltage curve.
Note 3 : Minimum load current is defined as the minimum output current required to maintain regulation.
Copyright HIPAC Semiconductor, Inc. 4 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Block Diagram
V IN VOUT
T herm al Current ADJ/GND
Protection Lim it
Voltage
Regulation
Application Circuits Improving Ripple Rejection
1.25V to 10.7V Adjustable Regulator
HPL1117 HPL1117
IN OUT
VIN IN OUT VOUT1 VIN VOUT
+ ADJ 150F
ADJ R1 + 100 F R1
C2 10F R2 121
121 365 1%
1%
+ 10 F + C1
10F
C1* R2
1k
* Needed if device is far from filter capacitors * C1 improves ripple rejection.
XC should be approximately
equal to R1 at ripple frequency
VOUT = 1.250V X R1 + R2
R1
Copyright HIPAC Semiconductor, Inc. 5 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Typical Characteristics
Load Transietn Response Line Transient Response
5 HPL1117-33 0.02 6 HPL1117-33 0.15
4.5
0.01 5
4
Output Current (A) 3.5 Input Voltage (V) 0.1
3 0 4
2.5 -0.01
-0.02 CIN=10F
2
1.5 COUT=10F Tantalum
1 CIN=10F 3 IOUT=0.1A 0.05
0.5 COUT=10F Tantalum
VIN=5V 2
0 0
-100
1
-0.03 0 -0.05
100 300 500 700 900
-20 30 80 130 180
Time (S)
Time (S)
Dropout Voltage vs. Output Current Output Voltage vs. Input Voltage
6
1.25 HPL1117-33
1.2 5
Dropout Voltage (V) 1.15 Output Voltage (V) 4
1.1
3
1.05
2 .
1
0.95 1
0.9 0
0123456789
0 0.2 0.4 0.6 0.8 1
Input Voltage (V)
Output Current (A)
Copyright HIPAC Semiconductor, Inc. 6 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Typical Characteristics Cont.
Input Current vs. Input Voltage Current Limit vs. Input Voltage
HPL1117-33 HPL1117-33
6 2.4
5 2.2
Input Current (mA) Current Limit (A) 2
4
1.8
3
1.6
2
1.4
1 1.2
0 1
0 2 4 6 8 10 12 5 7 9 11 13
Input Voltage (V) Input Voltage (V)
Output Voltage vs. Temperature Output Voltage vs. Temperature
2.6 3.4
2.5
2.4 3.3
Output Voltage (V) 2.3 Output Voltage (V) 3.2
2.2
3.1
2.1 3
2
2.9
1.9
1.8
1.7 2.8
1.6 2.7
-50 -25
-50 -25 0 25 50 75 100 125 0 25 50 75 100 125
Temperature (C) Temperature (C)
Copyright HIPAC Semiconductor, Inc. 7 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Typical Characteristics Cont.
Output Voltage vs. Temperature Input Current vs. Tmeperature
5.3 8 HPL1117-33
5.2 7
Output Voltage (V) 5.1 Input Current (mA) 6
5 5
4.9 4
4.8 3
4.7 0 25 50 75 100 125 2 0 25 50 75 100 125
-50 -25 -50 -25
Temperature (C) Temperature (C)
Current Limit vs. Temperature PSRR vs. Frequency HPL1117-33
HPL1117-33 +0 Cadj=22F
-10 IOUT=0.1A
1.9
Vripple=1Vp-p
1.8 -20
Current Limit (A) 1.7 -30
VIN-VOUT=5V
1.6
PSRR (dB) -40
1.5
-50
1.4 -60
VIN-VOUT>=Vdropout
1.3 -70
1.2 -80
1.1 -90 VIN-VOUT>=3V
5k 10k 20k 50k 200k
1 -100
10 20
-50 0 50 100 150 50 100 200 500 1k 2k
Temperature (C) Frequency (Hz)
Copyright HIPAC Semiconductor, Inc. 8 www.hipacsemi.com
Rev. B.613 - Mar., 2004
HPL1117
Typical Characteristics Cont.
Adjustable Pin Current vs. Temperature
70 HPL1117-Adj
Adjustable Pin Current (A) 68
66
64
62
60
58
56
54
52
50
-50 -25 0 25 50 75 100 125
Temperature (C)
Copyright HIPAC Semiconductor, Inc. 9 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Application Information
Output Voltage Rp
The HPL1117 develops a 1.25V reference voltage be- PARASITIC
tween the output and the adjust terminal. By placing
a resistor between these two terminals, a constant HPL1117 LINE RESISTANCE
Current is caused to flow through R1 and down through
R2 to set the overall output voltage. Normally this VIN IN OUT
current is chosen to be the specified minimum load
current of 10mA. For fixed voltage devices R1 and R2 ADJ
are included in the device.
R1 CONNECT RL
R1 TO CASE
R2
HPL1117 CONNECT
R2 TO LOAD
VIN IN OUT VOUT
R1 Figure 2. Connections for Best Load Regulation
ADJ VREF
R2 Input Capacitor
IADJ
60A An input capacitor of 10F or greater is
recommended. Tantalum, or aluminum electrolytic
VOUT = VREF(1+ RR21)+IADJR2 capacitors can be used for bypassing. Larger Val-
ues will improve ripple rejection by bypassing the in-
Figure 1. Basic Adjustable Regulator put to the regulator.
Load Regulation
When the adjustable regulator is used. Load regula- Output Capacitor
tion will be limited by the resistance of the wire con-
necting the regulator to the load. The data sheet speci- The HPL1117 requires an output capacitor to maintain
fication for load regulation is measured at the output stability and improve transient response. Proper ca-
pin of the device. Best load regulation is obtained pacitor selection is important to ensure proper
when the top of the resistor divider (R1) is tied di- operation. The HPL1117 output capacitor selection is
rectly to the output pin of the device, not to the load. dependent upon the ESR (equivalent series resistance)
For fixed voltage devices the top of R1 is internally of the output capacitor to maintain stability. When the
connected to the output, and the ground pin can be output capacitor is 10uF or greater, the output capaci-
connected to low side of the load. If R1 were con- tor should have an ESR less than 1.This will improve
nected to the load, RP is multiplied by the divider transient response as well as promote stability. A low-
ratio, the effective resistance between the regulator ESR solid tantalum capacitor works extremely well
and the load would be: and provides good transient response and stability over
temperature.
Rp X (1+ RR21), Rp = Parasitic Line Resistance
Copyright HIPAC Semiconductor, Inc. 10 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Application Information (Cont.)
Output Capacitor (Cont.) Figure 3&4 shows for the TO-252 and SOT-223 the
Aluminum electrolytics can also be used, as long as measured values of (J-A) for different copper area
the ESR of the capacitor is <1. The value of the
output capacitor can be increased without limit. Higher sizes using a 2 layers, 1.6mm, and 6Sq. cm FR-4
capacitance values help to improve transient response PCB with 2oz. copper and a ground plane layer on
and ripple rejection and reduce output noise. the backside area used for heatsinking. It can be
used as a rough guideline in estimating thermal
Ripple Rejection resistance.
The curves for Ripple Rejection were generated us- 50
ing an adjustable device with the adjust pin bypassed. TA=25C
With a 22F bypassing capacitor 75dB ripple rejec-
tion is obtainable at any output level. The impedance 45
of the adjust pin capacitor, at the ripple frequency, Thermal Resistance
should be < R1. R1 is normally in the range of 100- (Juntion to Ambient) (C/W) 40
200. The size of the required adjust pin capacitor
is a function of the input ripple frequency. At 120Hz, 35
with R1=100, the adjust pin capacitor should be
13F. For fixed voltage devices, and adjustable de- 30
vices without an adjust pin capacitor, the output ripple
will increase as the ratio of the output voltage to the 25
reference voltage (VOUT /VREF ).
0 2 4 6 8 10 12 14
Top Copper Area (cm2)
Figure 3.
(J-A) vs. copper area for the TO-252 package
Thermal Considerations
HPL1117 has thermal protection which limits junction
temperature to 150C. However, device functionality
is only guaranteed to a maximum junction tempera-
ture of +125C.
Both the TO-220, TO-252, TO-263 and SOT-223
packages use a copper plane on the PCB and the
PCB itself as a heatsink. To optimize the heat sinking
ability of the plane and PCB, solder the tab of the
package to the plane.
Copyright HIPAC Semiconductor, Inc. 11 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Application Information (Cont.)
Thermal Considerations (Cont.)
Thermal Resistance 60
(Juntion to Ambient) (C/W) TA=25C
55
50
45
40
35
30
0 2 4 6 8 10 12 14
Top Copper Area (cm2)
Figure 4.
(J-A) vs. copper area for the SOT-223 package
The thermal resistance for each application will be
affected by thermal interactions with other compo-
nents on the board. Some experimentation will be
necessary to determine the actual value.
The power dissipation of HPL1117 is equal to :
PD = (VIN - VOUT) x IOUT
Maximum junction temperature is equal to :
TJUNCTION = TAMBIENT + (PD x JA)
Note: TJUNCTION must not exceed 125C
Copyright HIPAC Semiconductor, Inc. 12 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Package Information
TO-220 ( Reference JEDEC Registration TO-220)
D
Q
R
be
E b1 e1
L1
H1 L
A c J1
F
M illim eters Inches
Dim Min. Max. Min. Max.
3.56 4.83 0.140 0.190
A 1.14 1.78 0.045 0.070
b1 0.51 1.14 0.020 0.045
b 0.31 1.14 0.012 0.045
c 14.23 16.51 0.560 0.650
D 2.29
e 4.83 2.79 0.090 0.110
e1 9.65 5.33 0.190 0.210
E 0.51 10.67 0.380 0.420
F 5.84 1.40 0.020 0.055
H1 2.03 6.86 0.230 0.270
J1 12.7 2.92 0.080 0.115
L 3.65 14.73 0.500 0.580
L1 3.53 6.35 0.143 0.250
R 2.54 4.09 0.139 0.161
Q 3.43 0.100 0.135
Copyright HIPAC Semiconductor, Inc. 13 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117 A
C1
Package Informaion
TO-252( Reference JEDEC Registration TO-252)
E
b2
L2
b D
H
e1
D1 L1
L
C
A1
E1
Dim Millimeters Inches
A Min. Max. Min. Max.
A1
b 2.18 2.39 0.086 0.094
b2
C 0.89 1.27 0.035 0.050
C1
D 0.508 0.89 0.020 0.035
D1
E 5.207 5.461 0.205 0.215
E1
e1 0.46 0.58 0.018 0.023
H
L 0.46 0.58 0.018 0.023
L1
L2 5.334 6.22 0.210 0.245
5.2 REF 0.205 REF
6.35 6.73 0.250 0.265
5.3 REF 0.209 REF
3.96 5.18 0.156 0.204
9.398 10.41 0.370 0.410
0.51 0.020
0.64 1.02 0.025 0.040
0.89 2.032 0.035 0.080
Copyright HIPAC Semiconductor, Inc. 14 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Package Information
TO-263 ( Reference JEDEC Registration TO-263)
E TERMINAL 4
L2 E1
D D1
L
L3
e b2
b
e1
A
c2
1 R
L4 L1
DETAIL "A"ROTED
c
Dim Min. M illim eters Max. Min. Inches Max.
4.06 0.38 TYP. 4.83 0.160 0.015 TYP. 0.190
A 0.51 2.54 TYP 1.016 0.02 0.100 TYP 0.040
b 1.14 1.651 0.045 0.065
b2
c 1.14 1.40 0.045 0.055
c2 8.64 9.65 0.340 0.380
D 9.65 10.54 0.380 0.415
e
e1 14.60 15.88 0.575 0.625
L 2.24 2.84 0.090 0.110
L1 1.02 2.92 0.040 0.112
L2 1.20 1.78 0.050 0.070
L3
Copyright HIPAC Semiconductor, Inc. 15 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117 A a
Package Information c
SOT-223( Reference JEDEC Registration SOT-223)
D
B1
H E
L
e
e1 K
A1
b
B
Dim Millimeters Inches
Min. Max. Min. Max.
0.06 0.07
A 1.50 1.80
A1 0.02 0.08
B 0.60 0.80 0.02 0.03
0.11 0.12
B1 2.90 3.10 0.01 0.01
0.25 0.26
c 0.28 0.32 0.13 0.15
D 6.30 6.70 0.26 0.29
0.04 0.04
E 3.30 3.70 0.06 0.08
10
e 2.3 BSC 0 0.09 BSC
0.18 BSC
e1 4.6 BSC
13
H 6.70 7.30
L 0.91 1.10
K 1.50 2.00
0 10
13
Copyright HIPAC Semiconductor, Inc. 16 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Physical Specifications
Terminal Material Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb
Lead Solderability Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Packaging 2500 devices per reel
Reflow Condition (IR/Convection or VPR Reflow)
TP tp
Critical Zone
R am p-up TL to TP
Temperature TL tL
Tsmax
Tsm in
R am p-down
ts
Preheat
25 t 25 C to Peak
T im e
Classificatin Reflow Profiles
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Large Body Small Body Large Body Small Body
Average ramp-up rate 3C/second max. 3C/second max.
(TL to TP)
100C 150C
Preheat 150C 200C
- Temperature Min (Tsmin) 60-120 seconds 60-180 seconds
- Temperature Mix (Tsmax)
- Time (min to max)(ts)
Tsmax to TL 183C 3C/second max
- Temperature(TL) 217C
- Time (tL)
Peak Temperature(Tp)
60-150 seconds 60-150 seconds
Time within 5C of actual Peak 225 +0/-5C 240 +0/-5C 245 +0/-5C 250 +0/-5C
Temperature(tp)
Ramp-down Rate 10-30 seconds 10-30 seconds 10-30 seconds 20-40 seconds
Time 25C to Peak Temperature 6C/second max. 6C/second max.
6 minutes max. 8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
Copyright HIPAC Semiconductor, Inc. 17 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Package Reflow Conditions
pkg. thickness 2.5mm pkg. thickness < 2.5mm pkg. thickness < 2.5mm and pkg.
and all bgas and pkg. volume 350mm3 volume < 350mm3
Convection 235 +5/-0C
Convection 220 +5/-0C VPR 235 +5/-0C
VPR 215-219C IR/Convection 235 +5/-0C
IR/Convection 220 +5/-0C
Reliability test program
Test item Method Description
SOLDERABILITY MIL-STD-883D-2003 245C , 5 SEC
HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @ 125 C
PCT JESD-22-B, A102 168 Hrs, 100 % RH , 121C
TST MIL-STD-883D-1011.9 -65C ~ 150C, 200 Cycles
ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V
Latch-Up JESD 78 10ms , Itr > 100mA
Carrier Tape & Reel Dimension
t
Po P D
E
P1
F Bo
W
Ao D1 Ko
T2
J
C
A B
T1
Copyright HIPAC Semiconductor, Inc. 18 www.hipacsemi.com
Rev. B.13 - Mar., 2004
HPL1117
Carrier Tape & Reel Dimension
A p p lica tio n A B C J T1 T2 W P E
TO -252 330 3 100 2 13 0. 5 2 0 .5 16 .4 + 0.3 2.5 0.5 1 6 + 0 .3 8 0 .1 1 .75 0.1
F D D1 Po -0 .2 Ao - 0 .1 Ko t
P1 Bo
7 .5 0 .1 1 .5 + 0.1 1 .5 0 .2 5 4 .0 0 .1 2 .0 0 .1 6 .8 0 .1 1 0 .4 0 .1 2 .5 0 .1 0 .3 0 .0 5
A p p lica tio n A B C J T1 T2 W P E
80 2 13 0. 5 2 0 .5 24 4 2 0.3 24 + 0.3
3803 16 0 .1 1 .7 5 0.1
D D1 Po P1 Ao - 0 .1
TO -263 F 1 .5 + 0.1 Bo Ko t
1.5 0 .25 5.2 0 .1 0 .3 5 0 .0 1
11 .5 0 .1 B C 4 .0 0 .1 2 .0 0 .1 1 0 .8 0.1 1 6 .1 0 .1
6 2 1 .5 P 3
A p p lica tio n A 1 2 .7 5 J T1 T2 W E
D 0 .1 5
3301 D1 2 0 .6 1 2 .4 +0 .2 2 0.2 12 0 .3 8 0 .1 1 .7 5 0.1
S O T -223 F Po P1 Ao Bo Ko t
5 .5 0 .0 5 1 .5 + 0.1 1 .5 + 0.1 4 .0 0 .1 2 .0 0 .0 5 6 .9 0 .1 7 .5 0 .1 2 .1 0 .1 0 .3 0 .0 5
Cover Tape Dimensions
Application Carrier Width Cover Tape Width Devices Per Reel
TO- 252 16 13.3 2500
TO- 263 24 21.3 1000
SOT- 223 12 9.3 2500
CONTACT
HIPAC Semiconductor, Inc.
2540 North First Street, Suite 308
San Jose, CA 95131-1016
U.S.A.
Tel: 1-408-943-0808
Fax: 1-408-943-0878
E-Mail: info@hipacsemi.com
Copyright HIPAC Semiconductor, Inc. 19 www.hipacsemi.com
Rev. B.13 - Mar., 2004
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