MC68HC05X16 MC68HC05X16/D
Rev. 1
TECHNICAL DATA
HC05
MC68HC05X16
MC68HC05X32
MC68HC705X32
TECHNICAL
DATA
1 INTRODUCTION
2 MODES OF OPERATION AND PIN DESCRIPTIONS
3 MEMORY AND REGISTERS
4 INPUT/OUTPUT PORTS
5 MOTOROLA CAN MODULE (MCAN)
6 PROGRAMMABLE TIMER
7 SERIAL COMMUNICATIONS INTERFACE
8 PULSE LENGTH D/A CONVERTERS
9 ANALOG TO DIGITAL CONVERTER
10 RESETS AND INTERRUPTS
11 CPU CORE AND INSTRUCTION SET
12 ELECTRICAL SPECIFICATIONS
13 MECHANICAL DATA
14 ORDERING INFORMATION
15 APPENDICES
1
1 INTRODUCTION
2 MODES OF OPERATION AND PIN DESCRIPTIONS
3 MEMORY AND REGISTERS
4 INPUT/OUTPUT PORTS
5 MOTOROLA CAN MODULE (MCAN)
6 PROGRAMMABLE TIMER
7 SERIAL COMMUNICATIONS INTERFACE
8 PULSE LENGTH D/A CONVERTERS
9 ANALOG TO DIGITAL CONVERTER
10 RESETS AND INTERRUPTS
11 CPU CORE AND INSTRUCTION SET
12 ELECTRICAL SPECIFICATIONS
13 MECHANICAL DATA
14 ORDERING INFORMATION
15 APPENDICES
2
MC68HC05X16
MC68HC05X32
MC68HC705X32
High-density complementary
metal oxide semiconductor
(HCMOS) microcontroller unit
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subject to change without notice.
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MOTOROLA LTD., 1997
3
Conventions
Where abbreviations are used in the text, an explanation can be found in the
glossary, at the back of this manual. Register and bit mnemonics are defined in the
paragraphs describing them.
An overbar is used to designate an active-low signal, eg: RESET.
Unless otherwise stated, a shaded cell in a register diagram indicates that the bit is
either unused or reserved; `u' is used to indicate an undefined state (on reset).
Unless otherwise stated, a pin labelled as `NU' should be tied to VSS in an electrically
noisy environment. Pins labelled `NC' can be left floating, since they are not bonded
to any part of the device.
4
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6
TABLE OF CONTENTS
Paragraph TITLE Page
Number Number
1
INTRODUCTION
1.1 Features ................................................................................................................ 1-2
1.2 Mask options for the MC68HC05X16 .................................................................... 1-3
2
MODES OF OPERATION AND
PIN DESCRIPTIONS
2.1 Modes of operation................................................................................................ 2-1
2.1.1 Single-chip mode ............................................................................................. 2-1
2.1.2 Bootstrap mode ............................................................................................... 2-2
2.1.2.1 Serial RAM loader ...................................................................................... 2-3
2.1.2.2 Jump to RAM + 1 ....................................................................................... 2-3
2.1.2.3 `Jump to any address' ................................................................................ 2-3
2.2 Low power modes ................................................................................................. 2-6
2.2.1 STOP mode ..................................................................................................... 2-6
2.2.2 WAIT mode ...................................................................................................... 2-7
2.2.2.1 Power consumption during WAIT mode ..................................................... 2-8
2.2.3 SLOW mode .................................................................................................... 2-8
2.2.3.1 Miscellaneous register .............................................................................. 2-10
2.3 Pin descriptions ..................................................................................................... 2-11
2.3.1 VDD and VSS .................................................................................................. 2-11
2.3.2 IRQ .................................................................................................................. 2-11
2.3.3 RESET............................................................................................................. 2-11
2.3.4 MDS................................................................................................................. 2-12
2.3.5 TCAP1 ............................................................................................................. 2-12
2.3.6 TCAP2 ............................................................................................................. 2-12
2.3.7 TCMP1............................................................................................................. 2-12
2.3.8 TCMP2............................................................................................................. 2-12
2.3.9 RDI (Receive data in)....................................................................................... 2-12
2.3.10 TDO (Transmit data out) .................................................................................. 2-12
2.3.11 SCLK ............................................................................................................... 2-13
MC68HC05X16 TABLE OF CONTENTS MOTOROLA
Rev. 1 i
7
Paragraph TITLE Page
Number Number
2.3.12 OSC1, OSC2 ................................................................................................... 2-13
2.3.12.1 Crystal........................................................................................................ 2-13
2.3.12.2 Ceramic resonator ..................................................................................... 2-13
2.3.12.3 External clock............................................................................................. 2-13
2.3.12.4 Oscillator division ....................................................................................... 2-15
2.3.13
2.3.14 PLMA ............................................................................................................... 2-15
2.3.15 PLMB ............................................................................................................... 2-15
2.3.16 VPP1 ............................................................................................................... 2-16
2.3.17 VRH ................................................................................................................. 2-16
2.3.18 VRL.................................................................................................................. 2-16
2.3.19 PA0 PA7/PB0 PB7/PC0 PC7 .................................................................. 2-16
2.3.20 NWOI ............................................................................................................... 2-16
2.3.21 PD0/AN0PD7/AN7......................................................................................... 2-16
2.3.22 VDD1 ............................................................................................................... 2-17
2.3.23 VSS1 ............................................................................................................... 2-17
2.3.24 VDDH .............................................................................................................. 2-17
2.3.25 RX0/RX1.......................................................................................................... 2-17
TX0/TX1 .......................................................................................................... 2-17
3
MEMORY AND REGISTERS
3.1 Registers ............................................................................................................... 3-1
3.2 RAM ...................................................................................................................... 3-1
3.3 ROM ...................................................................................................................... 3-1
3.4 Bootstrap ROM...................................................................................................... 3-3
3.5 EEPROM............................................................................................................... 3-4
3.5.1
3.5.2 EEPROM control register ................................................................................ 3-4
3.5.3 EEPROM read operation ................................................................................. 3-6
3.5.4 EEPROM erase operation ............................................................................... 3-6
3.5.5 EEPROM programming operation ................................................................... 3-7
3.6 Options register (OPTR) .................................................................................. 3-7
3.7 EEPROM during STOP mode ............................................................................... 3-8
3.8 EEPROM during WAIT mode ................................................................................ 3-8
Miscellaneous register.......................................................................................... 3-11
4
INPUT/OUTPUT PORTS
4.1 Input/output programming ..................................................................................... 4-1
4.2 Ports A and B ........................................................................................................ 4-2
4.3 Port C .................................................................................................................... 4-3
4.4 Port D .................................................................................................................... 4-4
4.5 Port registers ......................................................................................................... 4-4
MOTOROLA TABLE OF CONTENTS MC68HC05X16
ii Rev. 1
8
Paragraph TITLE Page
Number Number
4.5.1 Port data registers A and B (PORTA and PORTB) .......................................... 4-4
4.5.2 Port data register C (PORTC).......................................................................... 4-5
4.5.3 Port data register D (PORTD).......................................................................... 4-5
4.5.4 A/D status/control register ............................................................................... 4-5
4.5.5 Data direction registers (DDRA, DDRB and DDRC)........................................ 4-6
4.6 Other port considerations ...................................................................................... 4-6
5
MOTOROLA CAN MODULE (MCAN)
5.1 TBF Transmit buffer ............................................................................................ 5-4
5.2 RBF Receive buffer ............................................................................................ 5-4
5.3 Interface to the MC68HC05X16 CPU.................................................................... 5-4
5.3.1 MCAN control register (CCNTRL) ................................................................... 5-6
5.3.2 MCAN command register (CCOM) .................................................................. 5-7
5.3.3 MCAN status register (CSTAT) ........................................................................ 5-10
5.3.4 MCAN interrupt register (CINT) ....................................................................... 5-12
5.3.5 MCAN acceptance code register (CACC)........................................................ 5-13
5.3.6 MCAN acceptance mask register (CACM) ...................................................... 5-14
5.3.7 MCAN bus timing register 0 (CBT0) ................................................................ 5-14
5.3.8 MCAN bus timing register 1 (CBT1) ................................................................ 5-16
5.3.9 MCAN output control register (COCNTRL)...................................................... 5-18
5.3.10 Transmit buffer identifier register (TBI)............................................................. 5-20
5.3.11 Remote transmission request and data length code register (TRTDL)............ 5-20
5.3.12 Transmit data segment registers (TDS) 1 8 .................................................. 5-21
5.3.13 Receive buffer identifier register (RBI) ............................................................. 5-21
5.3.14 Remote transmission request and data length code register (RRTDL) ........... 5-22
5.3.15 Receive data segment registers (RDS) 1 8 .................................................. 5-22
5.4 Interface to the MCAN bus .................................................................................... 5-22
5.4.1 Single wire operation ....................................................................................... 5-24
5.5 Sleep mode ........................................................................................................... 5-24
5.5.1 Sleep comparator reference ............................................................................ 5-25
6
PROGRAMMABLE TIMER
6.1 Counter.................................................................................................................. 6-1
6.1.1 Counter register and alternate counter register ............................................... 6-3
6.2
6.2.1 Timer control and status ........................................................................................ 6-4
6.2.2 Timer control register (TCR) ............................................................................ 6-4
6.3 Timer status register (TSR) ............................................................................. 6-6
6.3.1
6.3.2 Input capture.......................................................................................................... 6-7
Input capture register 1 (ICR1) ........................................................................ 6-7
Input capture register 2 (ICR2) ........................................................................ 6-8
MC68HC05X16 TABLE OF CONTENTS MOTOROLA
Rev. 1 iii
9
Paragraph TITLE Page
Number Number
6.4 Output compare..................................................................................................... 6-9
6.4.1 Output compare register 1 (OCR1) ................................................................. 6-9
6.4.2 Output compare register 2 (OCR2) ................................................................. 6-10
6.4.3 Software force compare................................................................................... 6-11
6.5
6.5.1 Pulse length modulation (PLM) ............................................................................. 6-11
6.6 Pulse length modulation registers A and B (PLMA/PLMB).............................. 6-11
6.7
6.8 Timer during STOP mode ..................................................................................... 6-12
Timer during WAIT mode ...................................................................................... 6-12
Timer state diagrams............................................................................................. 6-12
7
SERIAL COMMUNICATIONS INTERFACE
7.1 SCI two-wire system features................................................................................ 7-1
7.2 SCI receiver features............................................................................................. 7-3
7.3 SCI transmitter features......................................................................................... 7-3
7.4 Functional description ........................................................................................... 7-3
7.5 Data format............................................................................................................ 7-5
7.6 Receiver wake-up operation.................................................................................. 7-5
7.6.1 Idle line wake-up.............................................................................................. 7-6
7.6.2 Address mark wake-up .................................................................................... 7-6
7.7 Receive data in (RDI) ............................................................................................ 7-6
7.8 Start bit detection .................................................................................................. 7-6
7.9 Transmit data out (TDO)........................................................................................ 7-8
7.10 SCI synchronous transmission.............................................................................. 7-9
7.11 SCI registers.......................................................................................................... 7-10
7.11.1 Serial communications data register (SCDR) .................................................. 7-10
7.11.2 Serial communications control register 1 (SCCR1) ......................................... 7-10
7.11.3 Serial communications control register 2 (SCCR2) ......................................... 7-14
7.11.4 Serial communications status register (SCSR) ............................................... 7-16
7.11.5 Baud rate register (BAUD) ............................................................................... 7-18
7.12 Baud rate selection................................................................................................ 7-20
7.13 SCI during STOP mode......................................................................................... 7-21
7.14 SCI during WAIT mode.......................................................................................... 7-21
8
PULSE LENGTH D/A CONVERTERS
8.1 Miscellaneous register........................................................................................... 8-3
8.2 PLM clock selection............................................................................................... 8-4
8.3 PLM during STOP mode ....................................................................................... 8-4
8.4 PLM during WAIT mode ........................................................................................ 8-4
MOTOROLA TABLE OF CONTENTS MC68HC05X16
iv Rev. 1
10
Paragraph TITLE Page
Number Number
9
ANALOG TO DIGITAL CONVERTER
9.1 A/D converter operation......................................................................................... 9-1
9.2 A/D registers.......................................................................................................... 9-3
9.2.1
9.2.2 Port D data register (PORTD).......................................................................... 9-3
9.2.3 A/D result data register (ADDATA) ................................................................... 9-3
9.3 A/D status/control register (ADSTAT)............................................................... 9-4
9.4 A/D converter during STOP mode......................................................................... 9-5
9.5 A/D converter during WAIT mode.......................................................................... 9-6
Port D analog input................................................................................................ 9-6
10
RESETS AND INTERRUPTS
10.1 Resets ................................................................................................................. 10-1
10.1.1 Power-on reset............................................................................................... 10-2
10.1.2 Miscellaneous register .................................................................................. 10-2
10.1.3 RESET pin ..................................................................................................... 10-3
10.1.4 Computer operating properly (COP) watchdog reset .................................... 10-3
10.1.4.1 COP watchdog during STOP mode ......................................................... 10-5
10.1.4.2 COP watchdog during WAIT mode .......................................................... 10-5
10.1.5 Functions affected by reset............................................................................ 10-5
10.2 Interrupts ............................................................................................................. 10-7
10.2.1 Interrupt priorities........................................................................................... 10-9
10.2.2 Nonmaskable software interrupt (SWI) .......................................................... 10-9
10.2.3 Maskable hardware interrupts........................................................................ 10-9
10.2.3.1 Miscellaneous register ............................................................................. 10-10
10.2.3.2 External interrupts.................................................................................... 10-11
10.2.3.3 MCAN interrupt (CIRQ) ............................................................................ 10-11
10.2.3.4 Timer interrupts ........................................................................................ 10-12
10.2.3.5 Serial communications interface (SCI) interrupts..................................... 10-12
10.2.4 Hardware controlled interrupt sequence........................................................ 10-13
11
CPU CORE AND INSTRUCTION SET
11.1 Registers ............................................................................................................. 11-1
11.1.1 Accumulator (A) ............................................................................................. 11-1
11.1.2 Index register (X) ........................................................................................... 11-2
11.1.3 Program counter (PC).................................................................................... 11-2
11.1.4 Stack pointer (SP).......................................................................................... 11-2
11.1.5 Condition code register (CCR)....................................................................... 11-2
11.2 Instruction set ...................................................................................................... 11-3
MC68HC05X16 TABLE OF CONTENTS MOTOROLA
Rev. 1 v
11
Paragraph TITLE Page
Number Number
11.2.1 Register/memory Instructions........................................................................ 11-4
11.2.2 Branch instructions ........................................................................................ 11-4
11.2.3 Bit manipulation instructions.......................................................................... 11-4
11.2.4 Read/modify/write instructions....................................................................... 11-4
11.2.5 Control instructions........................................................................................ 11-4
11.2.6 Tables ............................................................................................................ 11-4
11.3 Addressing modes............................................................................................... 11-11
11.3.1 Inherent ......................................................................................................... 11-11
11.3.2 Immediate ...................................................................................................... 11-11
11.3.3 Direct ............................................................................................................. 11-11
11.3.4 Extended ....................................................................................................... 11-12
11.3.5 Indexed, no offset .......................................................................................... 11-12
11.3.6 Indexed, 8-bit offset ....................................................................................... 11-12
11.3.7 Indexed, 16-bit offset ..................................................................................... 11-12
11.3.8 Relative.......................................................................................................... 11-13
11.3.9 Bit set/clear .................................................................................................... 11-13
11.3.10 Bit test and branch......................................................................................... 11-13
12
ELECTRICAL SPECIFICATIONS
12.1 Absolute maximum ratings .................................................................................. 12-1
12.2 DC electrical characteristics ............................................................................... 12-2
12.3 A/D converter characteristics .............................................................................. 12-4
12.4 Control timing ...................................................................................................... 12-5
12.5 MCAN bus interface DC electrical characteristics ............................................... 12-6
12.6 MCAN bus interface control timing characteristics .............................................. 12-6
13
MECHANICAL DATA
13.1 64-pin quad flat pack (QFP) pinout ..................................................................... 13-1
13.2 64-pin quad flat pack (QFP) mechanical dimensions.......................................... 13-2
14
ORDERING INFORMATION
14.1 EPROMS............................................................................................................. 14-2
14.2 Verification media ................................................................................................ 14-2
14.3 ROM verification units (RVU) .............................................................................. 14-2
MOTOROLA TABLE OF CONTENTS MC68HC05X16
vi Rev. 1
12
Paragraph TITLE Page
Number Number
A
MC68HC05X32
A.1 Features ................................................................................................................A-1
A.2 Memory map, register outline and block diagram..................................................A-2
A.3 Electrical specifications .........................................................................................A-6
A.3.1 Maximum ratings..............................................................................................A-6
A.3.2 DC electrical characteristics ...........................................................................A-7
A.3.3 A/D converter characteristics...........................................................................A-9
A.3.4 Control timing...................................................................................................A-10
A.3.5 MCAN bus interface DC electrical characteristics .................................................A-11
A.3.6 MCAN bus interface control timing characteristics ................................................A-12
B
MC68HC705X32
B.1 Features ................................................................................................................B-2
B.2 VPP6 .....................................................................................................................B-2
B.3 CANE.....................................................................................................................B-2
B.4 Block diagram, memory map and register outline .................................................B-3
B.5 EPROM .................................................................................................................B-7
B.5.1 EPROM read operation....................................................................................B-7
B.5.2 EPROM program operation .............................................................................B-8
B.5.3 EPROM/EEPROM/ECLK control register ........................................................B-8
B.6 EEPROM options register (OPTR) ........................................................................B-11
B.7 Mask option register (MOR) ..................................................................................B-12
B.8 Bootstrap mode .....................................................................................................B-14
B.8.1 Erased EPROM verification and EEPROM erasure ........................................B-17
B.8.2 EPROM/EEPROM parallel bootstrap...............................................................B-17
B.8.3 Serial RAM loader............................................................................................B-20
B.8.3.1 Jump to start of RAM ($0051) ....................................................................B-20
B.9 Electrical specifications .........................................................................................B-23
B.9.1 Maximum ratings..............................................................................................B-23
B.9.2 DC electrical characteristics ............................................................................B-24
B.9.3 EPROM electrical characteristics ....................................................................B-26
B.9.4 Control timing...................................................................................................B-27
B.9.5 A/D converter characteristics...........................................................................B-28
B.9.6 MCAN bus interface DC electrical characteristics ...........................................B-29
B.9.7 MCAN bus interface control timing characteristics ..........................................B-29
MC68HC05X16 TABLE OF CONTENTS MOTOROLA
Rev. 1 vii
13
Paragraph TITLE Page
Number Number
C
MC68HC05X32
HIGH SPEED OPERATION
C.1 DC electrical characteristics ..................................................................................C-1
C.2 Control Timing .......................................................................................................C-2
MOTOROLA TABLE OF CONTENTS MC68HC05X16
viii Rev. 1
14
LIST OF FIGURES
Figure TITLE Page
Number Number
1-1 MC68HC05X16 block diagram ............................................................................... 1-4
2-1 Bootstrap mode function selection flow chart......................................................... 2-2
2-2 MC68HC05X16 `jump to any address' schematic diagram..................................... 2-4
2-3 MC68HC05X16 `load program in RAM and execute' schematic diagram............... 2-5
2-4 STOP and WAIT flow charts................................................................................... 2-9
2-5 Slow mode divider block diagram ........................................................................... 2-10
2-6 Oscillator connections ............................................................................................ 2-14
2-7 Oscillator divider block diagram.............................................................................. 2-15
3-1 Memory map of the MC68HC05X16 ...................................................................... 3-2
3-2 MCAN module memory map .................................................................................. 3-3
4-1 Standard I/O port structure..................................................................................... 4-2
4-2 ECLK timing diagram ............................................................................................. 4-3
4-3 Port logic levels ...................................................................................................... 4-7
5-1 MCAN block diagram.............................................................................................. 5-1
5-2 MCAN frame formats.............................................................................................. 5-2
5-3 MCAN module memory map .................................................................................. 5-5
5-4 Oscillator block diagram ......................................................................................... 5-15
5-5 Segments within the bit time .................................................................................. 5-16
5-6 A typical physical interface between the MCAN and the MCAN bus lines ............. 5-23
6-1 16-bit programmable timer block diagram .............................................................. 6-2
6-2 Timer state timing diagram for reset....................................................................... 6-13
6-3 Timer state timing diagram for input capture .......................................................... 6-13
6-4 Timer state timing diagram for output compare...................................................... 6-14
6-5 Timer state timing diagram for timer overflow......................................................... 6-14
7-1 Serial communications interface block diagram ..................................................... 7-2
7-2 SCI rate generator division ..................................................................................... 7-4
7-3 Data format............................................................................................................. 7-5
7-4 SCI examples of start bit sampling technique ........................................................ 7-7
7-5 SCI sampling technique used on all bits ................................................................ 7-7
7-6 Artificial start following a framing error ................................................................... 7-8
7-7 SCI start bit following a break................................................................................. 7-8
7-8 SCI example of synchronous and asynchronous transmission .............................. 7-9
7-9 SCI data clock timing diagram (M=0) ..................................................................... 7-12
MC68HC05X16 LIST OF FIGURES MOTOROLA
Rev. 1 ix
15
Figure TITLE Page
Number Number
7-10 SCI data clock timing diagram (M=1) ......................................................................7-13
8-1 PLM system block diagram .....................................................................................8-1
8-2 PLM output waveform examples .............................................................................8-2
8-3 PLM clock selection ................................................................................................8-4
9-1 A/D converter block diagram ...................................................................................9-2
9-2 Electrical model of an A/D input pin ........................................................................9-6
10-1 Reset timing diagram ............................................................................................10-1
10-2 RESET external RC pull-down ..............................................................................10-3
10-3 Watchdog system block diagram...........................................................................10-4
10-4 Interrupt flow chart ................................................................................................10-8
11-1 Programming model ..............................................................................................11-1
11-2 Stacking order .......................................................................................................11-2
12-1 Timer relationship..................................................................................................12-5
13-1 64-pin QFP pinout .................................................................................................13-1
13-2 64-pin QFP mechanical dimensions .....................................................................13-2
A-1 MC68HC05X32 block diagram............................................................................... A-2
A-2 Memory map of the MC68HC05X32 ...................................................................... A-3
A-3 Timer relationship................................................................................................... A-11
B-1 MC68HC705X32 block diagram............................................................................. B-3
B-2 Memory map of the MC68HC705X32 .................................................................... B-5
B-3 Modes of operation flow chart ................................................................................ B-15
B-4 Timing diagram with handshake............................................................................. B-18
B-5 Parallel EPROM loader timing diagram.................................................................. B-18
B-6 EPROM parallel bootstrap schematic diagram ...................................................... B-19
B-7 RAM load and execute schematic diagram ............................................................ B-21
B-8 Parallel RAM loader timing diagram ....................................................................... B-22
B-9 Timer relationship................................................................................................... B-27
MOTOROLA LIST OF FIGURES MC68HC05X16
x Rev. 1
16
LIST OF TABLES
Table TITLE Page
Number Number
1-1 Data sheet appendices........................................................................................... 1-1
2-1 Mode of operation selection ................................................................................... 2-1
3-1 EEPROM control bits description ........................................................................... 3-6
3-2 MC68HC05X16 register outline.............................................................................. 3-9
3-3 MCAN register outline ............................................................................................ 3-10
3-4 IRQ and WOI sensitivity ......................................................................................... 3-11
4-1 I/O pin states .......................................................................................................... 4-2
5-1 Synchronization jump width.................................................................................... 5-15
5-2 Baud rate prescaler ................................................................................................ 5-15
5-3 Time segment values ............................................................................................. 5-17
5-4 Output control modes ............................................................................................. 5-18
5-5 MCAN driver output levels...................................................................................... 5-19
5-6 Data length codes .................................................................................................. 5-21
7-1 Method of receiver wake-up ................................................................................... 7-11
7-2 SCI clock on SCLK pin ........................................................................................... 7-13
7-3 First prescaler stage............................................................................................... 7-18
7-4 Second prescaler stage (transmitter) ..................................................................... 7-18
7-5 Second prescaler stage (receiver) ......................................................................... 7-19
7-6 SCI baud rate selection with CPU clock frequency = fOSC/2.................................. 7-20
7-7 SCI baud rate selection with CPU clock frequency = fOSC/8.................................. 7-20
7-8 SCI baud rate selection with CPU clock frequency = fOSC/10................................ 7-20
7-9 SCI transmit baud rate output for a given prescaler output .................................... 7-21
9-1 A/D clock selection ................................................................................................. 9-4
9-2 A/D channel assignment ........................................................................................ 9-5
10-1 Effect of RESET, POR, STOP and WAIT.............................................................. 10-6
10-2 Interrupt priorities ................................................................................................. 10-9
10-3 IRQ and WOI sensitivity ....................................................................................... 10-10
11-1 MUL instruction .................................................................................................... 11-5
11-2 Register/memory instructions............................................................................... 11-5
11-3 Branch instructions............................................................................................... 11-6
11-4 Bit manipulation instructions................................................................................. 11-6
11-5 Read/modify/write instructions ............................................................................. 11-7
11-6 Control instructions............................................................................................... 11-7
MC68HC05X16 LIST OF TABLES MOTOROLA
Rev. 1 xi
17
Table TITLE Page
Number Number
11-7 Instruction set........................................................................................................11-8
11-8 M68HC05 opcode map .........................................................................................11-10
12-1 Absolute maximum ratings ....................................................................................12-1
12-2 DC electrical characteristics..................................................................................12-2
12-3 A/D characteristics ................................................................................................12-4
12-4 Control timing ........................................................................................................12-5
12-5 MCAN bus interface DC electrical characteristics.................................................12-6
12-6 MCAN bus interface control timing characteristics................................................12-6
14-1 MC order numbers ................................................................................................14-1
14-2 EPROMs for pattern generation ............................................................................14-2
A-1 Register outline ...................................................................................................... A-5
A-2 Maximum ratings .................................................................................................... A-6
A-3 DC electrical characteristics................................................................................... A-7
A-4 A/D characteristics ................................................................................................. A-9
A-5 Control timing ......................................................................................................... A-10
1-6 MCAN bus interface DC electrical characteristics.................................................. A-11
1-7 MCAN bus interface control timing characteristics................................................. A-12
B-1 Register outline ...................................................................................................... B-4
B-2 EPROM control bits description ............................................................................. B-9
B-3 EEPROM1 control bits description......................................................................... B-10
B-4 Clock divide ratio selection..................................................................................... B-12
B-5 Mode of operation selection ................................................................................... B-14
B-6 Bootstrap vector targets in RAM ............................................................................ B-20
B-7 Maximum ratings .................................................................................................... B-23
B-8 DC electrical characteristics................................................................................... B-24
B-9 EPROM electrical characteristics........................................................................... B-26
B-10 Control timing ......................................................................................................... B-27
B-11 A/D characteristics ................................................................................................. B-28
B-12 MCAN bus interface DC electrical characteristics.................................................. B-29
B-13 MCAN bus interface control timing characteristics................................................. B-29
C-1 DC electrical characteristics................................................................................... C-1
C-2 Control timing ......................................................................................................... C-2
MOTOROLA LIST OF TABLES MC68HC05X16
xii Rev. 1
18
1
1
INTRODUCTION
The MC68HC05X16 microcomputer (MCU) is a member of Motorola's MC68HC05 family of
low-cost single chip microcomputers. This 8-bit MCU contains an on-board controller area network
module (MCAN), complete with interface circuitry, comprising output drivers, input comparators
and a VDD/2 generator. In addition, the device contains an on-chip oscillator, CPU, RAM, ROM,
EEPROM, A/D converter, pulse length modulated outputs, I/O, serial communications interface,
programmable timer system and watchdog. The fully static design allows operation at frequencies
down to dc, reducing power consumption to a few micro-amps.
This data sheet is structured such that devices similar to the MC68HC05X16 are described in a
set of appendices (see Table 1-1).
Table 1-1 Data sheet appendices
Device Appendix Differences from MC68HC05X16
MC68HC05X32
MC68HC705X32 A 32K bytes ROM; increased RAM
MC68HC05X32
B 32K bytes EPROM; increased RAM; bootstrap firmware
replaced
C 32K bytes ROM; increased RAM; high speed operation
Note: Appendix C contains only electrical characteristics exclusive to the high speed
operation of the MC68HC05X32. For all other information concerning this device, refer
to Appendix A.
MC68HC05X16 INTRODUCTION MOTOROLA
Rev. 1 1-1
19
1 Features
1.1
Hardware features
Fully static design featuring the industry standard M68HC05 family CPU core
On chip crystal oscillator with divide-by -2, -4, -8 or -10, or a software selectable divide-by -32,
-64, -128 or -160 option (SLOW mode)
352 bytes of RAM
15102 bytes of user ROM plus 16 bytes of user vectors
256 bytes of byte erasable EEPROM with internal charge pump and security bit
Write/erase protect bit for 224 of the 256 bytes EEPROM
Bootstrap firmware
Power saving STOP, WAIT and SLOW modes
Three 8-bit parallel I/O ports and one 8-bit input-only port; wired-OR interrupt capability on all
port B pins
Motorola controller area network (MCAN) with line interface circuitry
Software option available to output the internal E-clock to port pin PC2
16-bit timer with 2 input captures and 2 output compares
Computer operating properly (COP) watchdog timer
Serial communications interface system (SCI) with independent transmitter/receiver baud rate
selection; receiver wake-up function for use in multi-receiver systems
8 channel A/D converter
2 pulse length modulation systems which can be used as D/A converters
One interrupt request input plus 4 on-board hardware interrupt sources
2.2 MHz bus speed
40 to +125C temperature range
Available in 64-pin quad flat pack (QFP) package
Complete development system support available using the MMDS05 or M68MMPFB0508
development station with the M68EML05X32 emulation module or the M68HC05XEVS
evaluation system
MOTOROLA INTRODUCTION MC68HC05X16
1-2 Rev. 1
20
1
1.2 Mask options for the MC68HC05X16
The MC68HC05X16 has six mask options that are programmed during manufacture and must be
specified on the order form.
Oscillator division ratio selection (divide-by-2, -4, -8 or -10)
Oscillator start-up delay following power-on or STOP (tPORL) = 16 or 4064 cycles
Automatic watchdog enable/disable following a power-on or external reset
Watchdog enable/disable during WAIT mode
Wired-OR interrupt enable
Resistive pull-downs on ports B and/or C
Note: It is recommended that an external clock is always used if tPORL is set to 16 cycles. This
will prevent any problems arising from oscillator stability when the device is put into
STOP mode.
MC68HC05X16 INTRODUCTION MOTOROLA
Rev. 1 1-3
21
1
256 bytes PA0
EEPROM PA1
PA2
VPP1 Charge pump 15118 bytes Port A PA3
user ROM PA4
RESET COP watchdog (including 16 bytes Port B PA5
IRQ user vectors) PA6
Oscillator PA7
OSC2 576 bytes
OSC1 2 / 4 / 8 / 10 bootstrap ROM PB0
PB1
VDD1 Line MCAN 352 bytes PB2
VSS1 interface RAM PB3
VDDH PB4
16-bit Port C PB5
TX0 programmable PB6
TX1 M68HC05 PB7
RX0 CPU timer
RX1 PC0
Port D 8-bit SCI PC1
NWOI A/D converter PC2/ECLK
MDS PLM PC3
PC4
VDD PC5
VSS PC6
PC7
PD0/AN0
PD1/AN1 TCMP1
PD2/AN2 TCMP2
PD3/AN3 TCAP1
PD4/AN4 TCAP2
PD5/AN5
PD6/AN6 RDI
PD7/AN7 SCLK
TDO
VRH
VRL PLMA D/A
PLMB D/A
Figure 1-1 MC68HC05X16 block diagram
MOTOROLA INTRODUCTION MC68HC05X16
1-4 Rev. 1
22
2
2
MODES OF OPERATION AND
PIN DESCRIPTIONS
2.1 Modes of operation
The MC68HC05X16 MCU has two modes of operation, single-chip mode and bootstrap mode. In
the MC68HC05X16 the single-chip mode is the normal user operating frequency Table 2-1 shows
the conditions required to enter each mode on the rising edge of RESET.
Table 2-1 Mode of operation selection
MDS IRQ TCAP1 TCAP2 PD3 PD4 Mode
VSS AND VSS to VDD VSS to VDD X X X Single-chip
VDD OR 2VDD VSS X 0 0 Reserved for Motorola use
Bootstrap mode:
VDD OR 2VDD VDD VSS 1 1 Serial RAM loader
VDD OR 2VDD VDD VSS 1 0 Jump to RAM + 1
VDD OR 2VDD VDD VSS 0 1 Jump to any address
Note: On the rising edge of RESET, holding the IRQ pin at 2 x VDD is equivalent to holding
the MDS pin at VDD. The device cannot enter single-chip mode unless MDS is tied to
VSS (or left floating) and IRQ is below VDD.
2.1.1 Single-chip mode
This is the normal user operating mode of the MC68HC05X16. In this mode the device functions
as a self-contained microcomputer (MCU) with all on-board peripherals, including the three 8-bit
I/O ports and the 8-bit input-only port, available to the user. All address and data activity occurs
within the MCU.
MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA
Rev. 1 2-1
23
2.1.2 Bootstrap mode
2 To place the part in bootstrap mode, the following conditions must be met during transition of the
RESET pin from low to high:
1) IRQ pin at 2xVDD OR MDS pin at VDD
2) TCAP1 pin at VDD
3) TCAP2 pin at VSS
PD4 and PD3 are connected according to the values given in Table 2-1 to select the device's
function from the following three functions:
Execute serial RAM loader program
Jump to RAM + 1
Jump to any address
If the SEC bit in the option register is set, on first entering bootstrap mode the RAM and the EEPROM
are completely erased. The option register which contains the security bit is erased last, before any
program can be executed. The bootstrap software is implemented in the following locations:
RAM load and execute from $03B0 to $03FD
Vectors and program select from $7F80 to $7FEF
ENTRY
SEC bit active? YES
NO
Save PD in RAM. Erase
whole EEPROM + RAM
and check EPROM +
SEC bit.
PD3 set
NO ? YES
PD4 set PD4 set
NO ? YES NO ? YES
Reserved for Jump to address Jump to RAM + 1. Serial RAM bootstrap
Motorola use. defined by ports A, B loader.
and C.
Figure 2-1 Bootstrap mode function selection flow chart
MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS MC68HC05X16
2-2 Rev. 1
24
Note: Oscillator divide-by-two is forced in bootstrap mode; all other mask options are selected
by the customer (see Section 1.2). 2
2.1.2.1 Serial RAM loader
In the `load program in RAM and execute' routine, user programs are loaded into MCU RAM via
the SCI port and then executed. Data is loaded sequentially, starting at RAM location $0050, until
the last byte is loaded. The first byte loaded is the count of the total number of bytes in the program
plus the count byte. After completion of RAM loading, control can be transferred either to the
second byte in RAM, $0051, by executing a jump to RAM + 1 function, or it can be transferred to
any address by executing a jump to any address function. During the firmware initialization stage,
the SCI is configured for the NRZ data format (idle line, start bit, eight data bits and stop bit). The
baud rate is 9600 with a 4 MHz crystal. A program to convert ASCII S-records to the format
required by the RAM loader is available from Motorola.
When the last byte is loaded, the firmware halts operation expecting additional data to arrive. At
this point, the reset switch is placed in the reset position which resets the MCU, but keeps the RAM
program intact. All routines loaded in RAM can now be entered from this state, including the one
which executes the program in RAM (see Section 2.1.2.2 and Section 2.1.2.3).
To load a program in the EEPROM, the `load program in RAM and execute' function is also used.
In this instance the process involves two distinct steps. Firstly, the RAM is loaded with a program
which controls the loading of the EEPROM, and when the RAM contents are executed, the MCU
is instructed to load the EEPROM.
The erased state of the EEPROM is $FF.
Figure 2-3 shows the schematic diagram of the circuit required for the serial RAM loader.
2.1.2.2 Jump to RAM + 1
After the serial RAM loader program is completed this function can be used to execute a program
loaded in RAM starting at the second RAM address, $0051. It must be noted that the lowest RAM
address, $0050, is used by the RAM loader program to store the total number of bytes in the
program.
2.1.2.3 `Jump to any address'
This function allows execution of programs previously loaded in RAM or EEPROM using the
methods outlined in Section 2.1.2.1.
To execute the `jump to any address' function, data input at port A has to be $CC and data input at
port B and port C should represent the MSB and LSB respectively, of the address to jump to for
execution of the user program. A schematic diagram of the circuit required is shown in Figure 2-2.
MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA
Rev. 1 2-3
25
2 10 nF 47 mF P1
GND
+5V
2xVDD
10 k
RESET
VDD
RESET OSC1
OSC2
0.01 mF
22 pF 4 MHz 22 pF
10 k
8 x 10 k optional (see note) IRQ 3 x 10 k 10 k
PD3 10 k
PA7 PD4 10 k
PA6 TCAP1
PA5 MC68HC05X16 VRH optional
PA4 VRL
PA3 VPP1
PA2 PLMA
PA1 PLMB
PA0 SCLK
RDI
MSB 8 x 10 k PB7 TDO
8 x 10 k PB6 TCMP2
Select required address PB5 TCAP2 Connect as required
PB4 TCMP1 for the application
PB3
LSB PB2 PD7
PB1 PD6
PB0 PD5
PD2
PC7 PD1
PC6 PD0
PC5
PC4
PC3
PC2
PC1
PC0
VSS
Note: These eight resistors are optional; direct connection is possible if pins PA0-PA7, PB0-PB7 and PC0-PC7 are
kept in input mode during application.
Figure 2-2 MC68HC05X16 `jump to any address' schematic diagram
MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS MC68HC05X16
2-4 Rev. 1
26
10 nF 47 mF P1 2
GND
+5V
2xVDD
10 k
RESET
VDD
RESET OSC1
OSC2
0.01 mF
22 pF
4 MHz 22 pF
IRQ
PD3 10 k
PD4
9600 Bd TCAP1
VRH
RS232 level translator RDI VRL 10 k
VPP1 10 k
suggested: TDO PLMA 10 k
PLMB
RS232 MC145406 or MAX232 SCLK 3 x 10 k
PA7 MC68HC05X16 TCMP2 optional
PA6 TCAP2
Connect as required PA5 TCMP1 Connect as required
for the application PA4 for the application
PA3 PD7
PA2 PD6
PA1 PD5
PA0 PD2
PD1
PB7 PD0
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
VSS
Figure 2-3 MC68HC05X16 `load program in RAM and execute' schematic diagram
MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA
Rev. 1 2-5
27
2.2 Low power modes
2 The STOP and WAIT instructions have different effects on the programmable timer, the serial
communications interface, the watchdog system, the EEPROM and the A/D converter. These
different effects are described in the following sections.
2.2.1 STOP mode
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the
internal oscillator is turned off (providing the MCAN is `asleep', see Section 5.5) halting all internal
processing including timer, serial communications interface and the A/D converter (see flow chart
in Figure 2-4). The MCU will wake up from STOP mode only by receipt of an MCAN external
interrupt or by the detection of a reset (logic low on RESET pin or a power-on reset.
The STOP instruction can be executed (i.e. the oscillator can be turned off) only when the MCAN
module is in SLEEP mode. See Section 5.5.
During STOP mode, the I-bit in the CCR is cleared to enable external interrupts (see
Section 11.1.5). The SM bit is cleared to allow nominal speed operation for the 4064 cycles count
while exiting STOP mode (see Section 2.2.3).
All other registers and memory remain unaltered and all input/output lines remain unchanged. This
continues until a MCAN interrupt, wired-OR interrupt, external interrupt (IRQ) or reset is sensed,
at which time the internal oscillator is turned on. The interrupt or reset causes the program counter
to vector to the corresponding locations ($3FFA, B and $3FFE, F respectively).
When leaving STOP mode, a tPORL internal cycles delay is provided to give the oscillator time to
stabilise before releasing CPU operation. This delay is selectable via a mask option to be either 16
or 4064 cycles. The CPU will resume operation by servicing the interrupt that wakes it up, or by
fetching the reset vector, if reset wakes it up.
Note: If tPORL is selected to be 16 cycles, it is recommended that an external clock signal is
used to avoid problems with oscillator stability while the device is in STOP mode.
The stacking corresponding to an eventual interrupt to go out of STOP mode will only
be executed when going out of STOP mode.
The following list summarizes the effect of STOP mode on the modules of the MC68HC05X16.
The watchdog timer is reset; see Section 10.1.4.1
The EEPROM acts as read-only memory (ROM); see Section 3.6
All SCI activity stops; see Section 7.13
The timer stops counting; see Section 6.6
The PLM outputs remain at current levels; see Section 8.3
The A/D converter is disabled; see Section 9.3
The I-bit in the CCR is cleared
MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS MC68HC05X16
2-6 Rev. 1
28
2.2.2 WAIT mode
The WAIT instruction places the MCU in a low power consumption mode, but WAIT mode 2
consumes more power than STOP mode. All CPU action is suspended and the watchdog is
disabled, but the timer, A/D and SCI and MCAN systems remain active and operate as normal (see
flow chart in Figure 2-4). All other memory and registers remain unaltered and all parallel
input/output lines remain unchanged. The programming or erase mechanism of the EEPROM is
also unaffected, as well as the charge pump high voltage generator.
During WAIT mode the I-bit in the CCR is cleared to enable all interrupts. The INTE bit in the
miscellaneous register (Section 2.2.3.1) is not affected by WAIT mode. When any interrupt or reset
is sensed, the program counter vectors to the locations containing the start address of the interrupt
or reset service routine.
Any interrupt or reset condition causes the processor to exit WAIT mode.
If an interrupt exit from WAIT mode is performed, the state of the remaining systems will be
unchanged.
If a reset exit from WAIT mode is performed the entire system reverts to the disabled reset state.
Note: The stacking corresponding to an eventual interrupt to leave WAIT mode will only be
executed when leaving WAIT mode.
MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA
Rev. 1 2-7
29
The following list summarizes the effect of WAIT mode on the modules of the MC68HC05X16.
2 The watchdog timer functions according to the mask option selected; see
Section 10.1.4.2
The EEPROM is not affected; see Section 3.7
The SCI is not affected; see Section 7.14
The timer is not affected; see Section 6.7
The PLM is not affected; see Section 8.4
The A/D converter is not affected; see Section 9.4
The I-bit in the CCR is cleared
The MCAN module is unaffected
2.2.2.1 Power consumption during WAIT mode
Power consumption during WAIT mode depends on how many systems are active. The power
consumption will be highest when all the systems (A/D, timer, EEPROM, SCI and MCAN) are
active, and lowest when the EEPROM erase and programming mechanism, SCI and A/D are
disabled and the MCAN is in SLEEP mode. The timer cannot be disabled in WAIT mode. It is
important that before entering WAIT mode, the programmer sets the relevant control bits for the
individual modules to reflect the desired functionality during WAIT mode.
Power consumption may be further reduced by the use of SLOW mode. (See Section 2.2.3).
2.2.3 SLOW mode
The SLOW mode function is controlled by the SM bit in the miscellaneous register at location
$000C. It allows the user to insert, under software control, an extra divide-by-16 between the
oscillator and the internal clock driver (see Figure 2-5). This feature allows all the internal
operations to slow down and thus reduces power consumption.
Warning: The SLOW mode function should not be enabled while using the A/D converter or while
erasing/programming the EEPROM unless the internal A/D RC oscillator is turned on.
MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS MC68HC05X16
2-8 Rev. 1
30
STOP WAIT 2
YES Watchdog active?
NO Oscillator active. Timer,
SCI, A/D, EEPROM clocks
Stop oscillator and all active. Processor clocks
clocks.
stopped. Clear I-bit
Clear I bit.
NO Reset ? NO
Reset ?
NO CIRQ, YES YES WOI ? NO
wired-OR, external
interrupt?
YES Timer interrupt ? NO
YES
YES SCI ? NO
Turn on oscillator. YES NO
Wait for time delay to CIRQ ?
stabilise Restart processor clock
YES
Generate watchdog
interrupt
(1) Fetch reset vector or (1) Fetch reset vector or
(2) Service interrupt: (2) Service interrupt:
a. stack a. stack
b. set I-bit b. set I-bit
c. vector to interrupt c. vector to interrupt
routine routine
Figure 2-4 STOP and WAIT flow charts
MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA
Rev. 1 2-9
31
2 OSC1 OSC2
pin pin
fOSC 2, 4,
Oscillator 8 and 10 16
2
MCAN
SMbit Control logic
(bit 1, $000C)
Main internal clock
Note: The MCAN module clock is unaffected during SLOW mode.
Figure 2-5 Slow mode divider block diagram
2.2.3.1 Miscellaneous register
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Miscellaneous $000C POR INTP INTN INTE SFA SFB SM WDOG u001 000u
SM -- Slow mode
1 (set) The system runs at a bus speed 16 times lower than normal (fOSC/32,
/64, /128 or /160). SLOW mode affects all sections of the device
(including SCI, A/D and timer) except for the MCAN module.
0 (clear) The system runs at normal bus speed (fOSC/2, /4, /8 or /10).
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
Note: The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS MC68HC05X16
2-10 Rev. 1
32
2.3 Pin descriptions
2
2.3.1 VDD and VSS
Power is supplied to the microcontroller using these two pins. VDD is the positive supply and VSS
is ground.
It is in the nature of CMOS designs that very fast signal transitions occur on the MCU pins. These
short rise and fall times place very high short-duration current demands on the power supply. To
prevent noise problems, special care must be taken to provide good power supply bypassing at
the MCU. Bypass capacitors should have good high-frequency characteristics and be as close to
the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are
loaded.
2.3.2 IRQ
This is an input-only pin for external interrupt sources. Interrupt triggering is selected using the
INTP and INTN bits in the miscellaneous register, to be one of four options detailed in Table 10-3.
In addition, the external interrupt facility (IRQ) can be disabled using the INTE bit in the
Miscellaneous register (see Section 3.8). It is only possible to change the interrupt option bits in
the miscellaneous register while the I-bit is set. Selecting a different interrupt option will
automatically clear any pending interrupts. Further details of the external interrupt procedure can
be found in Section 10.2.3.2.
The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. A
high voltage detector is provided on this pin to select modes of operation other than single-chip
mode. See Section 2.1.
2.3.3 RESET
This active low I/O pin is used to reset the MCU. Applying a logic zero to this pin forces the device
to a known start-up state. An external RC-circuit can be connected to this pin to generate a
power-on reset (POR) if required. In this case, the time constant must be great enough (at least
100ms) to allow the oscillator circuit to stabilise. This input has an internal Schmitt trigger to
improve noise immunity. When a reset condition occurs internally, i.e. from the COP watchdog, the
RESET pin provides an active-low open drain output signal that may be used to reset external
hardware.
MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA
Rev. 1 2-11
33
2.3.4 MDS
2 A pull-down device is activated on this pin each time the RESET pin is pulled low. Even after the
RESET pin is pulled high, the pull-down on the MDS pin will remain active until the pin is pulled
high. In single-chip mode MDS can be connected to VSS or left floating. When MDS is tied to VDD
at the end of reset, it is used to select any mode of operation other than single-chip mode. This
has the same effect as tying IRQ to 2VDD. See Section 2.1.
Note: Although this pin can be left floating to select single-chip mode, it is advisable to
hard-connect it to VSS, especially in an electrically noisy environment.
2.3.5 TCAP1
The TCAP1 input controls the input capture 1 function of the on-chip programmable timer system.
2.3.6 TCAP2
The TCAP2 input controls the input capture 2 function of the on-chip programmable timer system.
2.3.7 TCMP1
The TCMP1 pin is the output of the output compare 1 function of the timer system.
2.3.8 TCMP2
The TCMP2 pin is the output of the output compare 2 function of the timer system.
2.3.9 RDI (Receive data in)
The RDI pin is the input pin of the SCI receiver.
2.3.10 TDO (Transmit data out)
The TDO pin is the output pin of the SCI transmitter.
MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS MC68HC05X16
2-12 Rev. 1
34
2.3.11 SCLK
The SCLK pin is the clock output pin of the SCI transmitter. 2
2.3.12 OSC1, OSC2
These pins provide control input for an on-chip oscillator circuit. A crystal, ceramic resonator or
external clock signal connected to these pins supplies the oscillator clock. The oscillator frequency
(fOSC) is divided by two, four, eight or ten to give the internal bus frequency (fOP). There is also a
software option which introduces an additional divide by 16 into the oscillator clock, giving an
internal bus frequency of fOSC/32, /64, /128 or /160.
2.3.12.1 Crystal
The circuit shown in Figure 2-6(a) is recommended when using either a crystal or a ceramic
resonator. An internal feedback resistor is provided on-chip between OSC1 and OSC2.
Figure 2-6(d) lists the recommended capacitance values. The internal oscillator is designed to
interface with an AT-cut parallel-resonant quartz crystal resonator in the frequency range specified
for fOSC (see Section 12.4). Use of an external CMOS oscillator is recommended when crystals
outside the specified ranges are to be used. The crystal and associated components should be
mounted as close as possible to the input pins to minimise output distortion and start-up
stabilization time. The manufacturer of the particular crystal being considered should be consulted
for specific information.
2.3.12.2 Ceramic resonator
A ceramic resonator may be used instead of a crystal in cost sensitive applications for frequencies up
to 8MHz external. The circuit shown in Figure 2-6(a) is recommended when using either a crystal or a
ceramic resonator. Figure 2-6(d) lists the recommended capacitance and feedback resistance values.
The manufacturer of the particular ceramic resonator being considered should be consulted for specific
information. This option is recommended only for applications that operate at an external clock
frequency of 8MHz or less. Any application requiring an external operating frequency greater that
8MHz should use either a crystal oscillator or an external CMOS compatible clock source.
2.3.12.3 External clock
When using an external clock the OSC1 and OSC2 pins should be driven in antiphase, as shown
in Figure 2-6(c). The tOXOV or tILCH specifications (see Section 12.4) do not apply when using an
external clock input. The equivalent specification of the external clock source should be used in
lieu of tOXOV or tILCH.
MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA
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35
L C1 RS
2 OSC1 OSC2
C0
MCU
OSC1 OSC2
(b) Crystal equivalent circuit
COSC1 COSC2
MCU
(a) Crystal/ceramic resonator OSC1 OSC2
oscillator connections
External NC
clock
(c) External clock source connections
Crystal Ceramic resonator
2MHz 4MHz Unit 2 4MHz Unit
RS(max) 400 75 W RS(typ) 10 W
C0 5 7 pF C0 40 pF
C1 8 12 F C1 4.3 pF
COSC1 15 40 15 30 pF COSC1 30 pF
COSC2 15 30 15 25 pF COSC2 30 pF
Q 30 000 40 000 -- Q 1250 --
(d) Typical crystal and ceramic resonator parameters
Figure 2-6 Oscillator connections
MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS MC68HC05X16
2-14 Rev. 1
36
2.3.12.4 Oscillator division
The external oscillator can run up to 22MHz. For this reason an additional clock predivider is 2
provided; its division ratio is selected via a mask option (see Section 1.2). This allows a CPU clock
two, four, eight or ten times slower than the external clock, provided that SLOW mode has not been
entered. If the device is in SLOW mode, a further divide-by-16 oscillator predivider reduces the
CPU clock frequency to a frequency 32, 64, 128 or 160 times slower than the oscillator clock. The
MCAN is directly clocked with the external oscillator frequency divided by two. A block diagram of
the oscillator divider circuit is given in Figure 2-7.
OSC1 OSC2 Mask option
pin pin
2 MCAN clock MCAN module
Oscillator 1, 2, 2 16
4, or 5
fOSC/2, /4, /8 or /10 fOSC/32, /64,
/128 or /160
SM bit Control logic
Main internal clock
Figure 2-7 Oscillator divider block diagram
2.3.13 PLMA
The PLMA pin is the output of pulse length modulation converter A.
2.3.14 PLMB
The PLMB pin is the output of pulse length modulation converter B.
MC68HC05X16 MODES OF OPERATION AND PIN DESCRIPTIONS MOTOROLA
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37
2.3.15 VPP1
2 The VPP1 pin is the output of the charge pump for the EEPROM1 array.
2.3.16 VRH
The VRH pin is the positive reference voltage for the A/D converter.
2.3.17 VRL
The VRL pin is the negative reference voltage for the A/D converter.
2.3.18 PA0 PA7/PB0 PB7/PC0 PC7
These 24 I/O lines comprise ports A, B and C. The state of any pin is software programmable, and
all the pins are configured as inputs during power-on or reset.
Under software control the PC2 pin can output the internal E-clock (see Section 4.2).
Resistive pull downs are provided on port B and/or port C and can be enabled via a mask option
(see Section 1.2). Wired-OR interrupt capability is provided on all pins of port B (see
Section 10.2.3.3).
2.3.19 NWOI
This pin provides another wired-OR interrupt capability in addition to port B. Wired-OR interrupts
are requested when this pin is pulled high (if wired-OR interrupts are enabled), i.e. interrupt
sensitivity on this pin is complementary to sensitivity on the IRQ pin (see Table 10-3 in
Section 10.2.3.1). When this pin is not in use it is recommended that it be tied to VSS in noisy
conditions. It is not necessary to tie NWOI to VSS when there is a negligible amount of noise
present.
2.3.20 PD0/AN0PD7/AN7
This 8-bit input only port (D) shares its pins with the A/D converter. When enabled, the A/D
converter uses pins PD0/AN0 PD7/AN7 as its analog inputs. On reset, the A/D converter is
disabled which forces the port D pins to be input only port pins (see Section 9.5).
MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS MC68HC05X16
2-16 Rev. 1
38
2.3.21 VDD1
This pin is the power input for the input comparator of the MCAN module. 2
2.3.22 VSS1
This pin is the ground connection for the input comparator of the MCAN bus.
2.3.23 VDDH
This pin provides the high voltage reference output for the MCAN bus. The output voltage is equal
to VDD2.
2.3.24 RX0/RX1
These input pins connect the physical bus lines to the input comparator (receive). When the MCAN
is in SLEEP mode, a dominant level on these pins will wake it up.
2.3.25 TX0/TX1
These output pins connect the output drivers of the MCAN bus to the physical bus lines (transmit).
MCAN bus lines. The bus can have one of two complementary values: dominant or recessive.
During simultaneous transmission of dominant and recessive bits the resulting bus value will be
dominant. For example with a positive logic wired-AND implementation of the bus, the dominant
level would correspond to a logic 0 and the recessive level to a logic 1.
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2
THIS PAGE LEFT BLANK INTENTIONALLY
MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS MC68HC05X16
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40
3 3
MEMORY AND REGISTERS
The MC68HC05X16 MCU is capable of addressing 16384 bytes of memory and registers with its
program counter. The memory map includes 15118 bytes of user ROM (including user vectors),
576 bytes of bootstrap ROM, 352 bytes of RAM and 256 bytes of EEPROM.
3.1 Registers
All the I/O, control and status registers of the MC68HC05X16 are contained within the first 32-byte
block of the memory map, as shown in Figure 3-1. MCAN registers are contained in the next 30
bytes of memory.
The miscellaneous register is shown in Section 3.8 as this register contains bits which are relevant
to several modules.
3.2 RAM
The user RAM comprises 176 bytes of memory, from $0050 to $00FF. This is shared with a 64 byte
stack area. The stack begins at $00FF and may extend down to $00C0. The user RAM also
comprises 176 bytes from $0250 to $02FF which is completely free for the user.
Note: Using the stack area for data storage or temporary work locations requires care to prevent
the data from being overwritten due to stacking from an interrupt or subroutine call.
3.3 ROM
The user ROM consists of 15118 bytes of ROM mapped as follows:
15102 bytes of user ROM from $0300 to $3DFD
16 bytes of user vectors from $3FF0 to $3FFF
MC68HC05X16 MEMORY AND REGISTERS MOTOROLA
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41
MC68HC05X16 Registers
3 $0000 Port A data register $0000
I/O Ports Port B data register $0001
(32 bytes) 7 bytes
Port C data register $0002
$0020 Port D input data register $0003
$003E MCAN EEPROM/ECLK Port A data direction register $0004
$0050 registers control
$00C0 1 byte Port B data direction register $0005
$0100 RAM I
$0101 Stack (176 bytes) A/D Port C data direction register $0006
$0120 converter
OPTR (1 byte) 2 bytes E/EEPROM/ECLK control register $0007
$0200 Non protected (31 bytes)
PLM system A/D data register $0008
$0250 EEPROM 2 bytes
(256 bytes) A/D status/control register $0009
Protected (224 bytes) Miscellaneous
1 byte Pulse length modulation A $000A
Bootstrap ROM I
(80 bytes) SCI Pulse length modulation B $000B
5 bytes
RAM II Miscellaneous register $000C
176 bytes Timer
14 bytes SCI baud rate register $000D
MCAN SCI control register 1 $000E
control registers
SCI control register 2 $000F
10 bytes
SCI status register $0010
MCAN
transmit buffer SCI data register $0011
10 bytes Timer control register $0012
MCAN Timer status register $0013
receive buffer
Capture high register 1 $0014
10 bytes
Capture low register 1 $0015
$0300 Compare high register 1 $0016
ROM Compare low register 1 $0017
(15102 bytes)
Counter high register $0018
$3DFE Counter low register $0019
$3E00
Alternate counter high register $001A
Bootstrap ROM II Alternate counter low register $001B
(498 bytes)
Capture high register 2 $001C
$3FF01 CIRQ Capture low register 2 $001D
$3FF23 SCI Compare high register 2 $001E
$3FF45 Timer overflow Compare low register 2 $001F
$3FF67 Timer output compare 1& 2 User Options register $0100
$3FF89 Timer input capture 1& 2 Vectors
$3FFAB WOI, External IRQ Mask options register $3DFE
$3FFCD SWI
$3FFEF Reset/power-on reset Reserved
Figure 3-1 Memory map of the MC68HC05X16
MOTOROLA MEMORY AND REGISTERS MC68HC05X16
3-2 Rev. 1
42
MCAN register blocks MCAN registers
$0020 MCAN Control register $0020
control registers
$0029 Command register $0021
$002A 10 bytes
Status register $0022
$0033 MCAN
$0034 transmit buffer Interrupt register $0023 3
$003D 10 bytes Acceptance code register $0024
MCAN Acceptance mask register $0025
receive buffer
Bus timing register 1 $0026
10 bytes
Bus timing register 2 $0027
Output control register $0028
Test register $0029
Identifier $002A
RTR-bit, data length code $002B
Data segment byte 1 $002C
Data segment byte 2 $002D
Data segment byte 3 $002E
Data segment byte 4 $002F
Data segment byte 5 $0030
Data segment byte 6 $0031
Data segment byte 7 $0032
Data segment byte 8 $0033
Identifier $0034
RTR-bit, data length code $0035
Data segment byte 1 $0036
Data segment byte 2 $0037
Data segment byte 3 $0038
Data segment byte 4 $0039
Data segment byte 5 $003A
Data segment byte 6 $003B
Data segment byte 7 $003C
Data segment byte 8 $003D
Figure 3-2 MCAN module memory map
3.4 Bootstrap ROM
There are two areas of bootstrap ROM (ROMI and ROMII) located from $0200 to $024F (80 bytes)
and $3DFE to $3FEF (498 bytes) respectively.
MC68HC05X16 MEMORY AND REGISTERS MOTOROLA
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43
3.5 EEPROM
The user EEPROM consists of 256 bytes of memory located from address $0100 to $01FF. 255
bytes are general purpose and 1 byte is used by the option register. The non-volatile EEPROM is
3 byte erasable.
An internal charge pump provides the EEPROM voltage (VPP1), which removes the need to supply
a high voltage for erase and programming functions. The charge pump is a capacitor/diode ladder
network which will give a very high impedance output of around 20-30 M. The voltage of the
charge pump is visible at the VPP1 pin. During normal operation of the device, where
programming/erasing of the EEPROM array will occur, VPP1 should never be connected to either
VDD or VSS as this could prevent the charge pump reaching the necessary programming voltage.
Where it is considered dangerous to leave VPP1 unconnected for reasons of excessive noise in a
system, it may be tied to VDD; this will protect the EEPROM data but will also increase power
consumption, and therefore it is recommended that the protect bit function is used for regular
protection of EEPROM data (see Section 3.5.5).
In order to achieve a higher degree of security for stored data, there is no capability for bulk or row
erase operations.
The EEPROM control register ($0007) provides control of the EEPROM programming and erase
operations.
Warning: The VPP1 pin should never be connected to VSS, as this could cause permanent
damage to the device.
3.5.1 EEPROM control register
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
EEPROM/ECLK control $0007 WOIE CAF 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000
WOIE -- Wired-OR interrupt enable
This bit is used to enable wired-OR interrupts on the NWOI pin and on all port B pins which have
been programmed as inputs. Wired-OR interrupts can only be enabled if the WOI mask option is
selected (see Section 1.2). WOIE is forced to zero if this mask option is not selected. Power-on
reset clears the WOIE bit.
1 (set) Wired-OR interrupts are enabled (provided that wired-OR interrupts
have been selected as a mask option).
0 (clear) Wired-OR interrupts are disabled.
MOTOROLA MEMORY AND REGISTERS MC68HC05X16
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44
CAF -- MCAN asleep flag
This flag is set by the MCU when the MCAN module enters SLEEP mode. This is the only
indication that the MCAN is asleep (see Section 5.5). The bit is cleared when the MCAN wakes up.
1 (set) The MCAN module is in SLEEP mode. 3
0 (clear) The MCAN module is not in SLEEP mode.
ECLK -- External clock option bit
See Section 4.3 for a description of this bit.
E1ERA -- EEPROM erase/programming bit
Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the
EEPROM is for erasing or programming purposes.
1 (set) An erase operation will take place.
0 (clear) A programming operation will take place.
Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.
E1LAT -- EEPROM programming latch enable bit
1 (set) Address and data can be latched into the EEPROM for further
program or erase operations, providing the E1PGM bit is cleared.
0 (clear) Data can be read from the EEPROM.The E1ERA bit and the E1PGM
bit are reset to zero when E1LAT is `0'.
STOP, power-on and external reset clear the E1LAT bit.
Note: After the tERA1 erase time or tPROG1 programming time, the E1LAT bit has to be reset
to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM -- EEPROM charge pump enable/disable
1 (set) Internal charge pump generator switched on.
0 (clear) Internal charge pump generator switched off.
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array.
This bit cannot be set before the data is selected, and once this bit has been set it can only be
cleared by clearing the E1LAT bit.
A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are give in Table 3-1.
Note: Not all combinations are shown in Table 3-1, since the E1PGM and E1ERA bits are
cleared when the E1LAT bit is at zero, resulting in a read condition.
MC68HC05X16 MEMORY AND REGISTERS MOTOROLA
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45
Table 3-1 EEPROM control bits description
E1ERA E1LAT E1PGM Description
0 0 0 Read condition
3 0 1 0 Ready to load address/data for program/erase
0 1 1 Byte programming in progress
1 1 0 Ready for byte erase (load address)
1 1 1 Byte erase in progress
3.5.2 EEPROM read operation
To be able to read from EEPROM, the E1LAT bit has to be at logic zero, as shown in Table 3-1.
While this bit is at logic zero, the E1PGM bit and the E1ERA bit are permanently reset to zero and
the 256 bytes of EEPROM may be read as if it were a normal ROM area. The internal charge pump
generator is automatically switched off since the E1PGM bit is reset.
If a read operation is executed while the E1LAT bit is set (erase or programming sequence), data
resulting from the operation will be $FF.
Note: When not performing any programming or erase operation, it is recommended that
EEPROM should remain in the read mode (E1LAT = 0)
3.5.3 EEPROM erase operation
To erase the contents of a byte of the EEPROM, the following steps should be taken:
1 Set the E1LAT bit.
2 Set the E1ERA bit (1& 2 may be done simultaneously with the same
instruction).
3 Write address/data to the EEPROM address to be erased.
4 Set the E1PGM bit.
5 Wait for a time tERA1.
6 Reset the E1LAT bit (to logic zero).
While an erase operation is being performed, any access of the EEPROM array will not be
successful.
The erased state of the EEPROM is $FF and the programmed state is $00.
Note: Data written to the address to be erased is not used, therefore its value is not significant.
MOTOROLA MEMORY AND REGISTERS MC68HC05X16
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46
If a second word is to be erased, it is important that the E1LAT bit be reset before restarting the
erasing sequence, otherwise any write to a new address will have no effect. This condition provides
a higher degree of security for the stored data.
User programs must be running from the RAM or ROM as the EEPROM will have its address and
data buses latched. 3
3.5.4 EEPROM programming operation
To program a byte of EEPROM, the following steps should be taken:
1 Set the E1LAT bit.
2 Write address/data to the EEPROM address to be programmed.
3 Set the E1PGM bit.
4 Wait for time tPROG1.
5 Reset the E1LAT bit (to logic zero).
While a programming operation is being performed, any access of the EEPROM array will not be
successful.
Warning: To program a byte correctly, it has to have been previously erased.
If a second word is to be programmed, it is important that the E1LAT bit be reset before restarting
the programming sequence otherwise any write to a new address will have no effect. This condition
provides a higher degree of security for the stored data.
User programs must be running from the RAM or ROM as the EEPROM will have its address and
data buses latched.
Note: 224 bytes of EEPROM (address $0120 to $01FF) can be program and erase protected
under the control of bit 1 of the OPTR register detailed in Section 3.5.5.
3.5.5 Options register (OPTR)
This register (OPTR), located at $0100, contains the secure and protect functions for the EEPROM
and allows the user to select options in a non-volatile manner. The contents of the OPTR register
are loaded into data latches with each power-on or external reset.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Options (OPTR)(1) $0100 EE1P SEC Not affected
(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
MC68HC05X16 MEMORY AND REGISTERS MOTOROLA
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47
EE1P EEPROM protect bit
In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts,
both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to
$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit
3 of the options register.
1 (set) Part 2 of the EEPROM array is not protected; all 256 bytes of EEPROM
can be accessed for any read, erase or programming operations
0 (clear) Part 2 of the EEPROM array is protected; any attempt to erase or
program a location will be unsuccessful
When this bit is set (erased), the protection will remain until the next power-on or external reset.
EE1P can only be written to `0' when the ELAT bit in the EEPROM control register is set.
SEC Security bit
This high security bit allows the user to secure the EEPROM data from external accesses. When
the SEC bit is at `0', the EEPROM contents are secured by preventing any entry to test mode. The
only way to erase the SEC bit to `1' externally is to enter bootstrap mode, at which time the entire
EEPROM contents will be erased. When the SEC bit is changed, its new value will have no effect
until the next external or power-on reset.
3.6 EEPROM during STOP mode
When entering STOP mode, the EEPROM is automatically set to the read mode and the VPP1
high voltage charge pump generator is automatically disabled.
3.7 EEPROM during WAIT mode
The EEPROM is not affected by WAIT mode. Any program/erase operation will continue as in
normal operating mode. The charge pump is not affected by WAIT mode, therefore it is possible to
wait the tERA1 erase time or tPROG1 programming time in WAIT mode.
Under normal operating conditions, the charge pump generator is driven by the internal CPU
clocks. When the operating frequency is low, e.g. during slow mode (see Figure 3.8) or during
WAIT mode, the clocking should be done by the internal A/D RC oscillator. The RC oscillator is
enabled by setting the ADRC bit of the A/D status/control register at $0009.
MOTOROLA MEMORY AND REGISTERS MC68HC05X16
3-8 Rev. 1
48
Table 3-2 MC68HC05X16 register outline
Register name Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on
reset
Port A data (PORTA) $0000 Undefined 3
Port B data (PORTB) $0001 Undefined
Port C data (PORTC) $0002 PC2/ Undefined
ECLK
Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
Port A data direction (DDRA) $0004 0000 0000
Port B data direction (DDRB) $0005 0000 0000
Port C data direction (DDRC) $0006 0000 0000
EEPROM/ECLK control $0007 WOIE CAF 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000
A/D data (ADDATA) $0008 0000 0000
A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000
Pulse length modulation A (PLMA) $000A 0000 0000
Pulse length modulation B (PLMB) $000B 0000 0000
SM WDOG(2) u001 000u
Miscellaneous $000C POR(1) INTP INTN INTE SFA SFB
SCI baud rate (BAUD) $000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undefined
SCI control 2 (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000
SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u
SCI data (SCDR) $0011 0000 0000
Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undefined
Input capture high 1 $0014 Undefined
Input capture low 1 $0015 Undefined
Output compare high 1 $0016 Undefined
Output compare low 1 $0017 Undefined
Timer counter high $0018 1111 1111
Timer counter low $0019 1111 1100
Alternate counter high $001A 1111 1111
Alternate counter low $001B 1111 1100
Input capture high 2 $001C Undefined
Input capture low 2 $001D Undefined
Output compare high 2 $001E Undefined
Output compare low 2 $001F Undefined
Options (OPTR)(3) $0100 EE1P SEC Not affected
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
MC68HC05X16 MEMORY AND REGISTERS MOTOROLA
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Table 3-3 MCAN register outline
Register name Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on
reset
3 Control (CCNTRL) $0020 MODE SPD OIE EIE TIE RIE RR 0u - u uuu1
Command (CCOM) TR 00u0 0000
$0021 RX0 RX1 COMPSEL SLEEP COS RRB AT
Status (CSTAT) $0022 BS ES TS RS TCS TBA DO RBS uu00 1100
Interrupt (CINT) $0023 WIF OIF EIF TIF RIF - - - 0 0000
Acceptance code (CACC)(1)
Acceptance mask (CACM)(1) $0024 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Undefined
Bus timing 0 (CBT0)(1) $0025 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Undefined
Bus timing 1 (CBT1)(1)
$0026 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Undefined
Output control (COCNTRL)(1)
$0027 SAMP TSEG22TSEG21TSEG20TSEG13TSEG12TSEG11TSEG10 Undefined
$0028 OCTP1 OCTN1 OCPOL1 OCTP0 OCTN0 OCPOL0 OCM1 OCM0 Undefined
(reserved) $0029
Transmit buffer identifier (TBI) $002A ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 Undefined
RTR-bit, data length code (TRTDL) $002B ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 DLC0 Undefined
Transmit data segment 1 (TDS1) $002C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Transmit data segment 2 (TDS2) $002D DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Transmit data segment 3 (TDS3) $002E DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Transmit data segment 4 (TDS4) $002F DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Transmit data segment 5 (TDS5) $0030 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Transmit data segment 6 (TDS6) $0031 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Transmit data segment 7 (TDS7) $0032 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Transmit data segment 8 (TDS8) $0033 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Receive buffer identifier (RBI) $0034 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 Undefined
RTR-bit, data length code (RRTDL) $0035 ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 DLC0 Undefined
Receive data segment 1 (RDS1) $0036 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Receive data segment 2 (RDS2) $0037 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Receive data segment 3 (RDS3) $0038 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Receive data segment 4 (RDS4) $0039 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Receive data segment 5 (RDS5) $003A DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Receive data segment 6 (RDS6) $003B DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Receive data segment 7 (RDS7) $003C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
Receive data segment 8 (RDS8) $003D DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
(1) These registers can only be accessed when the reset request bit in the control register is set.
MOTOROLA MEMORY AND REGISTERS MC68HC05X16
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50
3.8 Miscellaneous register
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Miscellaneous $000C POR(1) INTP INTN INTE SFA SFB SM WDOG(2) u001 000u 3
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
POR -- Power-on reset bit (see Section 10.1)
This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the
user to make a software distinction between a power-on and an external reset. This bit cannot be
set by software and is cleared by writing it to zero.
1 (set) A power-on reset has occurred.
0 (clear) No power-on reset has occurred.
INTP, INTN -- External interrupt sensitivity options (see Section 10.2)
These two bits allow the user to select which edge the IRQ pin and WOI will be sensitive to (see
Table 3-4). Both bits can be written to only while the I-bit is set, and are cleared by power-on or
external reset, thus the device is initialised with negative edge and low level sensitivity.
Table 3-4 IRQ and WOI sensitivity
INTP INTN IRQ sensitivity WOI interrupt options
0 0 Negative edge and low level sensitive Positive edge and high level sensitive
0 1 Negative edge only Positive edge only
1 0 Positive edge only Negative edge only
1 1 Positive and negative edge sensitive Positive and negative edge sensitive
INTE -- External interrupt enable (see Section 10.2)
1 (set) External interrupt function (IRQ) enabled.
0 (clear) External interrupt function (IRQ) disabled.
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
SFA -- Slow or fast mode selection for PLMA (see Section 8.1)
1 (set) Slow mode PLMA (4096 x timer clock period).
0 (clear) Fast mode PLMA (256 x timer clock period).
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SFB -- Slow or fast mode selection for PLMB (see Section 8.1)
1 (set) Slow mode PLMB (4096 x timer clock period).
0 (clear) Fast mode PLMB (256 x timer clock period).
3 Note: The highest speed of the PLM system corresponds to the frequency of the TOF bit
being set, multiplied by 256. The lowest speed of the PLM system corresponds to the
frequency of the TOF bit being set, multiplied by 16.
Warning: Because the SFA bit and SFB bit are not double buffered, it is mandatory to set the SFA
bit and the SFB bit to the desired values before writing to the PLM registers; not doing
so could temporarily give incorrect values at the PLM outputs.
SM -- Slow mode (see Section 2.2.3)
1 (set) The system runs at a bus speed 16 times lower than normal
(fOSC/32). SLOW mode affects all sections of the device, including
SCI, A/D and timer.
0 (clear) The system runs at normal bus speed (fOSC/2).
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
WDOG -- Watchdog enable/disable (see Section 10.1.4)
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
1 (set) Watchdog counter cleared and enabled.
0 (clear) The watchdog cannot be disabled by software; writing a zero to this
bit has no effect.
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4
INPUT/OUTPUT PORTS 4
In single-chip mode, the MC68HC05X16 has a total of 24 I/O lines, arranged as three 8-bit ports
(A, B and C), and eight input-only lines, arranged as one 8-bit port (D). Each I/O line is individually
programmable as either input or output, under the software control of the data direction registers.
The 8-bit input-only port (D) shares its pins with the A/D converter, when the A/D converter is
enabled. To avoid glitches on the output pins, data should be written to the I/O port data register
before writing ones to the corresponding data direction register bits to set the pins to output mode.
4.1 Input/output programming
The bidirectional port lines may be programmed as inputs or outputs under software control. The
direction of each pin is determined by the state of the corresponding bit in the port data direction
register (DDR). Each port has an associated DDR. Any I/O port pin is configured as an output if
its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding
DDR bit is cleared to a logic zero.
At power-on or reset, all DDRs are cleared, thus configuring all port pins as inputs. The data
direction registers can be written to or read by the MCU. During the programmed output state, a
read of the data register actually reads the value of the output data latch and not the I/O pin. The
operation of the standard port hardware is shown schematically in Figure 4-1.
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Data direction DDRn
register bit
M68HC05 internal connections
Latched data DATA Output I/O
register bit buffer Pin
4 O/P DDRn DATA I/O Pin
data
buffer
1 0 0
Output
1 1 1
Input
buffer 0 0 tristate
Input
1 tristate
0
Figure 4-1 Standard I/O port structure
Table 4-1 shows the effect of reading from or writing to an I/O pin in various circumstances. Note
that the read/write signal shown is internal and not available to the user.
Table 4-1 I/O pin states
R/W DDRn Action of MCU write to/read of data bit
0 0 The I/O pin is in input mode. Data is written into the output data latch.
0 1 Data is written into the output data latch, and output to the I/O pin.
1 0 The state of the I/O pin is read.
1 1 The I/O pin is in output mode. The output data latch is read.
4.2 Ports A and B
These ports are standard M68HC05 bidirectional I/O ports, each comprising a data register and a
data direction register.
Reset does not affect the state of the data register, but clears the data direction register, thereby
returning all port pins to input mode. Writing a `1' to any DDR bit sets the corresponding port pin
to output mode.
Wired-OR interrupts are provided on all pins of port B. If WOIE is enabled, any combination of high
logic levels on port B pins which are programmed as inputs will trigger an external interrupt. See
Section 10.2.3.2.
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A mask option is provided to enable resistive pull downs on all port B pins that are programmed
as inputs.
4.3 Port C
In addition to the standard port functions described for ports A and B, port C pin 2 can be
configured, using the ECLK bit of the EEPROM/ECLK control register, to output the CPU clock. If 4
this is selected the corresponding DDR bit is automatically set and bit 2 of port C will always read
the output data latch. The other port C pins are not affected by this feature.
A mask option is provided to enable resistive pull downs on all port C pins that are programmed
as inputs.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
EEPROM/ECLK control $0007 0 0 0 0 ECLK E1ERA E1LAT E1PGM 0000 0000
ECLK -- External clock option bit
1 (set) ECLK CPU clock is output on PC2.
0 (clear) ECLK CPU clock is not output on PC2; port C acts as a normal I/O port.
The ECLK bit is cleared by power-on or external reset. It is not affected by the execution of a STOP
or WAIT instruction.
The timing diagram of the clock output is shown in Figure 4-2.
Internal clock (PHI2)
External clock (ECLK/PC2)
Output port (if write to output port)
Figure 4-2 ECLK timing diagram
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4.4 Port D
This 8-bit input-only port shares its pins with the A/D converter subsystem. When the A/D
converter is enabled, pins PD0-PD7 read the eight analog inputs to the A/D converter. Port D can
be read at any time, however, if it is read during an A/D conversion sequence noise, may be
injected on the analog inputs, resulting in reduced accuracy of the A/D. Furthermore, performing
a digital read of port D with levels other than VDD or VSS on the port D pins will result in greater
power dissipation during the read cycle.
4 As port D is an input-only port there is no DDR associated with it. Also, at power up or external
reset, the A/D converter is disabled, thus the port is configured as a standard input-only port.
Note: It is recommended that all unused input ports and I/O ports be tied to an appropriate
logic level (i.e. either VDD or VSS).
4.5 Port registers
The following sections explain in detail the individual bits in the data and control registers
associated with the ports.
4.5.1 Port data registers A and B (PORTA and PORTB)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Port A data (PORTA) $0000 Undefined
Port B data (PORTB)
$0001 Undefined
Each bit can be configured as input or output via the corresponding data direction bit in the port
data direction register (DDRx).
The state of the port data registers following reset is not defined.
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4.5.2 Port data register C (PORTC)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Port C data (PORTC) $0002 PC2/ Undefined
ECLK
Each bit can be configured as input or output via the corresponding data direction bit in the port
data direction register (DDRx). 4
In addition, bit 2 of port C is used to output the CPU clock if the ECLK bit in the EEPROM
CTL/ECLK register is set (see Section 4.3).
The state of the port data registers following reset is not defined.
4.5.3 Port data register D (PORTD)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
All the port D bits are input-only and are shared with the A/D converter. The function of each bit is
determined by the ADON bit in the A/D status/control register.
The state of the port data registers following reset is not defined.
4.5.4 A/D status/control register
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
A/D status/control $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000
ADON -- A/D converter on
1 (set) A/D converter is switched on; all port D pins act as analog inputs for
the A/D converter.
0 (clear) A/D converter is switched off; all port D pins act as input only pins.
Reset clears the ADON bit, thus configuring port D as an input only port.
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4.5.5 Data direction registers (DDRA, DDRB and DDRC)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Port A data direction (DDRA) $0004 0000 0000
Port B data direction (DDRB)
Port C data direction (DDRC) $0005 0000 0000
$0006 0000 0000
4 Writing a `1' to any bit configures the corresponding port pin as an output; conversely, writing any
bit to `0' configures the corresponding port pin as an input.
Reset clears these registers, thus configuring all ports as inputs.
4.6 Other port considerations
All output ports can emulate `open-drain' outputs. This is achieved by writing a zero to the relevant
output port latch. By toggling the corresponding data direction bit, the port pin will either be an
output zero or tri-state (an input). This is shown diagrammatically in Figure 4-3.
When using a port pin as an `open-drain' output, certain precautions must be taken in the user
software. If a read-modify-write instruction is used on a port where the `open-drain' is assigned and
the pin at this time is programmed as an input, it will read it as a `one'. The read-modify-write
instruction will then write this `one' into the output data latch on the next cycle. This would cause
the `open-drain' pin not to output a `zero' when desired.
Note: `Open-drain' outputs should not be pulled above VDD.
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Read buffer output
(a)
A Y
Data direction register bit DDRn
DDRn A Y 4
1 0 0
1 1 1 Normal operation tri state
0 0 tri state
0 1 tri state
(b)
1 0 low
1 1 -- `Open-drain'
0 0 high
0 1 high
VDD `Open-drain' output
VDD (c)
Px0 DDRx, bit 0 = 0
Portx, bit 0 = 0
DDRx, bit 0 = 0
Figure 4-3 Port logic levels Portx, bit 0 = 0
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4
THIS PAGE LEFT BLANK INTENTIONALLY
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5
MOTOROLA CAN MODULE (MCAN)
The MCAN includes all hardware modules necessary to implement the CAN transfer layer, which 5
represents the kernel of the CAN bus protocol as defined by BOSCH GmbH, the originators of the
CAN specification. For full details of the CAN protocol please refer to the published specifications.
Up to the message level, the MCAN is totally compatible with the full CAN implementation.
Functional differences are related to the object layer only. Whereas a full CAN controller provides
dedicated hardware for handling a set of messages, the MCAN is restricted to receiving and/or
transmitting messages on a message by message basis.
The MCAN will never initiate an overload frame. If the MCAN starts to receive a valid message
(one that passes the acceptance filter) and there is no receive buffer available for it then the
overrun flag in the CPU status register will be set. The MCAN will respond to overload frames
generated by other CAN nodes, as required by the CAN protocol. A summary of all the MCAN
frame formats is given in Figure 5-2 for reference. A diagram of the major blocks of the MCAN is
shown in Figure 5-1.
Interface Bit timing Line
management logic interface
logic Transceive logic
logic
Transmit
buffer Error MCAN
Receive management bus
buffer 0 line
Receive logic
buffer 1
Bit stream
Microprocessor related logic processor
Bus line related logic
Figure 5-1 MCAN block diagram
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5
MOTOROLA
5-2
Data frame (number of bits = 44 + 8N)
Start of frame 12 6 8N (0 N 8) 16 CRC Del 7
ID10 Arbitration field Control field Data field CRC field Acknowledge End of frame
Ack Del
11 4 8 8 15 r rrrrrrrr
ID0 CRC
Figure 5-2 MCAN frame formats RTR
MOTOROLA CAN MODULE (MCAN) RB1
RB0
DLC3
DLC0
d ddd
Identifier Reserved bits Data
Acceptance length
code
filtering
Stored in transmit/receive buffers
Stored in buffers Bit stuffing
Remote frame (number of bits = 44)
12 6 16 7 Note: A remote frame is identical to a
Arbitration field Control field CRC field End of frame data frame, except that the RTR
bit is recessive, and there is no
11 4 15 data field.
Start of frame CRC CRC Del
ID10 Acknowledge
ID0 Ack Del
RTR
RB1
RB0
DLC3
DLC0
d r dd r rrrrrrrr
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MC68HC05X16 Error frame
Rev. 1
6 6 8 Note: An error frame can start
Data frame Error flag Echo Error delimiter Inter-frame space anywhere in the middle of a
or error flag or frame.
remote frame overload frame
Figure 5-2 MCAN frame formats (Continued) ddddddd ddr r r r r r r r
MOTOROLA CAN MODULE (MCAN) Inter-frame space Note: INT = Intermission
Suspend transmission is only for
3 8 Bus idle Start of frame Data frame error passive nodes.
Any frame INT Suspend or
transmit
remote frame
rrrrrrrrrrrrrrrrrrrr r r rd
Overload frame
End of frame Note: An overload frame can only start
or at the end of a frame.
6 8 Inter-frame space Maximum echo of overload flag
error delimiter or is one bit.
or Overload flag Overload delimiter
error frame
overload delimiter
MOTOROLA dddddddr r r r r r r r
5-3
5
63
5.1 TBF Transmit buffer
The transmit buffer is an interface between the CPU and the bit stream processor (BSP) and is
able to store a complete message. The buffer is written by the CPU and read by the BSP. The CPU
may access this buffer whenever transmit buffer access is set to released. On requesting a
transmission (by setting transmission request in the MCAN command register to present) transmit
buffer access is set to locked, giving the BSP exclusive access to this buffer. The transmit buffer is
released after the message transfer has been completed or aborted.
The TBF is 10 bytes long and holds the identifier (1 byte), the control field (1 byte) and the data
field (maximum length 8 bytes). The buffer is implemented as a single-ported RAM, with mutually
exclusive access by the CPU and the BSP.
5
5.2 RBF Receive buffer
The receive buffer is an interface between the BSP and the CPU and stores a message received
from the bus line. Once filled by the BSP and allocated to the CPU (by the IML), the receive buffer
cannot be used to store subsequent received messages until the CPU has acknowledged the
reading of the buffer's contents. Thus, unless the CPU releases a receive buffer within a protocol
defined time frame, future messages to be received may be lost.
To reduce the requirements on the CPU, two receive buffers (RBF0 and RBF1) are implemented.
While one receive buffer is allocated to the CPU, the BSP may write to the other buffer. RBF0 and
RBF1 are each 10 bytes long and hold the identifier (1 byte), the control field (1 byte) and the data
field (maximum length 8 bytes). The buffers are implemented as single-ported RAMs with mutually
exclusive access from the CPU and the BSP. The BSP signals the MCU to read the receive buffer
only when the message being received has an identifier that passes the acceptance filter. Note
that a message being transmitted will be automatically written to the receive buffer if the identifier
passes the acceptance filter. This is because it cannot be known, until after the first byte has been
stored, whether or not the transmitting node will lose arbitration to another node.
5.3 Interface to the MC68HC05X16 CPU
The MCAN handles all the communication transactions flowing across the serial bus. For example,
the CPU merely places a message to be transmitted into the transmit buffer and sets the TR bit.
The MCAN will begin transmitting the message when it has determined that the bus is idle. In the
event of a transmission error, the MCAN will initiate a repeated transmission automatically.
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In a similar manner, the CPU module is notified that a message has been received only if it was
error free. If any error occurs, the MCAN signals the error within the CAN protocol without CPU
intervention.
The MCAN within the MC68HC05X16 is controlled using a block of 30 registers. This comprises
10 control registers, 10 Transmit buffer registers and 10 receive buffer registers. These registers
are memory mapped between $20 and $3D (see Figure 5-3).
Note: There is an offset of $20 between the MC68HC05X16 addresses and the MCAN
internal addresses, i.e. MCAN addresses $00 to $1D, as defined in the BOSCH CAN
specification, are mapped to MC68HC05X16 addresses $20 to $3D.
MCAN register blocks MCAN registers 5
$0020 MCAN Control register $0020
control registers Command register $0021
$0029 $0022
$002A 10 bytes Status register $0023
Interrupt register $0024
$0033 MCAN Acceptance code register $0025
$0034 transmit buffer Acceptance mask register $0026
Bus timing register 1 $0027
$003D 10 bytes Bus timing register 2 $0028
Output control register $0029
MCAN $002A
receive buffer Test register $002B
Identifier $002C
10 bytes $002D
RTR-bit, data length code $002E
Data segment byte 1 $002F
Data segment byte 2 $0030
Data segment byte 3 $0031
Data segment byte 4 $0032
Data segment byte 5 $0033
Data segment byte 6
Data segment byte 7 $0034
Data segment byte 8 $0035
$0036
Identifier $0037
RTR-bit, data length code $0038
$0039
Data segment byte 1 $003A
Data segment byte 2 $003B
Data segment byte 3 $003C
Data segment byte 4 $003D
Data segment byte 5
Data segment byte 6
Data segment byte 7
Data segment byte 8
Figure 5-3 MCAN module memory map
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5.3.1 MCAN control register (CCNTRL)
This register may be read or written to by the MCU; only the RR bit is affected by the MCAN.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset State
condition on reset
MCAN control (CCNTRL) $0020 MODE SPD External reset 0u - u uuu1
OIE EIE TIE RIE RR
RR bit set 0u - u uuu1
MODE -- Undefined mode
5 This bit must never be set by the CPU as this would result in the transmit and receive buffers being
mapped out of memory. The bit is cleared on reset, and should be left in this state for normal
operation.
SPD -- Speed mode
1 (set) Slow Bus line transitions from both `recessive' to `dominant' and
from `dominant' to `recessive' will be used for resynchronization.
0 (clear) Fast Only transitions from `recessive' to `dominant' will be used for
resynchronization.
OIE -- Overrun interrupt enable
1 (set) Enabled The CPU will get an interrupt request whenever the
Overrun Status bit gets set.
0 (clear) Disabled The CPU will get no overrun interrupt request.
EIE -- Error interrupt enable
1 (set) Enabled The CPU will get an interrupt request whenever the error
status or bus status bits in the CSTAT register change.
0 (clear) Disabled The CPU will get no error interrupt request.
TIE -- Transmit interrupt enable
1 (set) Enabled The CPU will get an interrupt request whenever a
message has been successfully transmitted, or when the transmit
buffer is accessible again following an ABORT command.
0 (clear) Disabled The CPU will get no transmit interrupt request.
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RIE -- Receive interrupt enable
1 (set) Enabled The CPU will get an interrupt request whenever a
message has been received free of errors.
0 (clear) Disabled The CPU will get no receive interrupt request.
RR -- Reset request
When the MCAN detects that RR has been set it aborts the current transmission or reception of a
message and enters the reset state. A reset request may be generated by either an external reset
or by the CPU or by the MCAN. The RR bit can be cleared only by the CPU. After the RR bit has
been cleared, the MCAN will start normal operation in one of two ways. If RR was generated by
an external reset or by the CPU, then the MCAN starts normal operation after the first occurrence 5
of 11 recessive bits. If, however, the RR was generated by the MCAN due to the BS bit being set
(see Section 5.3.3) the MCAN waits for 128 occurrences of 11 recessive bits before starting
normal operation.
A reset request should not be generated by the CPU during a message transmission. Ensure that
a message is not being transmitted as follows:
if TCS in CSTAT is clear set AT in CCOM (use STA or STX), read CSTAT.
if TS in CSTAT is set wait until TS is clear.
Note that a CPU-generated reset request does not change the values in the transmit and receive
error counters.
1 (set) Present MCAN will be reset.
0 (clear) Absent MCAN will operate normally.
Note: The following registers may only be accessed when reset request = present: CACC,
CACM, CBT0, CBT1, and COCNTRL.
5.3.2 MCAN command register (CCOM)
This is a write only register; a read of this location will always return the value $FF.
This register may be written only when the RR bit in CCNTRL is clear.
Do not use read-modify-write instructions on this register (e.g. BSET, BCLR).
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset State
condition on reset
MCAN command (CCOM) $0020 RX0 RX1 COMPSEL SLEEP COS RRB AT External reset 00u0 0000
TR
RR bit set 00u0 0000
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RX0 -- Receive pin 0 (passive) (Refer to Figure 5-6)
1 (set) VDD/2 will be connected to the input comparator. The RX0 pin is
disconnected.
0 (clear) The RX0 pin will be connected to the input comparator. VDD/2 is
disconnected.
RX1 -- Receive pin 1 (passive) (Refer to Figure 5-6)
1 (set) VDD/2 will be connected to the input comparator. The RX1 pin is
disconnected.
5 0 (clear) The RX1 pin will be connected to the input comparator. VDD/2 is
disconnected.
Note: If both RX0 and RX1 are set, or both are clear, then neither of the RX pins will be
disconnected.
COMPSEL -- Comparator selector
1 (set) RX0 and RX1 will be compared with VDD/2 during sleep mode (see
Figure 5-6).
0 (clear) RX0 will be compared with RX1 during sleep mode.
SLEEP -- Go to sleep
1 (set) Sleep The MCAN will go into sleep mode, as long as there are no
interrupts pending and there is no activity on the bus. Otherwise the
MCAN will issue a wake-up interrupt.
0 (clear) Wake-up The MCAN will function normally. If SLEEP is cleared by
the CPU then the MCAN will waken up, but will not issue a wake-up
interrupt.
Note: If SLEEP is set during the reception or transmission of a message, the MCAN will
generate an immediate wake-up interrupt. (This allows for a more orthogonal software
implementation on the CPU.) This will have no effect on the transfer layer, i.e. no
message will be lost or corrupted.
The CAF flag in the EEPROM control register indicates whether or not sleep mode was
entered successfully.
A node that was sleeping and has been awakened by bus activity will not be able to
receive any messages until its oscillator has started and it has found a valid end of
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frame sequence (11 recessive bits). The designer must take this into consideration
when planning to use the sleep command.
COS -- Clear overrun status
1 (set) This clears the read-only data overrun status bit in the CSTAT register
(see Section 5.3.3). It may be written at the same time as RRB.
0 (clear) No action.
RRB -- Release receive buffer
When set this releases the receive buffer currently attached to the CPU, allowing the buffer to be 5
reused by the MCAN. This may result in another message being received, which could cause
another receive interrupt request (if RIE is set). This bit is cleared automatically when a message
is received, i.e. when the RS bit (see Section 5.3.3) becomes set.
1 (set) Released receive buffer is available to the MCAN.
0 (clear) No action.
AT -- Abort transmission
When this bit is set a pending transmission will be cancelled if it is not already in progress, allowing
the transmit buffer to be loaded with a new (higher priority) message when the buffer is released.
If the CPU tries to write to the buffer when it is locked, the information will be lost without being
signalled. The status register can be checked to see if transmission was aborted or is still in
progress.
1 (set) Present Abort transmission of any pending messages.
0 (clear) No action.
TR -- Transmission request
1 (set) Present Depending on the transmission buffer's content, a data
frame or a remote frame will be transmitted.
0 (clear) No action. This will not cancel a previously requested transmission;
the abort transmission command must be used to do this.
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5.3.3 MCAN status register (CSTAT)
This is a read only register; only the MCAN can change its contents.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset condition State
on reset
MCAN status External reset 0000 1100
(CSTAT) $0022 BS ES TS RS TCS TBA DO RBS
RR bit set uu00 1100
BS -- Bus status
5 This bit is set (off-bus) by the MCAN when the transmit error counter reaches 256. The MCAN will
then set RR and will remain off-bus until the CPU clears RR again. At this point the MCAN will wait
for 128 successive occurrences of a sequence of 11 recessive bits before clearing BS and
resetting the read and write error counters. While off-bus the MCAN does not take part in bus
activities.
1 (set) Off-bus The MCAN is not participating in bus activities.
0 (clear) On-bus The MCAN is operating normally.
ES -- Error status
1 (set) Error Either the read or the write error counter has reached the
CPU warning limit of 96.
0 (clear) Neither of the error counters has reached 96.
TS -- Transmit status
1 (set) Transmit The MCAN has started to transmit a message.
0 (clear) Idle If the receive status bit is also clear then the MCAN is idle;
otherwise it is in receive mode.
RS -- Receive status
1 (set) Receive The MCAN entered receive mode from idle, or by losing
arbitration during transmission.
0 (clear) Idle If the transmit status bit is also clear then the MCAN is idle;
otherwise it is in transmit mode.
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TCS -- Transmission complete status
This bit is cleared by the MCAN when TR becomes set. When TCS is set it indicates that the last
requested transmission was successfully completed. If, after TCS is cleared, but before
transmission begins, an abort transmission command is issued then the transmit buffer will be
released and TCS will remain clear. TCS will then only be set after a further transmission is both
requested and successfully completed.
1 (set) Complete Last requested transmission successfully completed.
0 (clear) Incomplete Last requested transmission not complete.
TBA -- Transmit buffer access
When clear, the transmit buffer is locked and cannot be accessed by the CPU. This indicates that 5
either a message is being transmitted, or is awaiting transmission. If the CPU writes to the transmit
buffer while it is locked, then the bytes will be lost without this being signalled.
1 (set) Released The transmit buffer may be written to by the CPU.
0 (clear) Locked The CPU cannot access the transmit buffer.
DO -- Data overrun
This bit is set when both receive buffers are full and there is a further message to be stored. In this
case the new message is dropped, but the internal logic maintains the correct protocol. The MCAN
does not receive the message, but no warning is sent to the transmitting node. The MCAN clears
DO when the CPU sets the COS bit in the CCOM register.
Note that data overrun can also be caused by a transmission, since the MCAN will temporarily
store an outgoing frame in a receive buffer in case arbitration is lost during transmission.
1 (set) Overrun Both receive buffers were full and there was another
message to be stored.
0 (clear) Normal operation.
RBS -- Receive buffer status
This bit is set by the MCAN when a new message is available. When clear this indicates that no
message has become available since the last RRB command. The bit is cleared when RRB is set.
However, if the second receive buffer already contains a message, then control of that buffer is
given to the CPU and RBS is immediately set again. The first receive buffer is then available for
the next incoming message from the MCAN.
1 (set) Full A new message is available for the CPU to read.
0 (clear) Empty No new message is available.
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5.3.4 MCAN interrupt register (CINT)
All bits of this register are read only; all are cleared by a read of the register.
This register must be read in the interrupt handling routine in order to enable further interrupts.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset condition State
on reset
MCAN interrupt $0023 External reset - - - 0 0000
WIF OIF EIF TIF RIF
(CINT)
RR bit set - - - u 0u00
5 WIF -- Wake-up interrupt flag
If the MCAN detects bus activity whilst it is asleep, it clears the SLEEP bit in the CCOM register;
the WIF bit will then be set. WIF is cleared by reading the MCAN interrupt register (CINT), or by
an external reset.
1 (set) MCAN has detected activity on the bus and requested wake-up.
0 (clear) No wake-up interrupt has occurred.
OIF -- Overrun interrupt flag
When OIE is set then this bit will be set when a data overrun condition is detected. Like all the bits
in this register, OIF is cleared by reading the register, or when reset request is set.
1 (set) A data overrun has been detected.
0 (clear) No data overrun has occurred.
EIF -- Error interrupt flag
When EIE is set then this bit will be set by a change in the error or bus status bits in the MCAN
status register. Like all the bits in this register, EIF is cleared by reading the register, or by an
external reset.
1 (set) There has been a change in the error or bus status bits in CSTAT.
0 (clear) No error interrupt has occurred.
TIF -- Transmit interrupt flag
The TIF bit is set at the end of a transmission whenever both the TBA and TIE bits are set. Like all
the bits in this register, TIF is cleared by reading the register, or when reset request is set.
1 (set) Transmission complete, the transmit buffer is accessible.
0 (clear) No transmit interrupt has occurred.
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RIF -- Receive interrupt flag
The RIF bit is set by the MCAN when a new message is available in the receive buffer, and the RIE
bit in CCNTRL is set. At the same time RBS is set. Like all the bits in this register, RIF is cleared
by reading the register, or when reset request is set.
1 (set) A new message is available in the receive buffer.
0 (clear) No receive interrupt has occurred.
5.3.5 MCAN acceptance code register (CACC)
On reception each message is written into the current receive buffer. The MCU is only signalled to 5
read the message however, if it passes the criteria in the acceptance code and acceptance mask
registers (accepted); otherwise, the message will be overwritten by the next message (dropped).
Note: This register can only be accessed when the reset request bit in the CCNTRL register
is set.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
MCAN acceptance code (CACC) $0024 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Undefined
AC7 AC0 -- Acceptance code bits
AC7 AC0 comprise a user defined sequence of bits with which the 8 most significant bits of the
data identifier (ID10 ID3) are compared. The result of this comparison is then masked with the
acceptance mask register. Once a message has passed the acceptance criterion the respective
identifier, data length code and data are sequentially stored in a receive buffer, providing there is
one free. If there is no free buffer, the data overrun condition will be signalled.
On acceptance the receive buffer status bit is set to full and the receive interrupt bit is set (provided
RIE = enabled).
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5.3.6 MCAN acceptance mask register (CACM)
The acceptance mask register specifies which of the corresponding bits in the acceptance code
register are relevant for acceptance filtering.
Note: This register can only be accessed when the reset request bit in the CCNTRL register
is set.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
5 MCAN acceptance mask (CACM) $0025 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Undefined
AM0 AM7 -- Acceptance mask bits
When a particular bit in this register is clear this indicates that the corresponding bit in the
acceptance code register must be the same as its identifier bit, before a match will be detected.
The message will be accepted if all such bits match. When a bit is set, it indicates that the state of
the corresponding bit in the acceptance code register will not affect whether or not the message
is accepted.
1 (set) Ignore corresponding acceptance code register bit.
0 (clear) Match corresponding acceptance code register and identifier bits.
5.3.7 MCAN bus timing register 0 (CBT0)
Note: This register can only be accessed when the reset request bit in the CCNTRL register
is set.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
MCAN bus timing 0 (CBT0) $0026 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Undefined
SJW1, SJW0 -- Synchronization jump width bits
The synchronization jump width defines the maximum number of system clock (tSCL) cycles by
which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on
the bus (see Table 5-1).
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Table 5-1 Synchronization jump width
SJW1 SJW0 Synchronization jump width
0 0
0 1 1 tSCL cycle
1 0 2 tSCL cycles
1 1 3 tSCL cycles
4 tSCL cycles
BRP5 BRP0 -- Baud rate prescaler bits
These bits determine the MCAN system clock cycle time (tSCL), which is used to build up the
individual bit timing, according to Table 5-2 and the formula in Figure 5-4. 5
Table 5-2 Baud rate prescaler
BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P)
0 0 0 0 0 0 1
0 0 0 0 0 1 2
0 0 0 0 1 0 3
0 0 0 0 1 1 4
: : : : : : :
: : : : : : :
1 1 1 1 1 1 64
fosc Divide by fosc/2
OSC1 2
Prescaler (P) 2P
tSCL = fosc
MCAN module system clock
Divide by fOP
10, 8, 4 or 2
MCU bus clock
Figure 5-4 Oscillator block diagram
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5.3.8 MCAN bus timing register 1 (CBT1)
This register can only be accessed when the reset request bit in the CCNTRL register is set.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
MCAN bus timing 1 (CBT1) $0027 SAMP TSEG22TSEG21TSEG20TSEG13TSEG12TSEG11TSEG10 Undefined
SAMP -- Sampling
This bit determines the number of samples of the serial bus to be taken per bit time. When set three
5 samples per bit are taken. This sample rate gives better rejection of noise on the bus, but
introduces a one bit delay to the bus sampling. For higher bit rates SAMP should be cleared, which
means that only one sample will be taken per bit.
1 (set) Three samples per bit.
0 (clear) One sample per bit.
TSEG22 TSEG10 -- Time segment bits
Time segments within the bit time fix the number of clock cycles per bit time, and the location of
the sample point.
SYNC_SEG BIT_TIME TSEG 2 SYNC_SEG
TSEG 1
Transmit point 1 clock cycle Sample point Transmit point
tSCL
Figure 5-5 Segments within the bit time
SYNC_SEG System expects transitions to occur on the bus during this period.
Transmit point A node in transmit mode will transfer a new value to the MCAN bus at this point.
Sample point A node in receive mode will sample the bus at this point. If the three samples per
bit option is selected then this point marks the position of the third sample.
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in Table 5-3.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of
bus clock cycles (tSCL) per bit (as shown above).
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Table 5-3 Time segment values
TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 TSEG22 TSEG21 TSEG20 Time segment 2
0 0 0 1 2 tSCL cycles 0 0 1 2 tSCL cycles
0 0 1 0 3 tSCL cycles . . . .
0 0 1 1 4 tSCL cycles . . . .
. . . . . 1 1 1 8 tSCL cycles
. . . . .
1 1 1 1 16 tSCL cycles
Calculation of the bit time
BIT_TIME = SYNC_SEG + TSEG1 + TSEG2 5
Note: TSEG2 must be at least 2 tSCL, i.e. the configuration bits must not be 000. (If three
samples per bit mode is selected then TSEG2 must be at least 3 tSCL.)
TSEG1 must be at least as long as TSEG2.
The synchronization jump width (SJW) may not exceed TSEG2, and must be at least
tSCL shorter than TSEG1 to allow for physical propagation delays.
i.e. in terms of tSCL: SYNC_SEG = 1
and TSEG1 SJW + 1
or
TSEG1 TSEG2
TSEG2 SJW
TSEG2 2 (SAMP = 0)
TSEG2 3 (SAMP = 1)
These boundary conditions result in minimum bit times of 5 tSCL, for one sample, and 7 tSCL, for
three samples per bit.
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5.3.9 MCAN output control register (COCNTRL)
This register allows the setup of different output driver configurations under software control. The
user may select active pull-up, pull-down, float or push-pull output.
Note: This register can only be accessed when the reset request bit in the CCNTRL register
is set.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
5 MCAN output control (COCNTRL) $0028 OCTP1 OCTN1 OCPOL1 OCTP0 OCTN0 OCPOL0 OCM1 OCM0 Undefined
OCM1 and OCM0 -- Output control mode bits
The values of these two bits determine the output mode, as shown in Table 5-4.
Table 5-4 Output control modes
OCM1 OCM0 Function
0 0 Biphase mode
0 1 Not used
1 0 Normal mode 1
Bit stream transmitted on both TX0 and TX1
1 1 Normal mode 2
TX0 - bit sequence
TX1 - bus clock (txclk)
Note: The transmit clock (txclk) is used to indicate the end of the bit time and will be high during
the SYNC_SEG.
For all the following modes of operation, a dominant bit is internally coded as a zero, a
recessive as a one. The other output control bits are used to determine the actual
voltage levels transmitted to the MCAN bus for dominant and recessive bits.
Biphase mode
If the CAN modules are isolated from the bus lines by a transformer then the bit stream has to be
coded so that there is no resulting dc component. There is a flip-flop within the MCAN that keeps
the last dominant configuration; its direct output goes to TX0 and its complement to TX1. The
flip-flop is toggled for each dominant bit; dominant bits are thus sent alternately on TX0 and TX1;
i.e. the first dominant bit is sent on TX0, the second on TX1, the third on TX0 and so on. During
recessive bits, all output drivers are deactivated (i.e. high impedance).
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Normal mode 1
In contrast to biphase mode the bit representation is time invariant and not toggled.
Normal mode 2
For the TX0 pin this is the same as normal mode 1, however the data stream to TX1 is replaced
by the transmit clock. The rising edge of the transmit clock marks the beginning of a bit time. The
clock pulse will be tSCL long.
Other output control bits
The other six bits in this register control the output driver configurations, to determine the format
of the output signal for a given data value (see Figure 5-6). 5
OCTP0/1 These two bits control whether the P-type output control transistors are enabled.
OCTN0/1 These two bits control whether the N-type output control transistors are enabled.
OCPOL0/1 These two bits determine the driver output polarity for each of the MCAN bus lines
(TX0, TX1).
TP0/1 and TN0/1 These are the resulting states of the output transistors.
TD This is the internal value of the data bit to be transferred across the MCAN bus. (A zero
corresponds to a dominant bit, a one to a recessive.)
The actions of these bits in the output control register are as shown in Table 5-5.
Table 5-5 MCAN driver output levels
Mode TD OCPOLi OCTPi OCTNi TPi TNi TXi output level
Float Float
Pull-down 0 0 0 0 Off Off Float
Pull-up Float
Push-pull 1 0 0 0 Off Off Float
Low
0 1 0 0 Off Off Float
Float
1 1 0 0 Off Off Low
Float
0 0 0 1 Off On High
High
1 0 0 1 Off Off Float
Low
0 1 0 1 Off Off High
High
1 1 0 1 Off On Low
0 0 1 0 Off Off
1 0 1 0 On Off
0 1 1 0 On Off
1 1 1 0 Off Off
0 0 1 1 Off On
1 0 1 1 On Off
0 1 1 1 On Off
1 1 1 1 Off On
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5.3.10 Transmit buffer identifier register (TBI)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Transmit buffer identifier (TBI) $002A ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 Undefined
ID10 ID3 -- Identifier bits
The identifier consists of 11 bits (ID10 ID0). ID10 is the most significant bit and is transmitted first
on the bus during the arbitration procedure. The priority of an identifier is defined to be highest for
the smallest binary number. The three least significant bits are contained in the TRTDL register.
5 The seven most significant bits must not all be recessive.
5.3.11 Remote transmission request and data length code
register (TRTDL)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
RTR and data length code (TRTDL) $002B ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 DLC0 Undefined
ID2 ID0 -- Identifier bits
These bits contain the least significant bits of the transmit buffer identifier.
RTR -- Remote transmission request
1 (set) A remote frame will be transmitted.
0 (clear) A data frame will be transmitted.
DLC3 DLC0 -- Data length code bits.
The data length code contains the number of bytes (data byte count) of the respective message.
At transmission of a remote frame, the data length code is ignored, forcing the number of bytes to
be 0. The data byte count ranges from 0 to 8 for a data frame. Table 5-6 shows the effect of setting
the DLC bits.
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Table 5-6 Data length codes
Data length code Data byte
count
DLC3 DLC2 DLC1 DLC0
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7 5
1 0 0 0 8
5.3.12 Transmit data segment registers (TDS) 1 8
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Transmit data segment (TDS) $002C DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
$0033
DB7 DB0 -- data bits
These data bits in the eight data segment registers make up the bytes of data to be transmitted.
The number of bytes to be transmitted is determined by the data length code.
5.3.13 Receive buffer identifier register (RBI)
The layout of this register is identical to the TBI register (see Section 5.3.10).
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Receive buffer identifier (RBI) $0034 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 Undefined
(Note that there are actually two receive buffer register sets, but switching between them is
handled internally by the MCAN.)
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5.3.14 Remote transmission request and data length code
register (RRTDL)
The layout of this register is identical to the TRTDL register (see Section 5.3.11).
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
RTR and data length code (RRTDL) $0035 ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 DLC0 Undefined
5.3.15 Receive data segment registers (RDS) 1 8
5
The layout of these registers is identical to the TDSx registers (see Section 5.3.12).
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Receive data segment (RDS) $0036 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Undefined
$003D
(Note that there are actually two receive buffer register sets, but switching between them is
handled internally by the MCAN.)
5.4 Interface to the MCAN bus
Physically, the MCAN bus may be composed of two wires. The bus can take on one of two values:
dominant or recessive. During simultaneous transmission of dominant and recessive bits by two
or more CAN modules the resulting bus value will be dominant. (For example, with a wired-AND
implementation of the bus, the dominant level would correspond to a logic 0, and the recessive
level to a logic 1.)
The two wires of the MCAN bus are designated CANH and CANL. The voltage levels appearing
on these lines are designated VCANH and VCANL. A simple termination network is required for each
wire. Figure 5-6 shows the physical interface circuitry within the MCAN module, and its connection
to the MCAN bus with a typical low speed (<125 kbaud) hardware interface. (Note that the
suggested values shown in the diagram are subject to change in the future.)
For the voltage and resistor values shown in Figure 5-6 the voltages on the MCAN bus are:
Recessive level: VCANH = 3.25 V VCANL = 1.75 V
Dominant level: VCANH = 1.00 V VCANL = 4.00 V
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Termination TXP0
network TXN0
1.75V 3.25V
2 k 2 k
680 TX0
680 TX1 5
TXP1
TXN1
150k RX0 passive
RX0
+ Data
AC
150k RX1 passive
RX1
2 x 30k + COMPSEL
SC Wake-up
&
+
SC
CANL + VDD/2
CANH SC
VDDH
MCAN bus lines
Internal to the MC68HC05X16 MCAN module
Figure 5-6 A typical physical interface between the MCAN and the MCAN bus lines
MC68HC05X16 MOTOROLA CAN MODULE (MCAN) MOTOROLA
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If several CAN modules are driving a dominant level on the bus at the same time then the values
for VCANH and VCANL can go to 0.3 and 4.7 volts respectively. The residual 0.3 V is due to the
voltage drop across the diodes and driver transistors in the transmission circuit.
The receiver part of the network uses two identical voltage divider networks, with a divide ratio of
6:1 (resistor values of 150k and 30k) referenced to VDD/2. This increases the common mode
range of the input comparator on the physical bus lines. If the common mode range of the
comparator at its inputs is 1.5 to 3.5 volts then, for VDD = 5.0 V, the common mode range will be
increased to 3.5 to +8.5 volts on the bus lines.
5.4.1 Single wire operation
5 In the event of a bus fault occurring, limited operation of the MCAN bus may still be possible,
depending on the nature of the fault. If the fault is due to a short circuit between the two bus lines
or between one of the lines and ground, battery voltage or some other potential, it is possible to
identify (using a special software procedure) the line on which the fault exists and to switch the
corresponding comparator input from the faulty line to the VDD/2 reference supply. At the same
time the driver transistors to the faulty line should also be switched off. This will allow
communication to continue on the bus. One result of this mode of one wire transmission is a
significant reduction in the common mode range of the input comparator.
Switching to one wire operation is achieved using the control bits RX0-passive and RX1-passive
in the MCAN command register, located at address $21. Setting either of these bits will result in
the corresponding input being disconnected from the bus and connected to VDD/2.
5.5 Sleep mode
If the SLEEP bit in the MCAN command register is set by the processor the MCAN will go to sleep,
unless it is active. If there is activity on the MCAN bus lines, or there is an interrupt pending, the
MCAN is deemed to be active and will not go to sleep; a wake-up interrupt will be generated by
the MCAN in these circumstances. The SLEEP bit may also be cleared by the processor, in which
case no wake-up interrupt will be generated. Note that this bit is write-only by the CPU, and it is
not possible therefore to check whether sleep mode has been entered by reading it. However, the
CAF bit in the EEPROM control register is set when the MCAN is asleep, and cleared when it is
woken up (see Section 3.5.1).
In order to minimize power consumption, the active comparator is switched off and the sleep
comparator circuitry is used to detect activity on the bus. When in sleep mode the MCAN stops its
own clocks, leaving the MCU in normal run mode. (Similarly a STOP instruction will stop the
processor clocks, leaving the MCAN in run mode.) The on-chip oscillator will stop only if the MCAN
is in sleep mode and the MCU executes a STOP instruction. There is a time delay between the
STOP instruction being executed and the oscillator stopping. During this time it is possible that the
MCAN will come out of sleep mode, and hence prevent the oscillator from stopping.
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When a dominant level is detected on the MCAN bus, the MCAN is woken up and a wake-up
interrupt is generated.
Under normal operation the two MCAN bus lines are forced to complementary logic levels. The
level of one of the two wires can be disregarded and replaced by VDD/2 by setting one of the control
bits, RX0 or RX1.
5.5.1 Sleep comparator reference
When the COMPSEL bit in the MCAN command register ($21) is cleared the sleep comparator
inputs are the same as for the active comparator. However, when the COMPSEL bit is set each
input is compared with VDD/2 (VDDH see Figure 5-6) to detect a dominant level. For further 5
details of the active comparator, the sleep comparator and VDDH, refer to Section 12.
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5
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6
PROGRAMMABLE TIMER
The programmable timer on the MC68HC05X32 consists of a 16-bit read-only free-running
counter, with a fixed divide-by-four prescaler, plus the input capture/output compare circuitry. The
timer can be used for many purposes including measuring pulse length of two input signals and
generating two output signals. Pulse lengths for both input and output signals can vary from
several microseconds to many seconds. In addition, it works in conjunction with the pulse width 6
modulation (PWM) system to execute two 8-bit D/A PLM (pulse length modulation) conversions,
with a choice of two repetition rates. The timer is also capable of generating periodic interrupts or
indicating passage of an arbitrary multiple of four CPU cycles. A block diagram is shown in
Figure 6-1, and timing diagrams are shown in Figure 6-2, Figure 6-3, Figure 6-4 and Figure 6-5.
The timer has a 16-bit architecture, hence each specific functional segment is represented by two
8-bit registers (except the PLMA and PLMB which use one 8-bit register for each). These registers
contain the high and low byte of that functional segment. Accessing the low byte of a specific timer
function allows full control of that function; however, an access of the high byte inhibits that specific
timer function until the low byte is also accessed.
The 16-bit programmable timer is monitored and controlled by a group of sixteen registers, full
details of which are contained in this section.
Note: A problem may arise if an interrupt occurs in the time between the high and low bytes
being accessed. To prevent this, the I-bit in the condition code register (CCR) should be
set while manipulating both the high and low byte register of a specific timer function,
ensuring that an interrupt does not occur.
6.1 Counter
The key element in the programmable timer is a 16-bit, free-running counter or counter register,
preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the
timer a resolution of 2s if the internal bus clock is 2 MHz. The counter is incremented during the
low portion of the internal bus clock. Software can read the counter at any time without affecting
its value.
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Internal bus
8
Internal 8-bit
processor buffer
clock
High Low High Low High Low High Low High Low
byte byte byte byte byte byte byte byte byte byte
Output $0016 Output $001E 4 16-bit $0018 Input capture $0014 Input capture $001C
compare $0017 compare $001F free-running $0019 register 1 $0015 register 2 $001D
register 1 register 2
counter
COP watchdog Counter $001A
counter input alternate $001B
register
To PLM Internal timer bus
6 Output Output Overflow Edge Edge TCAP2
compare compare detect detect detect pin
circuit 1 circuit 2
circuit 1 circuit 2 circuit
TCAP1
pin
DQ TCMP2
pin
+ C Latch
DQ TCMP1
pin
7 6 5 4 3 Timer status + C Latch
ICF1 OCF1 TOF ICF2 OCF2 register
$0013 Timer control
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1 register
$0012
Interrupt circuit
Input capture Output compare Overflow interrupt
interrupt vector interrupt vector vector
$3FF4,5
$3FF8,9 $3FF6,7
Figure 6-1 16-bit programmable timer block diagram
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6.1.1 Counter register and alternate counter register
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Timer counter high $0018 1111 1111
Timer counter low
$0019 1111 1100
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Alternate counter high $001A 1111 1111
Alternate counter low
$001B 1111 1100
The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter
register) or $1A-$1B (alternate counter register). A read from only the less significant byte (LSB)
of the free-running counter ($19 or $1B) receives the count value at the time of the read. If a read 6
of the free-running counter or alternate counter register first addresses the more significant byte
(MSB) ($18 or $1A), the LSB is transferred to a buffer. This buffer value remains fixed after the first
MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the
free-running counter or alternate counter register LSB and thus completes a read sequence of the
total counter value. In reading either the free-running counter or alternate counter register, if the
MSB is read, the LSB must also be read to complete the sequence. If the timer overflow flag (TOF)
is set when the counter register LSB is read then a read of the timer status register (TSR) will clear
the flag.
The alternate counter register differs from the counter register only in that a read of the LSB does
not clear TOF. Therefore, where it is critical to avoid the possibility of missing timer overflow
interrupts due to clearing of TOF, the alternate counter register should be used.
The free-running counter is set to $FFFC during power-on and external reset and is always a
read-only register. During a power-on reset, the counter begins running after the oscillator start-up
delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-4 prescaler, the
value in the free-running counter repeats every 262,144 internal bus clock cycles. TOF is set when
the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE is set.
In some particular timing control applications it may be desirable to reset the 16-bit free running
counter under software control. When the low byte of the counter ($19 or $1B) is written to, the
counter is configured to its reset value ($FFFC).
The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of
the flags and enable bits remain unaltered by this operation. If access has previously been made
to the high byte of the free-running counter ($18 or $1A), then the reset counter operation
terminates the access sequence.
Warning: This operation may affect the function of the watchdog system (see Section 10.1.4).
The PLM results will also be affected while resetting the counter.
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6.2 Timer control and status
The various functions of the timer are monitored and controlled using the timer control and status
registers described below.
6.2.1 Timer control register (TCR)
The timer control register ($0012) is used to enable the input captures (ICIE), output compares
(OCIE), and timer overflow (TOIE) functions as well as forcing output compares (FOLV1 and
FOLV2), selecting input edge sensitivity (IEDG1) and levels of output polarity (OLV1 and OLV2).
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
6 Timer control (TCR) $0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLV1 0000 00u0
ICIE -- Input captures interrupt enable
If this bit is set, a timer interrupt is enabled whenever the ICF1 or ICF2 status flag (in the timer
status register) is set.
1 (set) Interrupt enabled.
0 (clear) Interrupt disabled.
OCIE -- Output compares interrupt enable
If this bit is set, a timer interrupt is enabled whenever the OCF1 or OCF2 status flag (in the timer
status register) is set.
1 (set) Interrupt enabled.
0 (clear) Interrupt disabled.
TOIE -- Timer overflow interrupt enable
If this bit is set, a timer interrupt is enabled whenever the TOF status flag (in the timer status
register) is set.
1 (set) Interrupt enabled.
0 (clear) Interrupt disabled.
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FOLV2 -- Force output compare 2
This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this position
will force the OLV2 bit to the corresponding output level latch, thus appearing at the TCMP2 pin. Note
that this bit does not affect the OCF2 bit of the status register (see Section 6.4.3).
1 (set) OLV2 bit forced to output level latch.
0 (clear) No effect.
FOLV1 -- Force output compare 1
This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this position
will force the OLV1 bit to the corresponding output level latch, thus appearing at the TCMP1 pin. Note
that this bit does not affect the OCF1 bit of the status register (see Section 6.4.3).
1 (set) OLV1 bit forced to output level latch.
0 (clear) No effect. 6
OLV2 -- Output level 2
When OLV2 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level
which will appear on the TCMP2 pin.
1 (set) A high output level will appear on the TCMP2 pin.
0 (clear) A low output level will appear on the TCMP2 pin.
IEDG1 -- Input edge 1
When IEDG1 is set, a positive-going edge on the TCAP1 pin will trigger a transfer of the
free-running counter value to the input capture register 1. When clear, a negative-going edge
triggers the transfer.
1 (set) TCAP1 is positive-going edge sensitive.
0 (clear) TCAP1 is negative-going edge sensitive.
Note: There is no need for an equivalent bit for the input capture register 2 as TCAP2 is
negative-going edge sensitive only.
OLV1 -- Output level 1
When OLV1 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level
which will appear on the TCMP1 pin.
1 (set) A high output level will appear on the TCMP1 pin.
0 (clear) A low output level will appear on the TCMP1 pin.
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6.2.2 Timer status register (TSR)
The timer status register ($13) contains the status bits corresponding to the timer interrupt
conditions ICF1, OCF1, TOF, ICF2 and OCF2.
Accessing the timer status register satisfies the first condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Timer status (TSR) $0013 ICF1 OCF1 TOF ICF2 OCF2 Undefined
ICF1 -- Input capture flag 1
This bit is set when the selected polarity of edge is detected by the input capture edge detector 1
at TCAP1; an input capture interrupt will be generated, if ICIE is set. ICF1 is cleared by reading
6 the TSR and then the input capture low register 1 ($15).
1 (set) A valid input capture has occurred.
0 (clear) No input capture has occurred.
OCF1 -- Output compare flag 1
This bit is set when the output compare 1 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF1 is cleared by reading
the TSR and then the output compare 1 low register ($17).
1 (set) A valid output compare has occurred.
0 (clear) No output compare has occurred.
TOF -- Timer overflow status flag
This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow interrupt
will occur if TOIE is set. TOF is cleared by reading the TSR and the counter low register ($19).
1 (set) Timer overflow has occurred.
0 (clear) No timer overflow has occurred.
When using the timer overflow function and reading the free-running counter at random times to
measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally
cleared if:
1 The timer status register is read or written when TOF is set, and
2 The LSB of the free-running counter is read, but not for the purpose of
servicing the flag.
Reading the alternate counter register instead of the counter register will avoid this potential
problem.
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ICF2 -- Input capture flag 2
This bit is set when a negative edge is detected by the input capture edge detector 2 at TCAP2;
an input capture interrupt will be generated if ICIE is set. ICF2 is cleared by reading the TSR and
then the input capture low register 2 ($1D).
1 (set) A valid (negative) input capture has occurred.
0 (clear) No input capture has occurred.
OCF2 -- Output compare flag 2
This bit is set when the output compare 2 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF2 is cleared by reading
the TSR and then the output compare 2 low register ($1F).
1 (set) A valid output compare has occurred.
0 (clear) No output compare has occurred. 6
6.3 Input capture
`Input capture' is a technique whereby an external signal is used to trigger a read of the free
running counter. In this way it is possible to relate the timing of an external signal to the internal
counter value, and hence to elapsed time.
There are two input capture registers: input capture register 1 (ICR1) and input capture register 2 (ICR2).
The same input capture interrupt enable bit (ICIE) is used for the two input captures.
6.3.1 Input capture register 1 (ICR1)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Input capture high 1 $0014 Undefined
Input capture low 1
$0015 Undefined
The two 8-bit registers that make up the 16-bit input capture register 1 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit 1 senses
a valid transition at TCAP1. The level transition that triggers the counter transfer is defined by the
input edge bit (IEDG1). When an input capture 1 occurs, the corresponding flag ICF1 in TSR is set.
An interrupt can also accompany an input capture 1 provided the ICIE bit in TCR is set. The 8 most
significant bits are stored in the input capture high 1 register at $14, the 8 least significant bits in
the input capture low 1 register at $15.
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The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register 1 on each valid signal transition whether the input capture 1 flag (ICF1) is set or
clear. The input capture register 1 always contains the free-running counter value that corresponds
to the most recent input capture 1. After a read of the input capture 1 register MSB ($14), the
counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes the time
used in the input capture software routine and its interaction with the main program to determine
the minimum pulse period. A read of the input capture 1 register LSB ($15) does not inhibit the
free-running counter transfer since the two actions occur on opposite edges of the internal bus
clock.
Reset does not affect the contents of the input capture 1 register, except when exiting STOP mode
(see Section 6.6).
6 Input capture register 2 (ICR2)
6.3.2
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Input capture high 2 $001C Undefined
Input capture low 2
$001D Undefined
The two 8-bit registers that make up the 16-bit input capture register 2 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit 2 senses
a negative transition at pin TCAP2. When an input capture 2 occurs, the corresponding flag ICF2
in TSR is set. An interrupt can also accompany an input capture 2 provided the ICIE bit in TCR is
set.The 8 most significant bits are stored in the input capture 2 high register at $1C, the 8 least
significant bits in the input capture 2 low register at $1D.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register 2 on each negative signal transition whether the input capture 2 flag (IC2F) is set
or clear. The input capture register 2 always contains the free-running counter value that
corresponds to the most recent input capture 2. After a read of the input capture register 2 MSB
($1C), the counter transfer is inhibited until the LSB ($1D) is also read. This characteristic causes
the time used in the input capture software routine and its interaction with the main program to
determine the minimum pulse period. A read of the input capture register 2 LSB ($1C) does not
inhibit the free-running counter transfer since the two actions occur on opposite edges of the
internal bus clock.
Reset does not affect the contents of the input capture 2 register, except when exiting STOP mode
(see Section 6.6).
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6.4 Output compare
`Output compare' is a technique which may be used, for example, to generate an output waveform,
or to signal when a specific time period has elapsed, by presetting the output compare register to
the appropriate value.
There are two output compare registers: output compare register 1 (OCR1) and output compare
register 2 (OCR2).
Note: The same output compare interrupt enable bit (OCIE) is used for the two output
compares.
6.4.1 Output compare register 1 (OCR1)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State 6
on reset
Output compare high 1 $0016 Undefined
Output compare low 1 $0017 Undefined
The 16-bit output compare register 1 is made up of two 8-bit registers at locations $16 (MSB) and
$17 (LSB). The contents of the output compare register 1 are compared with the contents of the
free-running counter continually and, if a match is found, the corresponding output compare flag
(OCF1) in the timer status register is set and the output level (OLVL1) is transferred to pin TCMP1.
The output compare register 1 values and the output level bit should be changed after each
successful comparison to establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The
free-running counter is updated every four internal bus clock cycles.)
After a processor write cycle to the output compare register 1 containing the MSB ($16), the output
compare function is inhibited until the LSB ($17) is also written. The user must write both bytes
(locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare
1 function. The processor can write to either byte of the output compare register 1 without affecting
the other byte. The output level (OLVL1) bit is clocked to the output level register and hence to the
TCMP1 pin whether the output compare flag 1 (OCF1) is set or clear. The minimum time required
to update the output compare register 1 is a function of the program rather than the internal
hardware. Because the output compare flag 1 and the output compare register 1 are not defined
at power on, and not affected by reset, care must be taken when initializing output compare
functions with software. The following procedure is recommended:
Write to output compare high 1 to inhibit further compares;
Read the timer status register to clear OCF1 (if set);
Write to output compare low 1 to enable the output compare 1 function.
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The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
6.4.2 Output compare register 2 (OCR2)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Output compare high 2 $001E Undefined
Output compare low 2
$001F Undefined
6 The 16-bit output compare register 2 is made up of two 8-bit registers at locations $1E (MSB) and
$1F (LSB). The contents of the output compare register 2 are compared with the contents of the
free-running counter continually and, if a match is found, the corresponding output compare flag
(OCF2) in the timer status register is set and the output level (OLVL2) is transferred to pin TCMP2.
The output compare register 2 values and the output level bit should be changed after each
successful comparison to establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The
free-running counter is updated every four internal bus clock cycles.)
After a processor write cycle to the output compare register 2 containing the MSB ($1E), the output
compare function is inhibited until the LSB ($1F) is also written. The user must write both bytes
(locations) if the MSB is written first. A write made only to the LSB ($1F) will not inhibit the compare
2 function. The processor can write to either byte of the output compare register 2 without affecting
the other byte. The output level (OLVL2) bit is clocked to the output level register and hence to the
TCMP2 pin whether the output compare flag 2 (OCF2) is set or clear. The minimum time required
to update the output compare register 2 is a function of the program rather than the internal
hardware. Because the output compare flag 2 and the output compare register 2 are not defined
at power on, and not affected by reset, care must be taken when initializing output compare
functions with software. The following procedure is recommended:
Write to output compare high 2 to inhibit further compares;
Read the timer status register to clear OCF2 (if set);
Write to output compare low 2 to enable the output compare 2 function.
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The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
6.4.3 Software force compare
A software force compare is required in many applications. To achieve this, bit 3 (FOLV1 for OCR1)
and bit 4 (FOLV2 for OCR2) in the timer control register are used. These bits always read as `zero',
but a write to `one' causes the respective OLVL1 or OLVL2 values to be copied to the respective
output level (TCMP1 and TCMP2 pins).
Internal logic is arranged such that in a single instruction, one can change OLVL1 and/or OLVL2,
at the same time causing a forced output compare with the new values of OLVL1 and OLVL2. In 6
conjunction with normal compare, this function allows a wide range of applications including fixed
frequency generation.
Note: A software force compare will affect the corresponding output pin TCMP1 and/or
TCMP2, but will not affect the compare flag, thus it will not generate an interrupt.
6.5 Pulse length modulation (PLM)
The programmable timer works in conjunction with the PLM system to execute two 8-bit D/A PLM
conversions, with a choice of two repetition rates (see Section 8).
6.5.1 Pulse length modulation registers A and B (PLMA/PLMB)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Pulse length modulation A (PLMA) $000A 0000 0000
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Pulse length modulation B (PLMB) $000B 0000 0000
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6.6 Timer during STOP mode
When the MCU enters STOP mode, the timer counter stops counting and remains at that particular
count value until STOP mode is exited by an interrupt. If STOP mode is exited by power-on or
external reset, the counter is forced to $FFFC but if it is exited by external interrupt (IRQ) then the
counter resumes from its stopped value.
Another feature of the programmable timer is that if at least one valid input capture edge occurs at
one of the TCAP pins while in STOP mode, the corresponding input capture detect circuitry is
armed. This action does not wake the MCU or set any timer flags, but when the MCU does wake-up
there will be an active input capture flag (and data) from that first valid edge which occurred during
STOP mode.
If STOP mode is exited by an external reset then no such input capture flag or data action takes
place even if there was a valid input capture edge (at one of the TCAP pins) during STOP mode.
6 6.7 Timer during WAIT mode
The timer system is not affected by WAIT mode and continues normal operation. Any valid timer
interrupt will wake-up the system.
6.8 Timer state diagrams
The relationships between the internal clock signals, the counter contents and the status of the
flag bits are shown in the following figures. It should be noted that the signals labelled `internal'
(processor clock, timer clocks and reset) are not available to the user.
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Internal
processor clock
Internal
reset
T00
Internal T01
timer clocks
T10
T11
16-bit $FFFC $FFFD $FFFE $FFFF
counter
External reset
or end of POR
Note: The counter and timer control registers are the only ones affected by power-on or external reset. 6
Figure 6-2 Timer state timing diagram for reset
Internal
processor clock
T00
Internal T01
timer clocks
T10
T11
16-bit $F123 $F124 $F125 $F126
counter
Input }
edge }
}
Internal }
capture latch
Input capture $???? $F124
register
Input capture
flag
Note: If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then
the input capture flag will be set during the next T11 state.
Figure 6-3 Timer state timing diagram for input capture
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Internal
processor clock
T00
Internal T01
timer clocks
T10
T11
16-bit $F456 $F457 $F458 $F459
counter (Note 1) $F457
Output compare CPU writes $F457
register
Compare register (Note 1)
latch
6 Output compare (Note 2)
flag and TCMP1,2
Note: The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state
T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare.
Figure 6-4 Timer state timing diagram for output compare
Internal
processor clock
T00
Internal T01
timer clocks
T10
T11
16-bit $FFFF $0000 $0001 $0002
counter
Timer overflow
flag
Note: The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by
a read of the timer status register during the internal processor clock high time, followed by a read of the
counter low register.
Figure 6-5 Timer state timing diagram for timer overflow
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7
SERIAL COMMUNICATIONS INTERFACE
A full-duplex asynchronous serial communications interface (SCI) is provided with a standard
non-return-to-zero (NRZ) format and a variety of baud rates. The SCI transmitter and receiver are
functionally independent and have their own baud rate generator; however they share a common
baud rate prescaler and data format.
The serial data format is standard mark/space (NRZ) and provides one start bit, eight or nine data
bits, and one stop bit.
The SCLK pin is the output of the transmitter clock. It outputs the transmitter data clock for 7
synchronous transmission (no clocks on start bit and stop bit, and a software option to send clock
on last data bit). This allows control of peripherals containing shift registers (e.g. LCD drivers).
Phase and polarity of these clocks are software programmable.
Any SCI bidirectional communication requires a two-wire system: receive data in (RDI) and
transmit data out (TDO).
`Baud' and `bit rate' are used synonymously in the following description.
7.1 SCI two-wire system features
Standard NRZ (mark/space) format
Advanced error detection method with noise detection for noise duration of up to 1/16th bit time
Full-duplex operation (simultaneous transmit and receive)
32 software selectable baud rates
Different baud rates for transmit and receive; for each transmit baud rate, 8 possible receive
baud rates
Software selectable word length (eight or nine bits)
Separate transmitter and receiver enable bits
Capable of being interrupt driven
Transmitter clocks available without altering the regular transmitter or receiver functions
Four separate enable bits for interrupt control
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Internal bus SCI interrupt
+
$0011 Transmit
(See note) data register $0011 Receive
(See note) data register
& & & & $000F
SCCR2
TDO Transmit TIE 7 Receive RDI
pin data shift TCIE 6 data shift pin
register RIE 5 register
ILIE 4
TE 3
RE 2
SBK 1
+ RWU 0
SCSR
$0010
7 6 5 4 32 1
TRDE TC RDRF IDLE OR NF FE Wake up
unit
7 TE SBK 7
Transmitter Flag Receiver
control control control
Transmitter Receiver
clock clock
SCLK Clock extraction
pin phase and
polarity control
7 65 4 32 1 0 SCCR1
R8 T8 M WAKE CPOL CPHA LBCL $000E
Note: The serial communications data register (SCI SCDR) is controlled by the internal
R/W signal. It is the transmit data register when written to and the receive data
register when read.
Figure 7-1 Serial communications interface block diagram
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7.2 SCI receiver features
Receiver wake-up function (idle line or address bit)
Idle line detection
Framing error detection
Noise detection
Overrun detection
Receiver data register full flag
7.3 SCI transmitter features
Transmit data register empty flag
Transmit complete flag
Send break 7
7.4 Functional description
A block diagram of the SCI is shown in Figure 7-1. Option bits in serial control register1 (SCCR1)
select the `wake-up' method (WAKE bit) and data word length (M bit) of the SCI. SCCR2 provides
control bits that individually enable the transmitter and receiver, enable system interrupts and
provide the wake-up enable bit (RWU) and the send break code bit (SBK). Control bits in the baud
rate register (BAUD) allow the user to select one of 32 different baud rates for the transmitter and
receiver (see Section 7.11.5).
Data transmission is initiated by writing to the serial communications data register (SCDR).
Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit data
shift register. This transfer of data sets the transmit data register empty flag (TDRE) in the SCI
status register (SCSR) and generates an interrupt (if transmitter interrupts are enabled). The
transfer of data to the transmit data shift register is synchronized with the bit rate clock (see
Figure 7-2). All data is transmitted least significant bit first. Upon completion of data transmission,
the transmission complete flag (TC) in the SCSR is set (provided no pending data, preamble or
break is to be sent) and an interrupt is generated (if the transmit complete interrupt is enabled). If
the transmitter is disabled, and the data, preamble or break (in the transmit data shift register) has
been sent, the TC bit will also be set. This will also generate an interrupt if the transmission
complete interrupt enable bit (TCIE) is set. If the transmitter is disabled during a transmission, the
character being transmitted will be completed before the transmitter gives up control of the
TDO pin.
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When SCDR is read, it contains the last data byte received, provided that the receiver is enabled.
The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has
been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the
receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is
synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error
flags in the SCSR may be set if data reception errors occurred.
An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects
idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-up mode to
detect the end of a message or the preamble of a new message, or to resynchronize with the
transmitter. A valid character must be received before the idle line condition or the IDLE bit will not
be set and idle line interrupt will not be generated.
The SCP0 and SCP1 bits function as a prescaler for SCR0SCR2 to generate the receiver baud rate
and for SCT0SCT2 to generate the transmitter baud rate. Together, these eight bits provide multiple
transmitter/receiver rate combinations for a given crystal frequency (see Figure 7-2). This register
should only be written to while both the transmitter and receiver are disabled (TE=0, RE=0).
Internal processor clock
7 SCP0 SCP1
prescaler
rate control
( NP)
SCT0 SCT2 SCR0 SCR2
transmitter receiver
rate control
rate control
( NR)
( NT)
16 SCP1 SPC0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 $000D
Transmitter clock 7 6 5 4 3 2 1 0
Baud rate register
Receiver clock
Note: There is a fixed rate divide-by-16 before the transmitter to compensate for the inherent divide-by-16 of
the receiver (sampling). This means that by loading the same value for both the transmitter and receiver
baud rate selector, the same baud rates can be obtained.
Figure 7-2 SCI rate generator division
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7.5 Data format
Receive data or transmit data is the serial data that is transferred to the internal data bus from the
receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The
non-return-to-zero (NRZ) data format shown in Figure 7-3 is used and must meet the following
criteria:
The idle line is brought to a logic one state prior to transmission/reception of
a character.
A start bit (logic zero) is used to indicate the start of a frame.
The data is transmitted and received least significant bit first.
A stop bit (logic one) is used to indicate the end of a frame. A frame consists
of a start bit, a character of eight or nine data bits, and a stop bit.
A break is defined as the transmission or reception of a low (logic zero) for at
least one complete frame time (10 zeros for 8-bit format, 11 zeros for 9-bit).
Control bit M selects
8 or 9 bit data
7
Idle line 012345678 0
Start Stop Start
Figure 7-3 Data format
7.6 Receiver wake-up operation
The receiver logic hardware also supports a receiver wake-up function which is intended for
systems having more than one receiver. With this function a transmitting device directs messages
to an individual receiver or group of receivers by passing addressing information as the initial
byte(s) of each message. The wake-up function allows receivers not addressed to remain in a
dormant state for the remainder of the unwanted message. This eliminates any further software
overhead to service the remaining characters of the unwanted message and thus improves system
performance.
The receiver is placed in wake-up mode by setting the receiver wake-up bit (RWU) in the SCCR2
register. While RWU is set, all of the receiver related status flags (RDRF, IDLE, OR, NF, and FE)
are inhibited (cannot become set). Note that the idle line detect function is inhibited while the RWU
bit is set. Although RWU may be cleared by a software write to SCCR2, it would be unusual to do
so. Normally RWU is set by software and is cleared automatically in hardware by one of the two
methods described below.
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7.6.1 Idle line wake-up
In idle line wake-up mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle
is defined as a continuous logic high level on the RDI line for ten (or eleven) full bit times. Systems
using this type of wake-up must provide at least one character time of idle between messages to
wake up sleeping receivers, but must not allow any idle time between characters within a message.
7.6.2 Address mark wake-up
In address mark wake-up, the most significant bit (MSB) in a character is used to indicate whether
it is an address (1) or data (0) character. Sleeping receivers will wake up whenever an address
character is received. Systems using this method for wake-up would set the MSB of the first
character of each message and leave it clear for all other characters in the message. Idle periods
may be present within messages and no idle time is required between messages for this wake-up
method.
7 7.7 Receive data in (RDI)
Receive data is the serial data that is applied through the input line and the SCI to the internal bus.
The receiver circuitry clocks the input at a rate equal to 16 times the baud rate. This time is referred
to as the RT rate in Figure 7-4 and as the receiver clock in Figure 7-2.
The receiver clock generator is controlled by the baud rate register, as shown in Figure 7-1 and
Figure 7-2; however, the SCI is synchronized by the start bit, independent of the transmitter.
Once a valid start bit is detected, the start bit, each data bit and the stop bit are sampled three
times at RT intervals 8 RT, 9 RT and 10 RT (1 RT is the position where the bit is expected to start),
as shown in Figure 7-5. The value of the bit is determined by voting logic which takes the value of
the majority of the samples. A noise flag is set when all three samples on a valid start bit or data
bit or the stop bit do not agree.
7.8 Start bit detection
When the input (idle) line is detected low, it is tested for three more sample times (referred to as
the start edge verification samples in Figure 7-4). If at least two of these three verification samples
detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to be idle. A
noise flag is set if one of the three verification samples detect a logic one, thus a valid start bit could
be assumed with a set noise flag present.
If there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros
for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start
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16X internal sampling clock
RT clock edges for all three examples 1RT 2RT 3RT 4RT 5RT 6RT 7RT 8RT
Idle Start
RDI
111111111110 0 0 0
Start
Start edge
qualifiers
verification samples
Start Noise
RDI
0 1 0
111111111110
Noise Start
RDI
111110111110 0 0 0
Figure 7-4 SCI examples of start bit sampling technique 7
Previous bit Present bit Samples Next bit
8RT 9RT 10RT 16RT 1RT
RDI <
<
<
16RT 1RT
Figure 7-5 SCI sampling technique used on all bits
edge will be placed artificially. The last bit received in the data shift register is inverted to a logic
one, and the three logic one start qualifiers (shown in Figure 7-4) are forced into the sample shift
register during the interval when detection of a start bit is anticipated (see Figure 7-6); therefore,
the start bit will be accepted no sooner than it is anticipated.
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If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $0000) produced
the framing error, the start bit will not be artificially induced and the receiver must actually detect
a logic one before the start bit can be recognised (see Figure 7-7).
Data Expected stop Artificial edge Data
RDI Start bit
Data samples
a) Case 1: receive line low during artificial edge
Data Expected stop Start edge Data
RDI Start bit
7 Data samples
b) Case 2: receive line high during expected start edge
Figure 7-6 Artificial start following a framing error
Expected stop Detected as valid start edge
Break Start bit
RDI
Start Start edge
qualifiers verification
samples
Data samples
Figure 7-7 SCI start bit following a break
7.9 Transmit data out (TDO)
Transmit data is the serial data from the internal data bus that is applied through the SCI to the
output line. Data format is as discussed in Section 7.5 and shown in Figure 7-3. The transmitter
generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal
to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the
receiver and transmitter).
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7.10 SCI synchronous transmission
The SCI transmitter allows the user to control a one way synchronous serial transmission. The
SCLK pin is the clock output of the SCI transmitter. No clocks are sent to that pin during start bit
and stop bit. Depending on the state of the LBCL bit (bit 0 of SCCR1), clocks will or will not be
activated during the last valid data bit (address mark). The CPOL bit (bit 2 of SCCR1) allows the
user to select the clock polarity, and the CPHA bit (bit 1 of SCCR1) allows the user to select the
phase of the external clock (see Figure 7-8, Figure 7-9 and Figure 7-10).
During idle, preamble and send break, the external SCLK clock is not activated.
These options allow the user to serially control peripherals which consist of shift registers, without
losing any functions of the SCI transmitter which can still talk to other SCI receivers. These options
do not affect the SCI receiver which is independent of the transmitter.
The SCLK pin works in conjunction with the TDO pin. When the SCI transmitter is disabled
(TE = 0), the SCLK and TDO pins go to the high impedance state.
Note: The LBCL, CPOL and CPHA bits have to be selected before enabling the transmitter to
ensure that the clocks function correctly. These bits should not be changed while the 7
transmitter is enabled.
RDI Data out Asynchronous
TDO Data in (e.g. Modem)
SCLK
MC68HC05X16 Data in Synchronous
Clock (e.g. shift register,
Output port Enable display driver, etc.)
Figure 7-8 SCI example of synchronous and asynchronous transmission
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7.11 SCI registers
The SCI system is configured and controlled by five registers: SCDR, SCCR1, SCCR2, SCSR,
and BAUD.
7.11.1 Serial communications data register (SCDR)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
SCI data (SCDR) $0011 0000 0000
The SCDR is controlled by the internal R/W signal and performs two functions in the SCI. It acts
as the receive data register (RDR) when it is read and as the transmit data register (TDR) when it
is written. Figure 7-1 shows this register as two separate registers, RDR and TDR. The RDR
provides the interface from the receive shift register to the internal data bus and the TDR provides
the parallel interface from the internal data bus to the transmit shift register.
7 The receive data register is a read-only register containing the last byte of data received from the
shift register for the internal data bus. The RDR full bit (RDRF) in the serial communications status
register is set to indicate that a byte has been transferred from the input serial shift register to the
SCDR. The transfer is synchronized with the receiver bit rate clock (from the receiver control) as
shown in Figure 7-1. All data is received with the least significant bit first.
The transmit data register (TDR) is a write-only register containing the next byte of data to be
applied to the transmit shift register from the internal data bus. As long as the transmitter is
enabled, data stored in the SCDR is transferred to the transmit shift register (after the current byte
in the shift register has been transmitted).
The transfer is synchronized with the transmitter bit rate clock (from the transmitter control) as
shown in Figure 7-1. All data is received with the least significant bit first.
7.11.2 Serial communications control register 1 (SCCR1)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
SCI control 1 (SCCR1) $000E R8 T8 M WAKE CPOL CPHA LBCL Undefined
The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character
format, the receiver wake-up feature and the options to output the transmitter clocks for
synchronous transmissions.
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R8 -- Receive data bit 8
This read-only bit is the ninth serial data bit received when the SCI system is configured for nine
data bit operation (M = 1). The most significant bit (bit 8) of the received character is transferred
into this bit at the same time as the remaining eight bits (bits 07) are transferred from the serial
receive shift register to the SCI receive data register.
T8 -- Transmit data bit 8
This read/write bit is the ninth data bit to be transmitted when the SCI system is configured for nine
data bit operation (M = 1). When the eight low order bits (bits 07) of a transmit character are
transferred from the SCI data register to the serial transmit shift register, this bit (bit 8) is transferred
to the ninth bit position of the shift register.
M -- Mode (select character format)
The read/write M-bit controls the character length for both the transmitter and receiver at the same
time. The 9th data bit is most commonly used as an extra stop bit or it can also be used as a parity
bit (see Table 7-1).
1 (set) Start bit, 9 data bits, 1 stop bit. 7
0 (clear) Start bit, 8 data bits, 1 stop bit.
Table 7-1 Method of receiver wake-up
WAKE M Method of receiver wake-up
0 x Detection of an idle line allows the next data type received to cause the receive
data register to fill and produce an RDRF flag.
1 0
Detection of a received one in the eighth data bit allows an RDRF flag and
1 1 associated error flags.
Detection of a received one in the ninth data bit allows an RDRF flag and
associated error flags.
x = Don't care
WAKE -- Wake-up mode select
This bit allows the user to select the method for receiver wake-up. The WAKE bit can be read or
written to any time. See Table 7-1.
1 (set) Wake-up on address mark; if RWU is set, SCI will wake-up if the 8th
(if M=0) or the 9th (if M=1) bit received on the Rx line is set.
0 (clear) Wake-up on idle line; if RWU is set, SCI will wake-up after 11 (if M=0)
or 12 (if M=1) consecutive `1's on the Rx line.
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CPOL Clock polarity
This bit allows the user to select the polarity of the clocks to be sent to the SCLK pin. It works in
conjunction with the CPHA bit to produce the desired clock-data relation (see Figure 7-9 and
Figure 7-10).
1 (set) Steady high value at SCLK pin outside transmission window.
0 (clear) Steady low value at SCLK pin outside transmission window.
This bit should not be manipulated while the transmitter is enabled.
CPHA Clock phase
This bit allows the user to select the phase of the clocks to be sent to the SCLK pin. This bit works
in conjunction with the CPOL bit to produce the desired clock-data relation (see Figure 7-9 and
Figure 7-10).
1 (set) SCLK clock line activated at beginning of data bit.
0 (clear) SCLK clock line activated in middle of data bit.
7 This bit should not be manipulated while the transmitter is enabled.
Idle or preceding M = 0 (8 data bits) Idle or next
transmission Start Stop transmission
clock *
(CPOL = 0, CPHA = 0)
clock *
(CPOL = 0, CPHA = 1)
clock *
(CPOL = 1, CPHA = 0)
clock *
(CPOL = 1, CPHA = 1)
data 01234567
Start LSB MSB Stop
* LBCL bit controls last data clock
Figure 7-9 SCI data clock timing diagram (M=0)
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Idle or preceding M = 1 (9 data bits) Idle or next
transmission Start Stop transmission
clock *
(CPOL = 0, CPHA = 0)
clock *
(CPOL = 0, CPHA = 1)
clock *
(CPOL = 1, CPHA = 0)
clock *
(CPOL = 1, CPHA = 1)
data 012345678
Start LSB MSB Stop
* LBCL bit controls last data clock
Figure 7-10 SCI data clock timing diagram (M=1) 7
LBCL Last bit clock
This bit allows the user to select whether the clock associated with the last data bit transmitted
(MSB) has to be output to the SCLK pin. The clock of the last data bit is output to the SCLK pin if
the LBCL bit is a logic one, and is not output if it is a logic zero.
The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected by M-bit
(seeTable 7-2).
This bit should not be manipulated while the transmitter is enabled.
Table 7-2 SCI clock on SCLK pin
Data format M-bit LBCL bit Number of clocks on
SCLK pin
8 bit 0 0 7
8
8 bit 0 1 8
9
9 bit 1 0
9 bit 1 1
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7.11.3 Serial communications control register 2 (SCCR2)
The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI
functions.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
SCI control (SCCR2) $000F TIE TCIE RIE ILIE TE RE RWU SBK 0000 0000
TIE -- Transmit interrupt enable
1 (set) TDRE interrupts enabled.
0 (clear) TDRE interrupts disabled.
TCIE -- Transmit complete interrupt enable
1 (set) TC interrupts enabled.
0 (clear) TC interrupts disabled.
7 RIE -- Receiver interrupt enable
1 (set) RDRF and OR interrupts enabled.
0 (clear) RDRF and OR interrupts disabled.
ILIE -- Idle line interrupt enable
1 (set) IDLE interrupts enabled.
0 (clear) IDLE interrupts disabled.
TE -- Transmitter enable
When the transmit enable bit is set, the transmit shift register output is applied to the TDO line and
the corresponding clocks are applied to the SCLK pin. Depending on the state of control bit M
(SCCR1), a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones is transmitted when software
sets the TE bit from a cleared state.
If a transmission is in progress and a zero is written to TE, the transmitter will wait until after the
present byte has been transmitted before placing the TDO and the SCLK pin in the idle, high
impedance state.
If the TE bit has been written to a zero and then set to a one before the current byte is transmitted,
the transmitter will wait for that byte to be transmitted and will then initiate transmission of a new
preamble. After this latest transmission, and provided the TDRE bit is set (no new data to transmit),
the line remains idle (driven high while TE = 1); otherwise, normal transmission occurs. This
function allows the user to neatly terminate a transmission sequence.
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After loading the last byte in the serial communications data register and receiving the TDRE flag,
the user should clear TE. Transmission of the last byte will then be completed and the line will go
idle.
1 (set) Transmitter enabled.
0 (clear) Transmitter disabled.
RE -- Receiver enable
1 (set) Receiver enabled.
0 (clear) Receiver disabled.
When RE is clear (receiver disabled) all the status bits associated with the receiver (RDRF, IDLE,
OR, NF and FE) are inhibited.
RWU -- Receiver wake-up
When the receiver wake-up bit is set by the user software, it puts the receiver to sleep and enables
the wake-up function. The type of wake-up mode for the receiver is determined by the WAKE bit
discussed above (in the SCCR1). When the RWU bit is set, no status flags will be set. Flags which 7
were set previously will not be cleared when RWU is set.
If the WAKE bit is cleared, RWU is cleared by the SCI logic after receiving 10 (M = 0) or 11 (M =1)
consecutive ones. Under these conditions, RWU cannot be set if the line is idle. If the WAKE bit is
set, RWU is cleared after receiving an address bit. The RDRF flag will then be set and the address
byte stored in the receiver data register.
SBK -- Send break
If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M = 1) zeros
and then reverts to idle sending data. If SBK remains set, the transmitter will continually send
whole blocks of zeros (sets of 10 or 11) until cleared. At the completion of the break code, the
transmitter sends at least one high bit to guarantee recognition of a valid start bit.
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7.11.4 Serial communications status register (SCSR)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
SCI status (SCSR) $0010 TDRE TC RDRF IDLE OR NF FE 1100 000u
The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for
generation of the SCI system interrupt. In addition, a noise flag bit and a framing error bit are also
contained in the SCSR.
TDRE -- Transmit data register empty flag
This bit is set when the contents of the transmit data register are transferred to the serial shift
register. New data will not be transmitted unless the SCSR register is read before writing to the
transmit data register to clear the TDRE flag.
If the TDRE bit is clear, this indicates that the transfer has not yet occurred and a write to the serial
communications data register will overwrite the previous value. The TDRE bit is cleared by
accessing the serial communications status register (with TDRE set) followed by writing to the
7 serial communications data register.
TC -- Transmit complete flag
This bit is set to indicate that the SCI transmitter has no meaningful information to transmit (no data
in shift register, no preamble, no break). When TC is set the serial line will go idle (continuous
MARK). The TC bit is cleared by accessing the serial communications status register (with TC set)
followed by writing to the serial communications data register. It does not inhibit the transmitter
function in any way.
RDRF -- Receive data register full flag
This bit is set when the contents of the receiver serial shift register are transferred to the receiver
data register.
If multiple errors are detected in any one received word, the NF and RDRF bits will be affected as
appropriate during the same clock cycle. The RDRF bit is cleared when the serial communications
status register is accessed (with RDRF set) followed by a read of the serial communications data
register.
IDLE -- Idle line detected flag
This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven
consecutive `1's). This bit will not be set by the idle line condition when the RWU bit is set. This
allows a receiver that is not in the wake-up mode to detect the end of a message, detect the
preamble of a new message or resynchronize with the transmitter. The IDLE bit is cleared by
accessing the serial communications status register (with IDLE set) followed by a read of the serial
communications data register. Once cleared, IDLE will not be set again until after RDRF has been
set, (i.e. until after the line has been active and becomes idle again).
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OR -- Overrun error flag
This bit is set when a new byte is ready to be transferred from the receiver shift register to the
receiver data register and the receive data register is already full (RDRF bit is set). Data transfer
is inhibited until the RDRF bit is cleared. Data in the serial communications data register is valid in
this case, but additional data received during an overrun condition (including the byte causing the
overrun) will be lost.
The OR bit is cleared when the serial communications status register is accessed (with OR set)
followed by a read of the serial communications data register.
NF -- Noise error flag
This bit is set if there is noise on a `valid' start bit, any of the data bits or on the stop bit. The NF bit
is not set by noise on the idle line nor by invalid start bits. If there is noise, the NF bit is not set until
the RDRF flag is set. Each data bit is sampled three times as described in Section 7.7.
The NF bit represents the status of the byte in the serial communications data register. For the byte
being received (shifted in) there will be also a `working' noise flag, the value of which will be
transferred to the NF bit when the serial data is loaded into the serial communications data
register. The NF bit does not generate an interrupt because the RDRF bit gets set with NF and can 7
be used to generate the interrupt.
The NF bit is cleared when the serial communications status register is accessed (with NF set)
followed by a read of the serial communications data register.
FE -- Framing error flag
This bit is set when the word boundaries in the bit stream are not synchronized with the receiver
bit counter (generated by the reception of a logic zero bit where a stop bit was expected). The FE
bit reflects the status of the byte in the receive data register and the transfer from the receive shift
register to the receive data register is inhibited by an overrun. The FE bit is set during the same
cycle as the RDRF bit but does not get set in the case of an overrun (OR). The framing error flag
inhibits further transfer of data into the receive data register until it is cleared.
The FE bit is cleared when the serial communications status register is accessed (with FE set)
followed by a read of the serial communications data register.
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7.11.5 Baud rate register (BAUD)
The baud rate register provides the means to select two different or equivalent baud rates for the
transmitter and receiver.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
SCI baud rate (BAUD) $000D SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 00uu uuuu
SCP1, SCP0 -- Serial prescaler select bits
These read/write bits determine the prescale factor, NP, by which the internal processor clock is
divided before it is applied to the transmitter and receiver rate control dividers, NT and NR. This
common prescaled output is used as the input to a divider that is controlled by the SCR0SCR2
bits for the SCI receiver, and by the SCT0SCT2 bits for the transmitter.
Table 7-3 First prescaler stage
7 SCP1 SCP0 Prescaler
0 0 division ratio (NP)
1
0 1 3
1 0 4
1 1 13
SCT2, SCT1, SCT0 -- SCI rate select bits (transmitter)
These three read/write bits select the baud rates for the transmitter. The prescaler output is divided
by the factors shown in Table 7-4.
Table 7-4 Second prescaler stage (transmitter)
SCT2 SCT1 SCT0 Transmitter
division ratio (NT)
0 0 0
0 0 1 1
0 1 0 2
0 1 1 4
1 0 0 8
1 0 1 16
1 1 0 32
1 1 1 64
128
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SCR2, SCR1, SCR0 -- SCI rate select bits (receiver)
These three read/write bits select the baud rates for the receiver. The prescaler output described
above is divided by the factors shown in Table 7-5.
Table 7-5 Second prescaler stage (receiver)
SCR2 SCR1 SCR0 Receiver
division ratio (NR)
0 0 0
0 0 1 1
0 1 0 2
0 1 1 4
1 0 0 8
1 0 1 16
1 1 0 32
1 1 1 64
128
The following equations are used to calculate the receiver and transmitter baud rates: 7
baudTx = 1----6---------N-f--c--P-l-k-------N-----R---
baudRx = 1----6---------N-f--c--P-l-k-------N-----R---
where:
NP = prescaler divide ratio
NT = transmitter baud rate divide ratio
NR = receiver baud rate divide ratio
baudTx = transmitter baud rate
baudRx = receiver baud rate
fCLK = CPU clock frequency
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7.12 Baud rate selection
The flexibility of the baud rate generator allows many different baud rates to be selected, depending
on the CPU clock frequency. A particular baud rate may be generated by manipulating the various
prescaler and division ratio bits. Table 7-6, Table 7-7 and Table 7-8 show the highest baud rates that
can be achieved for five typical crystal frequencies, for each of the CPU clock frequency options and
only using the prescaler bits. Table 7-9 shows how lower transmitter or receiver baud rates may be
obtained using a further division ratio provided by the SCI rate select bits. Note that the five
examples given in Table 7-9 are representative samples only.
Table 7-6 SCI baud rate selection with CPU clock frequency = fOSC/2
Clock Crystal frequency fosc (MHz)
SCP1 divided
SCP0 by 4.194304 4.00 2.4576 2.00 1.8432
0 0 1 131072 125000 76800 62500 57600
0 1 3 43691 41667 25600 20833 19200
7 1 0 4 32768 31250 19200 15625 14400
1 1 13 10082 9600 5907 4800 4430
Table 7-7 SCI baud rate selection with CPU clock frequency = fOSC/8
SCP1 SCP0 Clock 16.00 Crystal frequency fosc (MHz) 2.4576
divided 8.00 4.9152 4.194304
0 0 125000 19200
0 1 by 41667 62500 38400 32768 14400
1 0 1 31250 20833 12800 10082 4430
1 1 3 9600 15625 9600 8192 1477
4 4800 2954 2521
13
Table 7-8 SCI baud rate selection with CPU clock frequency = fOSC/10
SCP1 SCP0 Clock 20.00 Crystal frequency fosc (MHz) 5.0
divided 18.432 10.00 6.144
0 0 125000 31250
0 1 by 41667 115200 62500 38400 10417
1 0 1 31250 38400 20833 12800 7813
1 1 3 9600 28800 15625 9600 2400
4 8861 4800 2954
13
Note: The clock in the `Clock divided by' column refers to the internal processor clock.
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Table 7-9 SCI transmit baud rate output for a given prescaler output
SCT/SCR bits Divide Representative highest prescaler baud rate output
by
Bit 2 Bit 1 Bit 0 1 131072 32768 38400 19200 9600
2
0 0 0 4 131072 32768 38400 19200 9600
8
0 0 1 16 65536 16384 19200 9600 4800
32
0 1 0 64 32768 8192 9600 4800 2400
128
0 1 1 16384 4096 4800 2400 1200
1 0 0 8192 2048 2400 1200 600
1 0 1 4096 1024 1200 600 300
1 1 0 2048 512 600 300 150
1 1 1 1024 256 300 150 75
Note: The examples shown in Table 7-6, Table 7-7, Table 7-8 and Table 7-9 do not apply when
the part is operating in slow mode (see Section 2.2.3).
For the receiver, the internal clock frequency is 16 times higher than the selected baud
rate.
7
7.13 SCI during STOP mode
When the MCU enters STOP mode, the baud rate generator driving the receiver and transmitter
is shut down. This stops all SCI activity. Both the receiver and the transmitter are unable to operate.
If the STOP instruction is executed during a transmitter transfer, that transfer is halted. When STOP
mode is exited as a result of an external interrupt, that particular transmission resumes.
If the receiver is receiving data when the STOP instruction is executed, received data sampling is
stopped (baud generator stops) and the rest of the data is lost.
Warning: For the above reasons, all SCI transactions should be in the idle state when the STOP
instruction is executed.
7.14 SCI during WAIT mode
The SCI system is not affected by WAIT mode and continues normal operation. Any valid SCI
interrupt will wake-up the system. If required, the SCI system can be disabled prior to entering
WAIT mode by writing a zero to the transmitter and receiver enable bits in the serial communication
control register 2 at $000F. This action will result in a reduction of power consumption during WAIT
mode.
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8
PULSE LENGTH D/A CONVERTERS
The pulse length D/A converter (PLM) system works in conjunction with the timer to execute two
8-bit D/A conversions, with a choice of two repetition rates. (See Figure 8-1.)
Data bus
8 8
PLMA PLMB
register register
`A' register `B' register 8
buffer buffer
`A' `B'
comparator comparator
PLMA R R PLMB
Latch Latch D/A
D/A pin
pin S S
From timer
Zero detector 8 Zero detector
8
SFA `A'
bit multiplexer `B' SFB
16 multiplexer bit
16
Timer bus
Figure 8-1 PLM system block diagram
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The D/A converter has two data registers associated with it, PLMA and PLMB.
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Pulse length modulation A (PLMA) $000A 0000 0000
Pulse length modulation B (PLMB) $000B 0000 0000
This is a dual 8-bit resolution D/A converter associated with two output pins (PLMA and PLMB).
The outputs are pulse length modulated signals whose duty cycle ratio may be modified. These
signals can be used directly as PLMs, or the filtered average may be used as general purpose
analog outputs.
The longest repetition period is 4096 times the programmable timer clock period (CPU clock
multiplied by four), and the shortest repetition period is 256 times the programmable timer clock
period (the repetition rate frequencies for a 4 MHz crystal are 122 Hz and 1953 Hz respectively).
Registers PLMA ($0A) and PLMB ($0B) are associated with the pulse length values of the two
counters. A value of $00 loaded into these registers results in a continuously low output on the
corresponding D/A output pin. A value of $80 results in a 50% duty cycle output, and so on, to the
maximum value $FF corresponding to an output which is at `1' for 255/256 of the cycle. When the
MCU makes a write to register PLMA or PLMB the new value will only be picked up by the D/A
converters at the end of a complete cycle of conversion. This results in a monotonic change of the
DC component at the output without overshoots or vicious starts (a vicious start is an output which
8 gives totally erroneous PLM during the period immediately following an update of the PLM D/A
registers). This feature is achieved by double buffering of the PLM D/A registers. Examples of
PWM output waveforms are shown in Figure 8-2.
$00 256 T
255 T
$01 T
128 T
$80 128 T
$FF 255 T T
T = 4 CPU clocks in fast mode and 64 CPU clocks in slow mode
Figure 8-2 PLM output waveform examples
MOTOROLA PULSE LENGTH D/A CONVERTERS MC68HC05X16
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Note: Since the PLM system uses the timer counter, PLM results will be affected while resetting
the timer counter. Both D/A registers are reset to $00 during power-on or external reset.
WAIT mode does not affect the output waveform of the D/A converters.
8.1 Miscellaneous register
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Miscellaneous $000C POR INTP INTN INTE SFA SFB SM WDOG u001 000u
SFA -- Slow or fast mode selection for PLMA
This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation output.
1 (set) Slow mode PLMA (4096 x timer clock period).
0 (clear) Fast mode PLMA (256 x timer clock period).
SFB -- Slow or fast mode selection for PLMB
This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation output.
1 (set) Slow mode PLMB (4096 x timer clock period). 8
0 (clear) Fast mode PLMB (256 x timer clock period).
The highest speed of the PLM system corresponds to the frequency of the TOF bit being set,
multiplied by 256. The lowest speed of the PLM system corresponds to the frequency of the TOF
bit being set, multiplied by 16. Because the SFA bit and SFB bit are not double buffered, it is
mandatory to set them to the desired values before writing to the PLM registers; not doing so could
temporarily give incorrect values at the PLM outputs.
SM -- Slow mode
1 (set) The system runs at a bus speed 16 times lower than normal
(fOSC/32). SLOW mode affects all sections of the device, including
SCI, A/D and timer.
0 (clear) The system runs at normal bus speed (fOSC/2).
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
Note: The bits that are shown shaded in the above representation are explained individually
in the relevant sections of this manual. The complete register plus an explanation of
each bit can be found in Section 3.8.
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8.2 PLM clock selection
The slow/fast mode of the PLM D/A converters is selected by bits 1, 2, and 3 of the miscellaneous
register at address $000C (SFA bit for PLMA and SFB bit for PLMB). The slow/fast mode has no
effect on the D/A converters' 8-bit resolution (see Figure 8-3).
SM bit = 0 Bus Timer
2 frequency (fOP) 4 clock x4096 SF bit = 1
fOSC PLM
clock
SM bit = 1 SF bit = 0
32 x256
Figure 8-3 PLM clock selection
8.3 PLM during STOP mode
On entering STOP mode, the PLM outputs remain at their particular level. When STOP mode is
8 exited by an interrupt, the PLM systems resume regular operation. If STOP mode is exited by
power-on or external reset the registers values are forced to $00.
8.4 PLM during WAIT mode
The PLM system is not affected by WAIT mode and continues normal operation.
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9
ANALOG TO DIGITAL CONVERTER
The analog to digital converter system consists of a single 8-bit successive approximation
converter and a sixteen channel multiplexer. Eight of the channels are connected to the
PD0/AN0 PD7/AN7 pins of the MC68HC05X16 and the other eight channels are dedicated to
internal reference points for test functions. The channel input pins do not have any internal output
driver circuitry connected to them because such circuitry would load the analog input signals due
to output buffer leakage current. There is one 8-bit result data register (address $08) and one 8-bit
status/control register (address $09).
The A/D converter is ratiometric and two dedicated pins, VRH and VRL, are used to supply the
reference voltage levels for all analog inputs. These pins are used in preference to the system
power supply lines because any voltage drops in the bonding wires of the heavily loaded supply
pins could degrade the accuracy of the A/D conversion. An input voltage equal to or greater than
VRH converts to $FF (full scale) with no overflow indication and an input voltage equal to VRL
converts to $00.
The A/D converter can operate from either the bus clock or an internal RC type oscillator. The 9
internal RC type oscillator is activated by the ADRC bit in the A/D status/control register (ADSTAT)
and can be used to give a sufficiently high clock rate to the A/D converter when the bus speed is too
low to provide accurate results. When the A/D converter is not being used it can be disconnected,
by clearing the ADON bit in the ADSTAT register, in order to save power (see Section 9.2.3).
For further information on A/D converter operation please refer to the M68HC11 Reference
Manual -- M68HC11RM/AD.
9.1 A/D converter operation
The A/D converter consists of an analog multiplexer, an 8-bit digital to analog converter capacitor
array, a comparator and a successive approximation register (SAR) (see Figure 9-1).
There are eleven options that can be selected by the multiplexer; AN0AN7, VRH, (VRH+VRL)/2
or VRL. Selection is done via the CHx bits in the ADSTAT register (see Section 9.2.3). AN0AN7
are the only input points for A/D conversion operations; the others are reference points that can be
used for test purposes.
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The A/D reference input (AN0AN7) is applied to a precision internal D/A converter. Control logic
drives this D/A converter and the analog output is successively compared with the analog input
sampled at the beginning of the conversion. The conversion is monotonic with no missing codes.
AN0 8-bit capacitive DAC VRH
AN1 with sample and hold
AN2 VRL
AN3
AN4 Analog MUX Successive approximation
AN5 (Channel assignment) register (SAR) and control
AN6
AN7 Result
VRH
(VRH+VRL)/2 A/D status/control register (ADSTAT)$09
VRL CH0 CH1 CH2 CH3 0 ADON ADRC COCO
A/D result register (ADDATA) $08
9
Figure 9-1 A/D converter block diagram
The result of each successive comparison is stored in the SAR and, when the conversion is
complete, the contents of the SAR are transferred to the read-only result data register ($08), and
the conversion complete flag, COCO, is set in the A/D status/control register ($09).
Warning: Any write to the A/D status/control register will abort the current conversion, reset the
conversion complete flag and start a new conversion on the selected channel.
At power-on or external reset, both the ADRC and ADON bits are cleared; thus the A/D is disabled.
MOTOROLA ANALOG TO DIGITAL CONVERTER MC68HC05X16
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9.2 A/D registers
9.2.1 Port D data register (PORTD)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Port D data (PORTD) $0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
Port D is an input-only port which routes the eight analog inputs to the A/D converter. When the
A/D converter is disabled, the pins are configured as standard input-only port pins, which can be
read via the port D data register.
Note: When the A/D function is enabled, pins PD0PD7 will act as analog inputs. Using a pin
or pins as A/D inputs does not affect the ability to read port D as static inputs; however,
reading port D during an A/D conversion sequence may inject noise on the analog
inputs and result in reduced accuracy of the A/D result.
Performing a digital read of port D with levels other than VDD or VSS on the pins will
result in greater power dissipation during the read cycle, and may give unpredictable
results on the corresponding port D pins.
9.2.2 A/D result data register (ADDATA)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State 9
on reset
A/D data (ADDATA) $0008 0000 0000
ADDATA is a read-only register which is used to store the results of A/D conversions. Each result
is loaded into the register from the SAR and the conversion complete flag, COCO, in the ADSTAT
register is set.
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9.2.3 A/D status/control register (ADSTAT)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
A/D status/control (ADSTAT) $0009 COCO ADRC ADON 0 CH3 CH2 CH1 CH0 0000 0000
COCO -- Conversion complete flag
1 (set) COCO is set each time a conversion is complete, allowing the new
result to be read from the A/D result data register ($08). The
converter then starts a new conversion.
0 (clear) COCO is cleared by reading the result data register or writing to the
status/control register.
Reset clears the COCO flag.
ADRC -- A/D RC oscillator control
The ADRC bit allows the user to control the A/D RC oscillator, which is used to provide a
sufficiently high clock rate to the A/D to ensure accuracy when the chip is running at low speeds.
1 (set) When the ADRC bit is set, the A/D RC oscillator is turned on and, if
ADON is set, the A/D runs from the RC oscillator clock. See Table 9-1.
0 (clear) When the ADRC bit is cleared, the A/D RC oscillator is turned-off
and, if ADON is set, the A/D runs from the CPU clock.
9 When the A/D RC oscillator is turned on, it takes a time tADRC to stabilize (see Table 12-3). During
this time A/D conversion results may be inaccurate.
Note: If the MCU bus clock falls below 1MHz, the A/D RC oscillator should be switched on.
Power-on or external reset clears the ADRC bit.
Table 9-1 A/D clock selection
ADRC ADON RC A/D Comments
0 0 oscillator converter
0 1
1 0 OFF OFF A/D switched off.
1 1
OFF ON A/D using CPU clock.
ON OFF Allows the RC oscillator to stabilize.
ON ON A/D using RC oscillator clock.
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ADON -- A/D converter on
The ADON bit allows the user to enable/disable the A/D converter.
1 (set) A/D converter is switched on.
0 (clear) A/D converter is switched off.
When the A/D converter is switched on, it takes a time tADON for the current sources to stabilize
(see Table 12-3). During this time A/D conversion results may be inaccurate.
Power-on or external reset will clear the ADON bit, thus disabling the A/D converter.
CH3CH0 -- A/D channels 3, 2, 1 and 0
The CH3CH0 bits allow the user to determine which channel of the A/D converter multiplexer is
selected. See Table 9-2 for channel selection.
Reset clears the CH0CH3 bits.
Table 9-2 A/D channel assignment
CH3 CH2 CH1 CH0 Channel selected
0 0 0 0 AN0
0 0 0 1 AN1
0 0 1 0 AN2
0 0 1 1 AN3
0 1 0 0 AN4 9
0 1 0 1 AN5
0 1 1 0 AN6
0 1 1 1 AN7
1 0 0 0 VRH pin (high)
1 0 0 1 (VRH + VRL) / 2
1 0 1 0 VRL pin (low)
1 0 1 1 VRL pin (low)
1 1 0 0 VRL pin (low)
1 1 0 1 VRL pin (low)
1 1 1 0 VRL pin (low)
1 1 1 1 VRL pin (low)
9.3 A/D converter during STOP mode
When the MCU enters STOP mode with the A/D converter turned on, the A/D clocks are stopped
and the A/D converter is disabled for the duration of STOP mode, including the 4064 cycles
start-up time. If the A/D RC oscillator is in operation it will also be disabled.
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9.4 A/D converter during WAIT mode
The A/D converter is not affected by WAIT mode and continues normal operation.
In order to reduce power consumption the A/D converter can be disconnected, under software
control using the ADON bit and the ADRC bit in the A/D status/control register at $0009, before
entering WAIT mode.
9.5 Port D analog input
The external analog voltage value to be processed by the A/D converter is sampled on an internal
capacitor through a resistive path, provided by input-selection switches and a sampling aperture
time switch, as shown in Figure 9-2. Sampling time is limited to 12 bus clock cycles. After sampling,
the analog value is stored on the capacitor and held until the end of conversion. During this hold
time, the analog input is disconnected from the internal A/D system and the external voltage
source sees a high impedance input.
The equivalent analog input during sampling is an RC low-pass filter with a minimum resistance
of 50 k and a capacitance of at least 10pF. It should be noted that these are typical values
measured at room temperature.
Input protection device 50k
Analog
9 input + ~20V
pin
< 2pF - ~0.7V
400 nA 10pF
junction
leakage DAC
capacitance
Note: VRL
The analog switch is closed during the 12 cycle sample
time only.
Figure 9-2 Electrical model of an A/D input pin
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10
RESETS AND INTERRUPTS
10.1 Resets
The MC68HC05X32 can be reset in three ways: by the initial power-on reset function, by an active
low input to the RESET pin or by a computer operating properly (COP) watchdog reset. Any of
these resets will cause the program to go to its starting address, specified by the contents of
memory locations $3FFE and $3FFF, and cause the interrupt mask bit in the condition code
register to be set.
tVDDR
VDD VDD threshold (1-2V typical)
tOXOV
OSC1
tPORL tCYC
Internal
processor clock
RESET (Internal power-on reset) (External hardware reset) 10
tRL(or tDOGL)
Internal
address bus 3DFE New 3DFE 3FFE 3FFF New
3FFE 3FFF PC PC
Internal
data bus Reset sequence Reset sequence
New New Op Mask options New New Op
Mask options PCH PCL code PCH PCL code
Program Program
execution execution
begins begins
Figure 10-1 Reset timing diagram
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10.1.1 Power-on reset
A power-on reset occurs when a positive transition is detected on VDD. The power-on reset
function is strictly for power turn-on conditions and should not be used to detect drops in the power
supply voltage. The power-on circuitry provides a stabilization delay (tPORL) from when the
oscillator becomes active. If the external RESET pin is low at the end of this delay then the
processor remains in the reset state until RESET goes high. The user must ensure that the voltage
on VDD has risen to a point where the MCU can operate properly by the time tPORL has elapsed.
If there is doubt, the external RESET pin should remain low until the voltage on VDD has reached
the specified minimum operating voltage. This may be accomplished by connecting an external RC
circuit to this pin to generate a power-on reset (POR). In this case, the time constant must be great
enough to allow the oscillator circuit to stabilize.
During power-on reset, the RESET pin is driven low during a tPORL delay start-up sequence. tPORL is
defined by a user specified mask option to be either 16 cycles or 4064 cycles (see Section 1.2).
A software distinction between a power-on reset and an external reset can be made using the POR
bit in the miscellaneous register (see Section 10.1.2).
10.1.2 Miscellaneous register
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Miscellaneous $000C POR(1) INTP INTN INTE SFA SFB SM WDOG(2) u001 000u
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled,
0=watchdog disabled.
10 POR -- Power-on reset bit
This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the
user to make a software distinction between a power-on and an external reset. This bit cannot be
set by software and is cleared by writing it to zero.
1 (set) A power-on reset has occurred.
0 (clear) No power-on reset has occurred.
Note: The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
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10.1.3 RESET pin
When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied
to the RESET input for a minimum period of 1.5 machine cycles (tCYC). An internal Schmitt Trigger
is used to improve noise immunity on this pin. When the RESET pin goes high, the MCU will
resume operation on the following cycle. When a reset condition occurs internally, i.e. from POR
or the COP watchdog, the RESET pin provides an active-low open drain output signal which may
be used to reset external hardware. Current limitation to protect the pull-down device is provided
in case an RC type external reset circuit is used.
Note: If an external RC is connected to RESET, turning on the RESET pull-down transistor
may discharge the capacitor. The device will then remain in reset until the capacitor has
recharged, after turning off the pull-down device.
VDD
pin
MC68HC05X16
RESET
pin
Figure 10-2 RESET external RC pull-down
10.1.4 Computer operating properly (COP) watchdog reset 10
The watchdog counter system consists of a divide-by-7 counter, preceded by a fixed divide-by-4
and a fixed divide-by-256 prescaler, plus control logic as shown in Figure 10-3. The divide-by-7
counter can be reset by software.
Note: The input to the watchdog system is derived from the carry output of bit 7 of the free
running timer counter. Therefore, a reset of the timer may affect the period of the
watchdog timeout.
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Main CPU S Power-on
clock
Latch
R
fosc/2 4 256 + Reset
fosc/32 prescaler (Bit 7 of free pin
running counter) 7 watchdog
counter
Enable
Reset
WDOG bit Control logic Schmitt Input
trigger protection
Figure 10-3 Watchdog system block diagram
The watchdog system can be automatically enabled, following power-on or external reset, via a
mask option (see Section 1.2), or it can be enabled by software by writing a `1' to the WDOG bit in
the miscellaneous register at $000C (see Section 10.1.2). Once enabled, the watchdog system
cannot be disabled by software (writing a `zero' to the WDOG bit has no effect at any time). In
addition, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a `1' to this
bit clears the counter to its initial value and prevents a watchdog timeout.
10 WDOG -- Watchdog enable/disable
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
1 (set) Watchdog enabled and counter cleared.
0 (clear) The watchdog cannot be disabled by software; writing a zero to this
bit has no effect.
The divide-by-7 watchdog counter will generate a main reset of the chip when it reaches its final
state; seven clocks are necessary to bring the watchdog counter from its clear state to its final
state. This reset appears after time tDOG since the last clear or since the enable of the watchdog
counter system. The watchdog counter, therefore, has to be cleared periodically, by software, with
a period less than tDOG.
The reset generated by the watchdog system is apparent at the RESET pin (see Figure 10-3). The
RESET pin level is re-entered in the control logic, and when it has been maintained at level `zero'
for a minimum of tDOGL, the RESET pin is released.
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10.1.4.1 COP watchdog during STOP mode
The STOP instruction is inhibited when the watchdog system is enabled. If a STOP instruction is
executed while the watchdog system is enabled, then a watchdog reset will occur as if there were
a watchdog timeout. In the case of a watchdog reset due to a STOP instruction, the oscillator will
not be affected, thus there will be no tPORL cycles start-up delay. On start-up, the watchdog will be
configured according to the user specified mask option.
10.1.4.2 COP watchdog during WAIT mode
The state of the watchdog during WAIT mode is selected via a mask option (see Section 1.2) to
be one of the options below:
Watchdog enabled -- the watchdog counter will continue to operate during WAIT mode and a reset
will occur after time tDOG.
Watchdog disabled -- on entering WAIT mode, the watchdog counter system is reset and
disabled. On exiting WAIT mode the counter resumes normal operation.
10.1.5 Functions affected by reset
When processing stops within the MCU for any reason, i.e. power-on reset, external reset or the
execution of a STOP or WAIT instruction, various internal functions of the MCU are affected.
Table 10-1 shows the resulting action of any type of system reset, but not necessarily in the order
in which they occur.
Note: Reset action on individual MCAN registers is described in Section 5 and is also
summarised in Table 3-2.
10
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Table 10-1 Effect of RESET, POR, STOP and WAIT
Function/effect RESET POR WAIT STOP
Timer prescaler cleared x x
Timer counter set to $FFFC x x
All timer enable bits cleared (disable) x x
Data direction registers cleared (inputs) x x
Stack pointer set to $00FF x x
Internal address bus forced to restart x x
Vector $3FFE, $3FFF x x
Interrupt mask bit (I-bit CCR) set x x
Interrupt mask bit (I-bit CCR) cleared x x
Interrupt enable bit (INTE) set x x
POR bit in miscellaneous register set x
STOP latch reset x x
IRQ latch reset x x
WAIT latch reset x x
SCI disabled x x
SCI status bits cleared (except TDRE
and TC) x x
SCI interrupt enable bits cleared
SCI status bits TDRE and TC set x x
Oscillator disabled for 4064 cycles
Timer clock cleared x x
SCI clock cleared
A/D disabled x x
SM bit in the miscellaneous register
cleared x x
Watchdog counter reset
WDOG bit in the miscellaneous register x x
reset
EEPROM control bits set or cleared (as x x x
per Section 3.5.1)
x x x
10 x x x x
x x x
x x x
x = Described action takes place
= Described action does not take
place
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10.2 Interrupts
The MCU can be interrupted by five different sources: three maskable hardware interrupts, one
non maskable software interrupt and one maskable MCAN interrupt:
External signal on the IRQ pin, WOI on port B pins or NWOI pin
Serial communications interface (SCI)
Programmable timer
Software interrupt instruction (SWI)
MCAN interrupt (CIRQ)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. The RTI instruction (return from interrupt) causes the
register contents to be recovered from the stack and normal processing to resume. While
executing the RTI instruction, the value of the I-bit is replaced by the corresponding I-bit stored on
the stack.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (I-bit clear) and the
corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
Note: Power-on and external reset clear all interrupt enable bits to prevent interrupts during
the reset sequence, but set the INTE bit (see Section 3.8).
10
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Reset
Is I-bit set?
NO
IRQ or WOI YES Clear IRQ
request latch
external interrupt?
NO
Timer YES Stack
PC, X, A, CC
internal interrupt?
NO
SCI YES Set I-bit
internal interrupt?
NO
CIRQ YES Load PC from:
10 MCAN interrupt? IRQ: $3FFA-$3FFB
Timer IC: $3FF8-$3FF9
NO Timer OC: $3FF6-$3FF7
Timer OVF:$3FF4-$3FF5
SCI: $3FF2-$3FF3
Fetch next MCAN: $3FF0-$3FF1
instruction
Execute Complete interrupt
instruction routine and execute
RTI
Figure 10-4 Interrupt flow chart
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10.2.1 Interrupt priorities
Each potential interrupt source is assigned a priority level, which means that if more than one
interrupt is pending at the same time, the processor will service the one with the highest priority
first. For example, if both an external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced first.
Table 10-2 shows the relative priority of all the possible interrupt sources. Figure 10-4 shows the
interrupt processing flow.
Table 10-2 Interrupt priorities
Source Register Flags Vector address Priority
-- $3FFE, $3FFF highest
Reset -- -- $3FFC, $3FFD
-- $3FFA, $3FFB
Software interrupt (SWI) -- $3FF8, $3FF9
ICF1, ICF2 $3FF6, $3FF7
External interrupt (IRQ) or WOI -- OCF1, OCF2 $3FF4, $3FF5
Timer input captures TSR TOF $3FF2, $3FF3
TDRE, TC,
Timer output compares TSR OR, RDRF, $3FF0, $3FF1 lowest
Timer overflow TSR IDLE
WIF,OIF,EIF,
Serial communications SCSR
interface (SCI) TIF, RIF
MCAN CINT
10.2.2 Nonmaskable software interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is 10
executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specified by the
contents of memory locations $3FFC and $3FFD.
10.2.3 Maskable hardware interrupts
If the interrupt mask bit in the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur.
Note: The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit
is cleared.
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10.2.3.1 Miscellaneous register
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State
on reset
Miscellaneous $000C POR INTP INTN INTE SFA SFB SM WDOG u001 000u
Note: The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
INTP, INTN -- External interrupt sensitivity options
These two bits allow the user to select which edge the IRQ and WOI pins are sensitive to as shown
in Table 10-3. Both bits can be written to only while the I-bit is set, and are cleared by power-on or
external reset. Therefore the device is initialised with negative edge and low level sensitivity.
Table 10-3 IRQ and WOI sensitivity
INTP INTN IRQ sensitivity WOI interrupt sensitivity
0 Positive edge and high level
0 0 Negative edge and low level sensitive
1 sensitive Positive edge only
1 Negative edge only
1 Negative edge only Positive and negative edge
sensitive
0 Positive edge only
1 Positive and negative edge
sensitive
10 Interrupt sensitivity options selected by INTP and INTN of the miscellaneous register apply to
external interrupt signal, EI. EI is an OR function of all enabled WOI pins (port B and NWOI) and
of the inverted value of the IRQ pin. When one WOI pin is high, it masks any subsequent edge or
level on any other EI pin (IRQ, port B or NWOI).
INTE -- External interrupt enable
1 (set) External interrupt (IRQ) and wired-OR interrupt (WOI) enabled.
0 (clear) External interrupt (IRQ) and wired-OR interrupt (WOI) disabled.
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
Table 10-3 describes the various triggering options available for the IRQ and WOI pins, however it
is important to re-emphasize here that in order to avoid any conflict and spurious interrupt, it is
possible to change the external interrupt options only while the I-bit is set. Any attempt to change
the external interrupt option while the I-bit is clear will be unsuccessful. If an external interrupt is
pending, it will automatically be cleared when selecting a different interrupt option.
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Note: If the external interrupt function is disabled by the INTE bit and an external interrupt is
sensed by the edge detector circuitry, then the interrupt request is latched and the
interrupt stays pending until the INTE bit is set. The internal latch of the external
interrupt is cleared in the first part of the service routine (except for the low level
interrupt which is not latched); therefore, only one external interrupt pulse can be
latched during tILIL and serviced as soon as the I-bit is cleared.
10.2.3.2 External interrupts
IRQ interrupt
If the interrupt mask in the condition code register has been cleared and the interrupt enable bit
(INTE) is set and the signal on the external interrupt pin (IRQ) satisfies the condition selected by
the option control bits (INTP and INTN), then the external interrupt is recognized. INTE, INTP and
INTN are all bits contained in the miscellaneous register at $000C. When the interrupt is
recognized, the current state of the CPU is pushed onto the stack and the I-bit is set. This masks
further interrupts until the present one is serviced. The external interrupt service routine address
is specified by the content of memory locations $3FFA and $3FFB.
Wired-OR interrupt (WOI) 10
An external WOI capability is provided on all port B I/O pins when they are programmed as inputs,
and on the NWOI pin. A WOI is activated only if WOIE in the EEPROM control register is set and
if wired-OR interrupts have been chosen as an option on the device (see Section 1.2). If wired-OR
interrupts are enabled on a given input pin (NWOI pin or port B pins; refer to Section 2.3.19 and
Section 4.2), an external interrupt is requested when this pin is pulled high. The request is serviced
by the interrupt routine whose start address is contained in memory locations $3FFA and $3FFB.
External and power-on reset clear the WOIE bit. A WOI interrupt will cause the MCU to exit STOP
mode.
The interrupt enable bit (INTE) in the miscellaneous register enables both wired-OR interrupts and
the IRQ interrupt. IRQ and WOI are internally OR-ed before interrupt sensitivity selection (see
Section 10.2.3.1).
10.2.3.3 MCAN interrupt (CIRQ)
Several sources can trigger a CIRQ. The MCAN interrupt register at $0023 is used to identify the
source. Each CIRQ source can be individually enabled (except the wake-up interrupt, which is
always enabled) by different bits of the MCAN control register at $0020.
The CIRQ sources are (also see Section 5.3.4):
Receive IRQ: this signals successful reception of a complete message.
Transmit IRQ: this signals successful transmission of a complete message.
MC68HC05X16 RESETS AND INTERRUPTS MOTOROLA
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Error IRQ: this is set when either the error status or bus status bits in the MCAN status register
change state (see Section 5.3.3).
Data overrun: an incoming message on the bus cannot be received because both receive buffers
are tied up.
Wake-up IRQ: this signals activity on the bus while the MCAN is in SLEEP mode. This is the only
nonmaskable CIRQ.
CIRQ interrupts are serviced by the routine located at the address specified by the contents of
$3FF0 and $3FF1.
10.2.3.4 Timer interrupts
There are five different timer interrupt flags (ICF1, ICF2, OCF1, OCF2 and TOF) that will cause a
timer interrupt whenever they are set and enabled. These five interrupt flags are found in the five
most significant bits of the timer status register (TSR) at location $0013. ICF1 and ICF2 will vector
to the service routine defined by $3FF8-$3FF9, OCF1 and OCF2 will vector to the service routine
defined by $3FF6$3FF7 and TOF will vector to the service routine defined by $3FF4$3FF5 as
shown in Figure 6-1.
There are three corresponding enable bits; ICIE for ICF1 and ICF2, OCIE for OCF1 and OCF2,
and TOIE for TOF. These enable bits are located in the timer control register (TCR) at address
$0012. See Section 6.2.1 and Section 6.2.2 for further information.
10.2.3.5 Serial communications interface (SCI) interrupts
10 There are five different interrupt flags (TDRE, TC, OR, RDRF and IDLE) that cause SCI interrupts
whenever they are set and enabled. These five interrupt flags are found in the five most significant
bits of the SCI status register (SCSR) at location $0010.
There are four corresponding enable bits: TIE for TDRE, TCIE for TC, RIE for OR and RDRF, and
ILIE for IDLE. These enable bits are located in the serial communications control register 2
(SCCR2) at address $000F. See Section 7.11.3 and Section 7.11.4.
The SCI interrupt causes the program counter to vector to the address pointed to by memory
locations $3FF2 and $3FF3 which contain the starting address of the interrupt service routine.
Software in the SCI interrupt service routine must determine the priority and cause of the interrupt
by examining the interrupt flags and the status bits located in the serial communications status
register SCSR (address $0010).
The general sequence for clearing an interrupt is a software sequence of accessing the serial
communications status register while the flag is set followed by a read or write of an associated
register. Refer to Section 7 for a description of the SCI system and its interrupts.
MOTOROLA RESETS AND INTERRUPTS MC68HC05X16
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10.2.4 Hardware controlled interrupt sequence
The following three functions: reset, STOP and WAIT, are not in the strictest sense interrupts. However,
they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in Figure 2-4.
RESET: A reset condition causes the program to vector to its starting address, which is contained
in memory locations $3FFE (MSB) and $3FFF (LSB). The I-bit in the condition code
register is also set, to disable interrupts.
STOP: The STOP instruction puts the processor to `sleep' and, if the MCAN module is already
in SLEEP mode, it causes the oscillator to be turned off until an external, WOI or CIRQ
interrupt occurs or the device is reset.
WAIT: The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks
running. This `rest' state of the processor can be cleared by reset, an external or WOI
interrupt, a timer interrupt or an SCI interrupt. There are no special WAIT vectors for
these individual interrupts.
10
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THIS PAGE LEFT BLANK INTENTIONALLY
10
MOTOROLA RESETS AND INTERRUPTS MC68HC05X16
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11
CPU CORE AND INSTRUCTION SET
This section provides a description of the CPU core registers, the instruction set and the
addressing modes of the MC68HC05X16.
11.1 Registers
The MCU contains five registers, as shown in the programming model of Figure 11-1. The interrupt
stacking order is shown in Figure 11-2.
7 0
7 0 Accumulator
15 7 0 Index register
00 Program counter
15 7 0 Stack pointer
0000000011 Condition code register
7 0 Carry / borrow
Zero
1 1 1H I NZC Negative
Interrupt mask
Half carry 11
Figure 11-1 Programming model
11.1.1 Accumulator (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic
calculations or data manipulations.
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7 0 Stack
Condition code register
Increasing Decreasing
memory Accumulator memory
address Index register address
Program counter high
Unstack Program counter low
Return
Interrupt
Figure 11-2 Stacking order
11.1.2 Index register (X)
The index register is an 8-bit register, which can contain the indexed addressing value used to
create an effective address. The index register may also be used as a temporary storage area.
11.1.3 Program counter (PC)
The program counter is a 16-bit register, which contains the address of the next byte to be fetched.
Although the M68HC05 CPU core can address 64K bytes of memory, the actual address range of
the MC68HC05X32 is limited to 16K bytes. The two most significant bits of the program counter
are therefore not used and are permanently set to zero.
11.1.4 Stack pointer (SP)
11 The stack pointer is a 16-bit register, which contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to
location $00FF. The stack pointer is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the ten most significant bits are permanently set to 0000000011. These
ten bits are appended to the six least significant register bits to produce an address within the
range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64
locations are exceeded, the stack pointer wraps around and overwrites the previously stored
information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
11.1.5 Condition code register (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just
executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually
tested by a program, and specific actions can be taken as a result of their state. Each bit is
explained in the following paragraphs.
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Half carry (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
Interrupt (I)
When this bit is set, all maskable interrupts are masked. If an interrupt occurs while this bit is set,
the interrupt is latched and remains pending until the interrupt bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
zero.
Carry/borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred
during the last arithmetic operation. This bit is also affected during bit test and branch instructions
and during shifts and rotates.
11.2 Instruction set
The MCU has a set of 62 basic instructions. They can be grouped into five different types as 11
follows:
Register/memory
Read/modify/write
Branch
Bit manipulation
Control
The following paragraphs briefly explain each type. All the instructions within a given type are
presented in individual tables.
This MCU uses all the instructions available in the M146805 CMOS family plus one more: the
unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents
of the accumulator (A) and the index register (X). The high-order product is then stored in the index
register and the low-order product is stored in the accumulator. A detailed definition of the MUL
instruction is shown in Table 11-1.
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11.2.1 Register/memory Instructions
Most of these instructions use two operands. The first operand is either the accumulator or the
index register. The second operand is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand.
Refer to Table 11-2 for a complete list of register/memory instructions.
11.2.2 Branch instructions
These instructions cause the program to branch if a particular condition is met; otherwise, no
operation is performed. Branch instructions are two-byte instructions. Refer to Table 11-3.
11.2.3 Bit manipulation instructions
The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space
(page 0). All port data and data direction registers, timer and serial interface registers,
control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature
allows the software to test and branch on the state of any bit within these locations. The bit set, bit
clear, bit test and branch functions are all implemented with single instructions. For the test and
branch instructions, the value of the bit tested is also placed in the carry bit of the condition code
register. Refer to Table 11-4.
11.2.4 Read/modify/write instructions
11 These instructions read a memory location or a register, modify or test its contents, and write the
modified value back to memory or to the register. The test for negative or zero (TST) instruction is
an exception to this sequence of reading, modifying and writing, since it does not modify the value.
Refer to Table 11-5 for a complete list of read/modify/write instructions.
11.2.5 Control instructions
These instructions are register reference instructions and are used to control processor operation
during program execution. Refer to Table 11-6 for a complete list of control instructions.
11.2.6 Tables
Tables for all the instruction types listed above follow. In addition there is a complete alphabetical
listing of all the instructions (see Table 11-7), and an opcode map for the instruction set of the
M68HC05 MCU family (see Table 11-8).
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Table 11-1 MUL instruction
Operation X:A X*A
Description
Multiplies the eight bits in the index register by the eight
Condition bits in the accumulator and places the 16-bit result in the
codes concatenated accumulator and index register.
Source H : Cleared
Form I : Not affected
N : Not affected
Z : Not affected
C : Cleared
MUL
Addressing mode Cycles Bytes Opcode
Inherent 11 1 $42
Table 11-2 Register/memory instructions
Addressing modes
Immediate Direct Extended Indexed Indexed Indexed
(no (8-bit (16-bit
offset) offset)
offset)
Function Mnemonic
Opcode
Load A from memory # Bytes
Load X from memory # Cycles
Store A in memory Opcode
Store X in memory # Bytes
Add memory to A # Cycles
Add memory and carry to A Opcode
Subtract memory # Bytes
Subtract memory from A # Cycles
with borrow Opcode
AND memory with A # Bytes
OR memory with A # Cycles
Exclusive OR memory with A Opcode
Arithmetic compare A # Bytes
with memory # Cycles
Arithmetic compare X Opcode
with memory # Bytes
Bit test memory with A # Cycles
(logical compare)
Jump unconditional LDA A6 2 2 B6 2 3 C6 3 4 F6 1 3 E6 2 4 D6 3 5
Jump to subroutine
LDX AE 2 2 BE 2 3 CE 3 4 FE 1 3 EE 2 4 DE 3 5
STA B7 2 4 C7 3 5 F7 1 4 E7 2 5 D7 3 6
STX BF 2 4 CF 3 5 FF 1 4 EF 2 5 DF 3 6
ADD AB 2 2 BB 2 3 CB 3 4 FB 1 3 EB 2 4 DB 3 5
ADC A9 2 2 B9 2 3 C9 3 4 F9 1 3 E9 2 4 D9 3 5
SUB A0 2 2 B0 2 3 C0 3 4 F0 1 3 E0 2 4 D0 3 5
SBC A2 2 2 B2 2 3 C2 3 4 F2 1 3 E2 2 4 D2 3 5
AND A4 2 2 B4 2 3 C4 3 4 F4 1 3 E4 2 4 D4 3 5 11
ORA AA 2 2 BA 2 3 CA 3 4 FA 1 3 EA 2 4 DA 3 5
EOR A8 2 2 B8 2 3 C8 3 4 F8 1 3 E8 2 4 D8 3 5
CMP A1 2 2 B1 2 3 C1 3 4 F1 1 3 E1 2 4 D1 3 5
CPX A3 2 2 B3 2 3 C3 3 4 F3 1 3 E3 2 4 D3 3 5
BIT A5 2 2 B5 2 3 C5 3 4 F5 1 3 E5 2 4 D5 3 5
JMP BC 2 2 CC 3 3 FC 1 2 EC 2 3 DC 3 4
JSR BD 2 5 CD 3 6 FD 1 5 ED 2 6 DD 3 7
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Table 11-3 Branch instructions
Relative addressing mode
Function Mnemonic Opcode # Bytes # Cycles
Branch always BRA
Branch never BRN 20 2 3
Branch if higher BHI
Branch if lower or same BLS 21 2 3
Branch if carry clear BCC
(Branch if higher or same) (BHS) 22 2 3
Branch if carry set BCS
(Branch if lower) (BLO) 23 2 3
Branch if not equal BNE
Branch if equal BEQ 24 2 3
Branch if half carry clear BHCC
Branch if half carry set BHCS 24 2 3
Branch if plus BPL
Branch if minus BMI 25 2 3
Branch if interrupt mask bit is clear BMC
Branch if interrupt mask bit is set BMS 25 2 3
Branch if interrupt line is low BIL
Branch if interrupt line is high BIH 26 2 3
Branch to subroutine BSR
27 2 3
28 2 3
29 2 3
2A 2 3
2B 2 3
2C 2 3
2D 2 3
2E 2 3
2F 2 3
AD 2 6
Table 11-4 Bit manipulation instructions
Addressing modes
Bit set/clear Bit test and branch
Function Mnemonic Opcode # Bytes # Cycles Opcode # Bytes # Cycles
Branch if bit n is set BRSET n (n=07)
Branch if bit n is clear BRCLR n (n=07) 2n 3 5
Set bit n BSET n (n=07)
11 Clear bit n BCLR n (n=07) 01+2n 3 5
10+2n 2 5
11+2n 2 5
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Table 11-5 Read/modify/write instructions
Addressing modes
Inherent Inherent Direct Indexed Indexed
(A) (X) (no (8-bit
offset)
offset)
Function Mnemonic Opcode
# Bytes
# Cycles
Opcode
# Bytes
# Cycles
Opcode
# Bytes
# Cycles
Opcode
# Bytes
# Cycles
Opcode
# Bytes
# Cycles
Increment INC 4C 1 3 5C 1 3 3C 2 5 7C 1 5 6C 2 6
Decrement DEC 4A 1 3 5A 1 3 3A 2 5 7A 1 5 6A 2 6
Clear CLR 4F 1 3 5F 1 3 3F 2 5 7F 1 5 6F 2 6
Complement COM 43 1 3 53 1 3 33 2 5 73 1 5 63 2 6
Negate (two's complement) NEG 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6
Rotate left through carry ROL 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6
Rotate right through carry ROR 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6
Logical shift left LSL 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6
Logical shift right LSR 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6
Arithmetic shift right ASR 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6
Test for negative or zero TST 4D 1 3 5D 1 3 3D 2 4 7D 1 4 6D 2 5
Multiply MUL 42 1 11
Set bit n BSET n (n=07) 10+2n 2 5
Clear bit n BCLR n (n=07) 11+2n 2 5
Table 11-6 Control instructions
Inherent addressing mode
Function Mnemonic Opcode # Bytes # Cycles
Transfer A to X TAX
Transfer X to A TXA 97 1 2
Set carry bit SEC
Clear carry bit CLC 9F 1 2
Set interrupt mask bit SEI
Clear interrupt mask bit CLI 99 1 2
Software interrupt SWI
Return from subroutine RTS 98 1 2 11
Return from interrupt RTI
Reset stack pointer RSP 9B 1 2
No-operation NOP
Stop STOP 9A 1 2
Wait WAIT
83 1 10
81 1 6
80 1 9
9C 1 2
9D 1 2
8E 1 2
8F 1 2
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Table 11-7 Instruction set
Mnemonic Addressing modes Condition codes
INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H I N Z C
ADC
11 ADD
AND
ASL
ASR
BCC
BCLR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
CLI 0
CLR 0
CMP 01
Condition code symbols
Address mode abbreviations Tested and set if true,
cleared otherwise
BS H Half carry (from bit 3)
C
Bit set/clear IMM Immediate
I Interrupt mask Not affected
BTB Bit test & branch IX Indexed (no offset) N Negate (sign bit) ? Load CCR from stack
DIR Direct IX1 Indexed, 1 byte offset Z Zero 0 Cleared
EXT Extended IX2 Indexed, 2 byte offset C Carry/borrow 1 Set
Not implemented
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Table 11-7 Instruction set (Continued)
Mnemonic Addressing modes Condition codes
INH IMM DIR EXT REL IX IX1 IX2 BSC BTB H I N Z C
COM
CPX 1 11
DEC
EOR
INC
JMP
JSR
LDA
LDX
LSL
LSR
MUL 0
NEG 0 0
NOP
ORA
ROL
ROR
RSP
RTI
RTS ?????
SBC
SEC
SEI 1
STA 1
STOP
STX 0
SUB
SWI
TAX 1
TST
TXA
WAIT
0
Condition code symbols
Address mode abbreviations Tested and set if true,
cleared otherwise
BS H Half carry (from bit 3)
C
Bit set/clear IMM Immediate
I Interrupt mask Not affected
BTB Bit test & branch IX Indexed (no offset) N Negate (sign bit) ? Load CCR from stack
DIR Direct IX1 Indexed, 1 byte offset Z Zero 0 Cleared
EXT Extended IX2 Indexed, 2 byte offset C Carry/borrow 1 Set
Not implemented
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11
MOTOROLA Bit manipulation Branch Read/modify/write Control Register/memory
11-10
BTB BSC REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX
7
High 0 1 2 3 4 5 6 0111 8 9 A B C D E F High
1010
Low 0000 0001 0010 0011 0100 0101 0110 5 1000 1001 1011 1100 1101 1110 1111 Low
2
0 5 5 3 5 3 3 6 NEG 9 3 4 5 4 3 0
0000 BRSET0 BSET0 NEG NEGA NEGX NEG SUB 0000
BRA IX 1 RTI SUB SUB SUB SUB SUB
1 IMM 2 1
0001 3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 1 INH 2 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0001
2 5 5 3 5 6 CMP 3 4 5 4 3 2
0010 BRCLR0 BCLR0 0010
BRN COM RTS IMM 2 CMP CMP CMP CMP CMP
3 2 3
0011 3 BTB 2 BSC 2 REL IX 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0011
5 SBC
4 5 5 3 11 3 4 5 4 3 4
0100 BRSET1 BSET1 LSR IMM 2 0100
BHI MUL 2 SBC SBC SBC SBC SBC
5 IX 5
0101 3 BTB 2 BSC 2 REL 1 INH 2 CPX DIR 3 EXT 3 IX2 2 IX1 1 IX 0101
5
6 5 5 3 5 3 3 6 10 IMM 2 3 4 5 4 3 6
0110 BRCLR1 BCLR1 COM COMA COMX ROR 2 0110
BLS COM SWI CPX CPX CPX CPX CPX
7 IX AND 7
0111 3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 5 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 0111
IMM 2
8 5 5 3 5 3 3 6 ASR 2 3 4 5 4 3 8
1000 BRSET2 BSET2 LSR LSRA LSRX 1000
CPU CORE AND INSTRUCTION SET BCC LSR IX BIT AND AND AND AND AND
9 3 BTB 2 BSC 2 DIR 1 INH 1 INH 2 5 2 9 Table 11-8 M68HC05 opcode map
1001 REL 2 IX1 1 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 1001
LSL 2
A 5 5 3 3 4 5 4 3 A
1010 BRCLR2 BCLR2 IX LDA 1010
BCS 5 BIT BIT BIT BIT BIT
B 3 BTB 2 BSC 2 2 IMM 2 B
1011 REL ROL DIR 3 EXT 3 IX2 2 IX1 1 IX 1011
5 5 5 3 3 6 2
C BRSET3 BSET3 3 IX 2 3 4 5 4 3 C
1100 ROR RORA RORX ROR 5 1100
3 BTB 2 BSC 2 BNE 2 EOR LDA LDA LDA LDA LDA
D DIR 1 INH 1 INH 2 IX1 1 DEC 2 D
1101 5 5 REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 1101
BRCLR3 BCLR3 5 3 3 6 IX TAX 2
E 3 4 5 6 5 4 E
1110 3 BTB 2 BSC 2 ASR ASRA ASRX ASR 5 1 INH ADC 1110
BEQ 2 STA STA STA STA STA
F 5 5 DIR 1 INH 1 INH 2 IX1 1 INC 1 IMM 2 F
1111 BRSET4 BSET4 REL 2 CLC 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 1111
5 3 3 6 IX 1
3 BTB 2 BSC 2 3 4 INH 2 ORA 3 4 5 4 3
LSL LSLA LSLX LSL 1 2
5 5 BHCC TST IMM 2 EOR EOR EOR EOR EOR
BRCLR4 BCLR4 DIR 1 INH 1 INH 2 IX1 1 1 SEC 2
REL 2 IX DIR 3 EXT 3 IX2 2 IX1 1 IX
3 BTB 2 BSC 2 5 3 3 6 1 INH 2 ADD
3 1 2 3 4 5 4 3
5 5 ROL ROLA ROLX
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