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EBWT41-A

器件型号:EBWT41-A
器件类别:未分类   
厂商名称:Blue Giga
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EVAL KIT BLUETOOTH WT41LONG RANGE

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EBWT41-A器件文档内容

WT41-A / WT41-N

PRELIMINARY DATA SHEET

Monday, 04 October 2010
Version 0.7
Copyright 2000-2010 Bluegiga Technologies

All rights reserved.
Bluegiga Technologies assumes no responsibility for any errors which may appear in this manual.
Furthermore, Bluegiga Technologies reserves the right to alter the hardware, software, and/or specifications
detailed here at any time without notice and does not make any commitment to update the information
contained here. Bluegiga's products are not authorized for use as critical components in life support devices
or systems.
The WRAP is a registered trademark of Bluegiga Technologies
The Bluetooth trademark is owned by the Bluetooth SIG Inc., USA and is licensed to Bluegiga Technologies.
All other trademarks listed herein are owned by their respective owners.

                                                        Bluegiga Technologies Oy
VERSION HISTORY  Comment
Version
                 First draft
0.1             Description and product codes added
0.2             Dimensions updated, layout guide added, UART and USB chapters added
0.21            Pin descriptions, PCM, USB, UART, SPI
0.22            Physical dimensions corrected
0.3             Product codes corrected
0.31            Recommendation for a power-up reset circuitry added to chapter 10
0.32            Pins 1 and 52 (GND) removed. Dimensions updated, recommended land
0.4             pattern added
0.5             Certification information added
0.6             Physical dimensions and recommended PCB land pattern updated
0.7             Figure 5 recommended land pattern corrected

                 Bluegiga Technologies Oy
TABLE OF CONTENTS

WT41 ....................................................................................................................................................................1

PRELIMINARY Data Sheet ..................................................................................................................................1

1 Ordering Information......................................................................................................................................7

2 Pinout and Terminal Description ...................................................................................................................8

3 Electrical Characteristics ............................................................................................................................ 11

3.1 Absolute Maximum Ratings ................................................................................................................ 11

3.2 Recommended Operating Conditions ................................................................................................. 11

4 Physical Dimensions .................................................................................................................................. 12

5 Layout Guidelines....................................................................................................................................... 15

5.1 WT41-A ............................................................................................................................................... 15

6 UART Interface........................................................................................................................................... 16

6.1 UART Bypass...................................................................................................................................... 18

6.2 UART Configuration While Reset is Active ......................................................................................... 18

6.3 UART Bypass Mode............................................................................................................................ 18

7 USB Interface ............................................................................................................................................. 19

7.1 USB Data Connections ....................................................................................................................... 19

7.2 USB Pull-Up resistor ........................................................................................................................... 19

7.3 USB Power Supply.............................................................................................................................. 19

7.4 Self-Powered Mode............................................................................................................................. 19

7.5 Bus-Powered Mode............................................................................................................................. 20

7.6 USB Suspend Current......................................................................................................................... 21

7.7 USB Detach and Wake-Up Signaling.................................................................................................. 21

7.8 USB Driver .......................................................................................................................................... 22

7.9 USB v2.0 Compliance and Compatibility ............................................................................................ 22

8 Serial Peripheral Interface (SPI)................................................................................................................. 23

9 PCM Codec Interface ................................................................................................................................. 24

9.1 PCM Interface Master/Slave ............................................................................................................... 24

9.2 Long Frame Sync ................................................................................................................................ 25

9.3 Short Frame Sync ............................................................................................................................... 25

9.4 Multi-slot Operation ............................................................................................................................. 26

9.5 GCI Interface ....................................................................................................................................... 26

9.6 Slots and Sample Formats.................................................................................................................. 27

9.7 Additional Features ............................................................................................................................. 28

9.8 PCM_CLK and PCM_SYNC Generation ............................................................................................ 28

9.9 PCM Configuration .............................................................................................................................. 29

10 I/O Parallel Ports..................................................................................................................................... 31

10.1  PIO Defaults................................................................................................................................. 31

                   Bluegiga Technologies Oy
11 Reset....................................................................................................................................................... 32

11.1  Pin States on Reset ..................................................................................................................... 33

12 Certifications ........................................................................................................................................... 34

12.1  Bluetooth ...................................................................................................................................... 34

12.2  FCC .............................................................................................................................................. 34

12.3  CE ................................................................................................................................................ 35

12.4  Industry Canada (IC).................................................................................................................... 35

12.5  Qualified Antenna Types for WT41-N.......................................................................................... 35

13 Contact Information................................................................................................................................. 36

      Bluegiga Technologies Oy
WT41 Bluetooth Module

DESCRIPTION                                            FEATURES:

WT41 is a class 1, Bluetooth 2.1 + EDR module. It      Fully Qualified Bluetooth v2.1 + EDR end
introduces three times faster data rates compared            product, CE and FCC and IC
to existing Bluetooth 1.2 modules even with lower
power consumption! WT41 is a highly integrated          TX power : 18 dBm
and sophisticated Bluetooth module, containing all    RX sensitivity : -90 dBm
the necessary elements from Bluetooth radio to         Higly efficient chip antenna, U.FL connector or
antenna and a fully implemented protocol stack.
Therefore WT41 provides an ideal solution for                RF pin
developers who want to integrate Bluetooth             Class 1, range up to 800 meters
wireless technology into their design with limited      Industrial temperature range from -40oC to
knowledge of Bluetooth and RF technologies.
WT41 is optimized for long range applications and            +85oC
since it contains a RF power amplifier, low noise       RoHS Compliant
amplifier and a highly efficient chip antenna.          USB interface (USB 2.0 compatible)
                                                       UART with bypass mode
By default WT41 module is equipped with powerful       6 x GPIO
and easy-to-use iWRAP firmware. iWRAP enables          1 x 8-bit AIO
users to access Bluetooth functionality with simple    Support for 802.11 Coexistence
ASCII commands delivered to the module over             Integrated iWRAPTM Bluetooth stack or HCI
serial interface - it's just like a Bluetooth modem.
                                                             firmware
APPLICATIONS:

    Hand held terminals
    Industrial devices
    Point-of-Sale systems
    PCs
    Personal Digital Assistants (PDAs)
    Computer Accessories
    Access Points
    Automotive Diagnostics Units

Bluegiga Technologies Oy
1 Ordering Information

        WT41-A-HCI

                    Firmware          HCI firmware (Bluetooth 2.0 + EDR)
                              HCI =   HCI firmware (Bluetooth 2.1 + EDR)
                              HCI21=  HCI firmware (Bluetooth 3.0)
                              HCI30=  iWRAP 2.2.0
                              AI =    iWRAP 3.0.0
                              AI3 =   iWRAP 4.0.0
                              AI4 =

                    HW version        Chip antenna
                              A=      U.FL connector
                              E=      RF pin
                              N=

                    Product series

*) TBD

                        Bluegiga Technologies Oy

                                                                          Page 7 of 36
2       Pinout and Terminal Description

                           59     57     GND 5554
                              58     56           53

                           GND     GND           GND                Pins 1 and 52 (GND)
                              GND     GND           GND             are not connected
                                                                    and have been
                   2  GND                                RF     51  removed
                   3  GND                             RFGND     50
                   4  GND
                   5  GND                                  GND  49
                                                           GND  48
                   6 GND
                   7 GND                                        47
             8                                             GND  46
             9        GND                                  GND  45
            10        GND                                  GND  44
                      GND                                  GND
            11 VDD_PA                                      AIO 43
            12                                                  42
            13        PIO2                         UART_TX      41
            14        PIO3                               PIO5   40
            15        UART_RTS
            16        UART_RX                      SPI_MOSI
                      GND                          SPI_MISO 39
                                                                38
            17        USB+                         SPI_CLK      37
            18        USB-                         SPI_CSB
            19        UART_CTS                                  36
                                                        GND     35
                                                        PIO7
            20 PCM_IN                                           34
            21 PCM_CLK                                   PIO6   33
            22                                        RESET
            23        PCM_SYNC                                  32
                      GND                                VDD    31
                                                         GND
                           GND
                              PCM_OUT27 GND28 GND  PIO 4
                                 GND                  GND

                           24                    29
                              25                    30
                                 26

                                   Figure 1: WT41 pin out

            PIN            PAD TYPE                                 DESCRIPTION
        NUMBER
NC                         Not connected                            Pins 1 and 52 (GND) have been removed
RESET       1, 52                                                   from the module.

GND          33       Input, weak internal pull- Active low reset. Keep low for >5 ms
        2-10, 16,
RF      23,24,26-                      up                           to cause a reset
RFGND
VDD_PA    28, 30,                  GND                              GND
        31,36,44-
        49, 53-59

        51                 RF output                                RF output for WT41-N. For WT41-A
                                                                    and WT41-E this pin is not connected

        50                         GND                              RF ground. Connected to GND internally to
                                                                    the module.

        11                 Supply voltage                           Supply voltage for the RF power amplifier
                                                                    and the low noise amplifier of the module

                      Table 1: Supply and RF Terminal Descriptions

                           Bluegiga Technologies Oy

                                                                                         Page 8 of 36
PIO PORT      PIN  PAD TYPE                            DESCRIPTION
          NUMBER

PIO[2]      12        Bi-directional, programmamble Programmamble input/output
PIO[3]             strength internal pull-down/pull-up line
PIO[4]
PIO[5]      13        Bi-directional, programmamble Programmamble input/output
PIO[6]             strength internal pull-down/pull-up line
PIO[7]
AIO[1]      29        Bi-directional, programmamble Programmamble input/output
                   strength internal pull-down/pull-up line
SPI
INTERFACE   41        Bi-directional, programmamble Programmamble input/output
PCM_OUT            strength internal pull-down/pull-up line
PCM_IN
PCM_SYNC    34        Bi-directional, programmamble Programmamble input/output
PCM_CLK            strength internal pull-down/pull-up line

            35        Bi-directional, programmamble Programmamble input/output
                   strength internal pull-down/pull-up line

            43               Bi-directional            Programmamble analog
                                                       input/output line

                            Table 2: GPIO Terminal Descriptions

            PIN             PAD TYPE                 DESCRIPTION
            NUMBER
                            CMOS output, tri-state,  Synchronous data output
                    25      weak internal pull-down

                   20        CMOS input, weak        Synchronous data input
                             internal pull-down

                   22        Bi-directional, weak    Synchronous data sync
                              internal pull-down

                   21        Bi-directional, weak    Synchronous data clock
                              internal pull-down

                            Table 3: PCM Terminal Descriptions

UART            PIN         PAD TYPE         DESCRIPTION
Interfaces      NUMBER
UART_TX                     CMOS output, tri-
                        42   state, with weak UART data output, active high
UART_RTS#                     internal pull-up
                        14  CMOS output, tri-
UART_RX                      state, with weak UART request to send, active low
                        15    internal pull-up
UART_CTS#                    CMOS input, tri-
                        19   state, with weak UART data input, active high
                            internal pull-down
                             CMOS input, tri-
                             state, with weak UART clear to send, active low
                            internal pull-down

                            Table 4: UART Terminal Descriptions

                             Bluegiga Technologies Oy

                                                                                Page 9 of 36
USB Interfaces  PIN         PAD TYPE       DESCRIPTION
                NUMBER

USB+            17          Bidirectional  USB data plus with selectable internal 1.5k
                            Bidirectional  pull-up resistor
USB-            18                         USB data minus

                            Table 5: USB Terminal Descriptions

SPI             PIN         PAD TYPE                 DESCRIPTION
INTERFACE       NUMBER
SPI_MOSI                    CMOS input with weak     SPI data input
SPI_CS#                 40     internal pull-down
                        37                           Chip select for Serial Peripheral
SPI_CLK                     CMOS input with weak     Interface, active low
                        38       internal pull-up
SPI_MISO
                        39  CMOS input with weak     SPI clock
                               internal pull-down    SPI data output

                            CMOS output, tristate,
                            with weak internal pull

                                         down

                            Table 6: Terminal Descriptions

                            Bluegiga Technologies Oy

                                                                      Page 10 of 36
3  Electrical Characteristics

3.1 Absolute Maximum Ratings

Rating                                Min                       Max          Unit
Storage Temperature
                                      -40                               85   C
VDD_PA, VDD
                                      -0.4                              3.6  V

Other Terminal Voltages               VSS-0.4                   VDD+0.4      V

                             Table 7: Absolute Maximum Ratings

3.2 Recommended Operating Conditions

Rating                                Min                       Max          Unit
                                                                              C
Operating Temperature Range           -40                               85    V
VDD_PA, VDD *)
                                      3.0                               3.6

                         *) VDD_PA has an effect on the RF output power.

                             Table 8: Recommended Operating Conditions

                             Bluegiga Technologies Oy

                                                                                 Page 11 of 36
4 Physical Dimensions

Figure 2: Physical dimensions (top view)

Figure 3: Dimensions for the RF pin (top view)
            Bluegiga Technologies Oy

                                                Page 12 of 36
3.35 mm  25.3 mm                       5.65 mm
                35.3 mm                  14.0 mm

         Figure 4: Dimensions of WT41

         Bluegiga Technologies Oy

                                       Page 13 of 36
Figure 5: Recommended land pattern

Bluegiga Technologies Oy

                                    Page 14 of 36
5 Layout Guidelines

5.1 WT41-A

WT41-A should be mounted directly over a solid GND plane. The best performance can be achieved when
placing the module to the left corner or to a middle edge of the mother board, as shown in the figure below.
Components can be mounted directly under the module and the antenna. The antenna is extremely robust for
environment in close proximity to the antenna. Any dielectric material has minor effect on the resonant
frequency of the antenna. Metal objects with physical height less than 2 mm can be placed freely anywhere
around the module within the area of the mother board without significantly effecting on the radiation
characteristics. It is important to place the module to the edge of the mother board and not to place metal
objects in front of the antenna.

WT41-A                            WT41-A

        Figure 6: Recommended positions for WT41-A

        Bluegiga Technologies Oy

                                                    Page 15 of 36
6 UART Interface

This is a standard UART interface for communicating with other serial devices.WT41 UART interface provides
a simple mechanism for communicating with other serial devices using the RS232 protocol.
Four signals are used to implement the UART function. When WT41 is connected to another digital device,
UART_RX and UART_TX transfer data between the two devices. The remaining two signals, UART_CTS and
UART_RTS, can be used to implement RS232 hardware flow control where both are active low indicators. All
UART connections are implemented using CMOS technology and have signalling levels of 0V and VDD.
UART configuration parameters, such as data rate and packet format, are set using WT41 software.

Note:
In order to communicate with the UART at its maximum data rate using a standard PC, an accelerated serial
port adapter card is required for the PC.

                                                          Table 9: Possible UART Settings

The UART interface is capable of resetting WT41 upon reception of a break signal. A break is identified by a
continuous logic low (0V) on the UART_RX terminal, as shown in Figure XXX. If tBRK is longer than the
value, defined by PSKEY_HOST_IO_UART_RESET_TIMEOUT, (0x1a4), a reset will occur. This feature
allows a host to initialise the system to a known state. Also, WT41 can emit a break character that may be
used to wake the host.

                                                                  Figure 7: Break Signal

Table XXX shows a list of commonly used data rates and their associated values for
PSKEY_UART_BAUD_RATE (0x204). There is no requirement to use these standard values. Any data rate
within the supported range can be set in the PS Key according to the formula in Equation XXX

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                          Page 16 of 36
Equation 1: Data Rate

Table 10: Standard Data Rates

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                               Page 17 of 36
6.1 UART Bypass

                                                       Figure 8: UART Bypass Architecture

6.2 UART Configuration While Reset is Active

The UART interface for WT41 while the chip is being held in reset is tristate. This will allow the user to daisy
chain devices onto the physical UART bus. The constraint on this method is that any devices connected to
this bus must tristate when WT41 reset is de-asserted and the firmware begins to run.

6.3 UART Bypass Mode

Alternatively, for devices that do not tristate the UART bus, the UART bypass mode on BlueCore4-External
can be used. The default state of BlueCore4-External after reset is de-asserted; this is for the host UART bus
to be connected to the BlueCore4-External UART, thereby allowing communication to BlueCore4-External via
the UART. All UART bypass mode connections are implemented using CMOS technology and have signalling
levels of 0V and VDD.
In order to apply the UART bypass mode, a BCCMD command will be issued to BlueCore4-External. Upon
this issue, it will switch the bypass to PIO[7:4] as Figure XXX indicates. Once the bypass mode has been
invoked, WT41 will enter the Deep Sleep state indefinitely.
In order to re-establish communication with WT41, the chip must be reset so that the default configuration
takes effect.
It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass
mode is invoked. Therefore, it is not possible to have active Bluetooth links while operating the bypass mode.
The current consumption for a device in UART bypass mode is equal to the values quoted for a device in
standby mode.

                 Bluegiga Technologies Oy

                                           Page 18 of 36
7 USB Interface

This is a full speed (12Mbits/s) USB interface for communicating with other compatible digital devices. WT41
acts as a USB peripheral, responding to requests from a master host controller such as a PC.

The USB interface is capable of driving a USB cable directly. No external USB transceiver is required. The
device operates as a USB peripheral, responding to requests from a master host controller such as a PC.
Both the OHCI and the UHCI standards are supported. The set of USB endpoints implemented can behave as
specified in the USB section of the Bluetooth v2.1 + EDR specification or alternatively can appear as a set of
endpoints appropriate to USB audio devices such as speakers.

As USB is a master/slave oriented system (in common with other USB peripherals), WT41 only supports USB
Slave operation.

7.1 USB Data Connections

The USB data lines emerge as pins USB_DP and USB_DN. These terminals are connected to the internal
USB I/O buffers of the BlueCore4-External, therefore, have a low output impedance. To match the connection
to the characteristic impedance of the USB cable, resistors must be placed in series with USB_DP/USB_DN
and the cable.

7.2 USB Pull-Up resistor

WT41 features an internal USB pull-up resistor. This pulls the USB_DP pin weakly high when WT41 is ready
to enumerate. It signals to the PC that it is a full speed (12Mbits/s) USB device.

The USB internal pull-up is implemented as a current source, and is compliant with section 7.1.5 of the USB
specification v1.2. The internal pull-up pulls USB_DP high to at least 2.8V when loaded with a 15k 5% pull-
down resistor (in the hub/host) when VDD_PADS = 3.1V. This presents a Thevenin resistance to the host of
at least 900. Alternatively, an external 1.5k pull-up resistor can be placed between a PIO line and D+ on the
USB cable. The firmware must be alerted to which mode is used by setting PSKEY_USB_PIO_PULLUP
appropriately. The default setting uses the internal pull-up resistor.

7.3 USB Power Supply

The USB specification dictates that the minimum output high voltage for USB data lines is 2.8V. To safely
meet the USB specification, the voltage on the VDD supply terminal must be an absolute minimum of 3.1V.
Bluegiga recommends 3.3V for optimal USB signal quality.

7.4 Self-Powered Mode

In self-powered mode, the circuit is powered from its own power supply and not from the VBUS (5V) line of the
USB cable. It draws only a small leakage current (below 0.5mA) from VBUS on the USB cable. This is the
easier mode for which to design, as the design is not limited by the power that can be drawn from the USB
hub or root port. However, it requires that VBUS be connected to WT41 via a resistor network (Rvb1 and
Rvb2), so WT41 can detect when VBUS is powered up. BlueCore4-External will not pull USB_DP high when
VBUS is off.

Self-powered USB designs (powered from a battery or PSU) must ensure that a PIO line is allocated for USB
pullup purposes. A 1.5k 5% pull-up resistor between USB_DP and the selected PIO line should be fitted to the
design. Failure to fit this resistor may result in the design failing to be USB compliant in self-powered mode.
The internal pull-up in BlueCore is only suitable for bus-powered USB devices, e.g., dongles.

Bluegiga Technologies Oy

                          Page 19 of 36
                                             Figure 9: USB Connections for Self-Powered Mode

The terminal marked USB_ON can be any free PIO pin. The PIO pin selected must be registered by setting
PSKEY_USB_PIO_VBUS to the corresponding pin number.

Figure 10: USB Interface Component Values

7.5 Bus-Powered Mode

In bus-powered mode, the application circuit draws its current from the 5V VBUS supply on the USB cable.
WT41 negotiates with the PC during the USB enumeration stage about how much current it is allowed to
consume. On power-up the device must not draw more than 100 mA but after being configured it can draw up
to 500 mA.

For WT41, the USB power descriptor should be altered to reflect the amount of power required. This is
accomplished by setting PSKEY_USB_MAX_POWER (0x2c6). This is higher than for a Class 2 application
due to the extra current drawn by the Transmit RF PA. By default for WT41 the setting is 300 mA.

When selecting a regulator, be aware that VBUS may go as low as 4.4V. The inrush current (when charging
reservoir and supply decoupling capacitors) is limited by the USB specification. See the USB Specification.
Some applications may require soft start circuitry to limit inrush current if more than 10uF is present between
VBUS and GND. The 5V VBUS line emerging from a PC is often electrically noisy. As well as regulation down
to 3.3V and 1.8V, applications should include careful filtering of the 5V line to attenuate noise that is above the
voltage regulator bandwidth. Excessive noise on WT41 supply pins will result in reduced receiver sensitivity
and a distorted RF transmit signal.

                      Bluegiga Technologies Oy

                                                Page 20 of 36
                                            Figure 11: USB Connections for Bus-Powered Mode

7.6 USB Suspend Current

All USB devices must permit the USB controller to place them in a USB suspend mode. While in USB
Suspend, bus-powered devices must not draw more than 2.5mA from USB VBUS (self-powered devices may
draw more than 2.5mA from their own supply). This current draw requirement prevents operation of the radio
by bus-powered devices during USB Suspend.

When computing suspend current, the current from VBUS through the bus pull-up and pull-down resistors
must be included. The pull-up resistor at the device is 1.5 k. (nominal). The pull-down resistor at the hub is
14.25k. to 24.80k. The pull-up voltage is nominally 3.3V, which means that holding one of the signal lines high
takes approximately 200uA, leaving only 2.3mA available from a 2.5mA budget. Ensure that external LEDs
and/or amplifiers can be turned off by BlueCore4-External. The entire circuit must be able to enter the
suspend mode.

7.7 USB Detach and Wake-Up Signaling

WT41 can provide out-of-band signaling to a host controller by using the control lines called USB_DETACH
and USB_WAKE_UP. These are outside the USB specification (no wires exist for them inside the USB cable),
but can be useful when embedding WT41 into a circuit where no external USB is visible to the user. Both
control lines are shared with PIO pins and can be assigned to any PIO pin by setting
PSKEY_USB_PIO_DETACH and PSKEY_USB_PIO_WAKEUP to the selected PIO number.

USB_DETACH is an input which, when asserted high, causes WT41 to put USB_DN and USB_DP in high
impedance state and turns off the pull-up resistor on DP. This detaches the device from the bus and is
logically equivalent to unplugging the device. When USB_DETACH is taken low, WT41 will connect back to
USB and await enumeration by the USB host.

USB_WAKE_UP is an active high output (used only when USB_DETACH is active) to wake up the host and
allow USB communication to recommence. It replaces the function of the software USB WAKE_UP message
(which runs over the USB cable) and cannot be sent while BlueCore4-External is effectively disconnected
from the bus.

Bluegiga Technologies Oy

                          Page 21 of 36
                                             Figure 12: USB_Detach and USB_Wake_Up Signals

7.8 USB Driver

A USB Bluetooth device driver is required to provide a software interface between BlueCore4-External and
Bluetooth software running on the host computer. Please, contact support@bluegiga.com for suitable drivers.

7.9 USB v2.0 Compliance and Compatibility

Although WT41 meets the USB specification, CSR cannot guarantee that an application circuit designed
around the module is USB compliant. The choice of application circuit, component choice and PCB layout all
affect USB signal quality and electrical characteristics. The information in this document is intended as a guide
and should be read in association with the USB specification, with particular attention being given to Chapter
7. Independent USB qualification must be sought before an application is deemed USB compliant and can
bear the USB logo. Such qualification can be obtained from a USB plugfest or from an independent USB test
house.
Terminals USB_DP and USB_DN adhere to the USB Specification v2.0 (Chapter 7) electrical requirements.
BlueCore4-External is compatible with USB v2.0 host controllers; under these circumstances the two ends
agree the mutually acceptable rate of 12Mbits/s according to the USB v2.0 specification.

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8 Serial Peripheral Interface (SPI)

The SPI port can be used for system debugging. It can also be used for programming the Flash memory and
setting the PSKEY configurations. WT41 uses 16-bit data and 16-bit address serial peripheral interface, where
transactions may occur when the internal processor is running or is stopped. SPI interface is connected using
the MOSI, MISO, CSB and CLK pins. Please, contact support@bluegiga.com for detailed information about
the instruction cycle.

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9 PCM Codec Interface

PCM is a standard method used to digitize audio (particularly voice) for transmission over digital
communication channels. Through its PCM interface, WT41 has hardware support for continual transmission
and reception of PCM data, thus reducing processor overhead for wireless headset applications. WT41 offers
a bidirectional digital audio interface that routes directly into the baseband layer of the on-chip firmware. It
does not pass through the HCI protocol layer.
Hardware on WT41 allows the data to be sent to and received from a SCO connection. Up to three SCO
connections can be supported by the PCM interface at any one time.
WT41 can operate as the PCM interface master generating an output clock of 128, 256 or 512kHz. When
configured as PCM interface slave, it can operate with an input clock up to 2048kHz. WT41 is compatible with
a variety of clock formats, including Long Frame Sync, Short Frame Sync and GCI timing environments.
It supports 13-bit or 16-bit linear, 8-bit -law or A-law companded sample formats at 8ksamples/s and can
receive and transmit on any selection of three of the first four slots following PCM_SYNC. The PCM
configuration options are enabled by setting PSKEY_PCM_CONFIG32.
WT41 interfaces directly to PCM audio devices.

NOTE: Analog audio lines are very sensitive to RF disturbance. Use good layout practices to ensure noise
less audio. Make sure that the return path for the audio signals follows the forward current all the way as close
as possible and use fully differential signals when possible. Do not compromise audio routing.

9.1 PCM Interface Master/Slave

When configured as the master of the PCM interface, WT41 generates PCM_CLK and PCM_SYNC.

                                                          Figure 13: PCM Interface Master
When configured as the Slave of the PCM interface, WT41 accepts PCM_CLK rates up to 2048kHz.

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                                                           Figure 14: PCM Interface Slave

9.2 Long Frame Sync

Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or
samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When
WT41 is configured as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8-bits long.
When WT41 is configured as PCM Slave, PCM_SYNC may be from two consecutive falling edges of
PCM_CLK to half the PCM_SYNC rate, i.e., 62.5s long.

                                 Figure 15: Long Frame Sync (Shown with 8-bit Companded Sample)

WT41 samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge.
PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or
on the rising edge.

9.3 Short Frame Sync

In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is
always one clock cycle long.

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                                         Figure 16: Short Frame Sync (Shown with 16-bit Sample)

As with Long Frame Sync, WT41 samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT
on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in
the LSB position or on the rising edge.

9.4 Multi-slot Operation

More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO
connections can be carried over any of the first four slots.

                          Figure 17: Multi-slot Operation with Two Slots and 8-bit Companded Samples

9.5 GCI Interface

WT41 is compatible with the GCI, a standard synchronous 2B+D ISDN timing interface. The two 64kbits/s B
channels can be accessed when this mode is configured.

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                                                                Figure 18: GCI Interface

The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With WT41 in Slave mode,
the frequency of PCM_CLK can be up to 4.096MHz.

9.6 Slots and Sample Formats

WT41 can receive and transmit on any selection of the first four slots following each sync pulse. Slot durations
can be either 8 or 16 clock cycles. Durations of 8 clock cycles may only be used with 8-bit sample formats.
Durations of 16 clocks may be used with 8-bit, 13-bit or 16-bit sample formats.
WT41 supports 13-bit linear, 16-bit linear and 8-bit -law or A-law sample formats. The sample rate is
8ksamples/s. The bit order may be little or big endian. When 16-bit slots are used, the 3 or 8 unused bits in
each slot may be filled with sign extension, padded with zeros or a programmable 3-bit audio attenuation
compatible with some Motorola codecs.

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                                              Figure 19: 16-bit Slot Length and Sample Formats

9.7 Additional Features

WT41 has a mute facility that forces PCM_OUT to be 0. In master mode, PCM_SYNC may also be forced to 0
while keeping PCM_CLK running which some codecs use to control power down.

9.8 PCM_CLK and PCM_SYNC Generation

WT41 has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is generating
these signals by DDS from BlueCore4-External internal 4MHz clock. Using this mode limits PCM_CLK to 128,
256 or 512kHz and PCM_SYNC to 8kHz. The second is generating PCM_CLK and PCM_SYNC by DDS from
an internal 48MHz clock (which allows a greater range of frequencies to be generated with low jitter but
consumes more power). This second method is selected by setting bit 48M_PCM_CLK_GEN_EN in
PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the length of PCM_SYNC can be
either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in PSKEY_PCM_CONFIG32.
The Equation XXX describes PCM_CLK frequency when being generated using the internal 48MHz clock:

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                 Equation 2: PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock

The frequency of PCM_SYNC relative to PCM_CLK can be set using Equation XXX:

                                         Equation 3: PCM_SYNC Frequency Relative to PCM_CLK

CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an
example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set
PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.

9.9 PCM Configuration

The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 detailed in Table XXX and
PSKEY_PCM_LOW_JITTER_CONFIG in Table XXX. The default for PSKEY_PCM_CONFIG32 is
0x00800000, i.e., first slot following sync is active, 13-bit linear voice format, long frame sync and interface
master generating 256kHz PCM_CLK from 4MHz internal clock with no tri-state of PCM_OUT.

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        Name     Bit position  Description
           -
                 0                                       Set to 0
SLAVE MODE EN
                               0 selects Master mode with internal generation of PCM_CLK and
SHORT SYNC EN
           -     1             PCM_SYNC. 1 selects Slave mode requiring externally generated
                                      PCM_CLK and PCM_SYNC. This should be set to 1 if
SIGN EXTENDED
          EN                   48M_PCM_CLK_GEN_EN (bit 11) is set.

  LSB FIRST EN   2             0 selects long frame sync (rising edge indicates start of frame), 1
TX TRISTATE EN                  selects short frame sync (falling edge indicates start of frame).

  TX TRISTATE    3                                       Set to 0
RISING EDGE EN
                               0 selects padding of 8 or 13-bit voice sample into a 16- bit slot by

                 4                 inserting extra LSBs, 1 selects sign extension. When padding is
                               selected with 3-bit voice sample, the 3 padding bits are the audio gain

                               setting; with 8-bit samples the 8 padding bits are zeroes.

                 5             0 transmits and receives voice samples MSB first, 1 uses LSB first.

                               0 drives PCM_OUT continuously, 1 tri-states PCM_OUT immediately

                 6             after the falling edge of PCM_CLK in the last bit of an active slot,

                               assuming the next slot is not active.

                               0 tristates PCM_OUT immediately after the falling edge of PCM_CLK

                 7             in the last bit of an active slot, assuming the next slot is also not active.

                               1 tristates PCM_OUT after the rising edge of PCM_CLK.

SYNC SUPPRESS       8          0 enables PCM_SYNC output when master, 1 suppresses PCM_SYNC
           EN       9          whilst keeping PCM_CLK running. Some CODECS utilize this to enter
                   10
   GCI MODE EN     11                                             a low power state.
      MUTE EN
                   12                                           1 enables GCI mode.
48M PCM CLK GEN  [20:16]                                      1 forces PCM_OUT to 0.
           EN                  0 sets PCM_CLK and PCM_SYNC generation via DDS from internal 4
                                      MHz clock, as for BlueCore4-External. 1 sets PCM_CLK and
  LONG LENGTH                         PCM_SYNC generation via DDS from internal 48 MHz clock.
       SYNC EN
                                0 sets PCM_SYNC length to 8 PCM_CLK cycles and 1 sets length to
             -                      16 PCM_CLK cycles. Only applies for long frame sync and with
                                                      48M_PCM_CLK_GEN_EN set to 1.

                                                                    Set to 0b00000.

MASTER CLK RATE  [22:21]       Selects 128 (0b01), 256 (0b00), 512 (0b10) kHz PCM_CLK frequency
                                     when master and 48M_PCM_CLK_GEN_EN (bit 11) is low.

   ACTIVE SLOT   [26:23]                         Default is 0001. Ignored by firmaware
SAMPLE_FORMAT    [28:27]       Selects between 13 (0b00), 16 (0b01), 8 (0b10) bit sample with 16

                                   cycle slot duration 8 (0b11) bit sample 8 cycle slot duration.

                    Table 11: PSKEY_PCM_CONFIG32 description

    Name         Bit position                         Description
CNT LIMIT           [12:0]                Sets PCM_CLK counter limit
CNT RATE            [23:16]                  Sets PCM_CLK count rate.
SYNC LIMIT          [31:24]    Sets PCM_SYNC division relative to PCM_CLK.

                 Table 12: PSKEY_PCM_LOW_JITTER_CONFIG Description

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10 I/O Parallel Ports

Six lines of programmable bidirectional input/outputs (I/O) are provided. All the PIO lines are power from VDD.

PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. All PIO
lines are configured as inputs with weak pull-downs at reset. Any of the PIO lines can be configured as
interrupt request lines or as wake-up lines from sleep modes.

WT41 has a general purpose analogue interface pin AIO[1]. This is used to access internal circuitry and
control signals. It may be configured to provide additional functionality.

Auxiliary functions available via AIO[1] include an 8-bit ADC and an 8-bit DAC. Typically the ADC is used for
battery voltage measurement. Signals selectable at this pin include the band gap reference voltage and a
variety of clock signals: 48, 24, 16, 8MHz and the XTAL clock frequency. When used with analogue signals,
the voltage range is constrained by the analogue supply voltage internally to the module (1.8V). When
configured to drive out digital level signals (e.g., clocks), the output voltage level is determined by VDD.

10.1 PIO Defaults

Bluegiga cannot guarantee that these terminal functions remain the same. Refer to the software release note
for the implementation of these PIO lines, as they are firmware build-specific.

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11 Reset

WT41 may be reset from several sources: RESET pin, power on reset, a UART break character or via
software configured watchdog timer. The RESET pin is an active low reset and is internally filtered using the
internal low frequency clock oscillator. A reset will be performed between 1.5 and 4.0ms following RESETB
being active. It is recommended that RESET be applied for a period greater than 5ms.
The power on reset occurs when the VDD_CORE supply internally to the module falls below typically 1.5V
and is released when VDD_CORE rises above typically 1.6V. At reset the digital I/O pins are set to inputs for
bidirectional pins and outputs are tri-state.
The reset should be held active at power up until all the supply voltages have stabilized to ensure correct
operation of the internal flash memory. Following figure shows an example of a simple power up reset circuit.
Time constant of the RC circuitry is set so that the supply voltage is safely stabilized before the reset
deactivates.

                                   Figure 20: Example of a simple power on reset circuit.

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11.1 Pin States on Reset

PIN NAME                  STATE
PIO[7:2]                  Input with weak pull-down
PCM_OUT                   Tri-staed with weak pull-down
PCM_IN                    Input with weak pull-down
PCM_SYNC                  Input with weak pull-down
PCM_CLK                   Input with weak pull-down
UART_TX                   Output tristated with weak pull-up
UART_RX                   Input with weak pull-down
UART_RTS                  Output tristated with weak pull-up
UART_CTS                  Input with weak pull-down
USB+                      Input with weak pull-down
USB-                      Input with weak pull-down
SPI_CSB                   Input with weak pull-down
SPI_CLK                   Input with weak pull-down
SPI_MOSI                  Input with weak pull-down
SPI_MISO                  Output tristated with weak pull-down
AIO[1]                    Output, driving low

                                Table 13: Pin States on Reset

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12 Certifications

WT41 is compliant to the following specifications.

12.1 Bluetooth

WT41 module is Bluetooth qualified and listed as a controller subsystem and it is Bluetooth compliant to the
following profiles of the core spec version 2.1/2.1+EDR.
TBA

12.2 FCC

This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:

        (1) this device may not cause harmful interference, and
        (2) this device must accept any interference received, including interference that may
        cause undesired operation.

FCC RF Radiation Exposure Statement:
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. End
users must follow the specific operating instructions for satisfying RF exposure compliance. This transmitter
must not be co-located or operating in conjunction with any other antenna or transmitter.
Note:
When using WT41-A or WT41-N the end product must display an exterior label with the following detail
incorporated: "Contains Transmitter Module FCC ID: QOQWT41"

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12.3 CE

WT41 meets the requirements of the standards below and hence fulfills the requirements of EMC Directive
89/336/EEC as amended by Directives 92/31/EEC and 93/68/EEC within CE marking requirement.

      EMC (immunity only) EN 301 489-17 V.1.3.3 in accordance with EN 301 489-1 V1.8.1
      Radiated emissions EN 300 328 V1.7.1

12.4 Industry Canada (IC)

WT41 meets Industry Canada's procedural and specification requirements for certification.
Industry Canada ID: 5123A-BGTWT41

12.5 Qualified Antenna Types for WT41-N

This device has been designed to operate with the antennas listed below, and having a maximum gain of 2
dB. Antennas not included in this list or having a gain greater than 2 dB are strictly prohibited for use with this
device. The required antenna impedance is 50 ohms.

Qualified Antenna Types for WT41-N

Antenna Type  Maximum Gain

Dipole                            2.2 dBi

Table 14: Qualified Antenna Types for WT41-N

Any antenna that is of the same type and of equal or less directional gain as listed in table 14 can be used
without a need for retesting. To reduce potential radio interference to other users, the antenna type and its
gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that
permitted for successful communication. Using an antenna of a different type or gain more than 2.2 dBi will
require additional testing for FCC, CE and IC. Please, contact support@bluegiga.com for more information.

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13 Contact Information

Sales:                  sales@bluegiga.com

Technical support:      support@bluegiga.com
                        http://www.bluegiga.com/techforum/

Orders:                 orders@bluegiga.com

Head Office / Finland:  Phone: +358-9-4355 060
Street Address:         Fax: +358-9-4355 0660
Postal address:
Sales Office / USA:     Sinikalliontie 5A
                        02630 ESPOO
                        FINLAND

                        P.O. BOX 120
                        02631 ESPOO
                        FINLAND

                        Phone: (781) 556-1039
                        Bluegiga Technologies, Inc.
                        99 Derby Street, Suite 200 Hingham, MA 02043

                        Bluegiga Technologies Oy

                                                                      Page 36 of 36
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