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DSC-11524-443L

器件型号:DSC-11524-443L
器件类别:模拟混合信号IC    转换器   
厂商名称:Data Device Corporation
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器件描述

Digital to Synchro or Resolver, Hybrid, DDIP-36

参数
是否无铅含铅
是否Rohs认证不符合
厂商名称Data Device Corporation
零件包装代码DIP
包装说明DDIP-36
针数36
Reach Compliance Codecompliant
ECCN代码EAR99
最大角精度4 arc min
转换器类型DIGITAL TO SYNCHRO OR RESOLVER
JESD-30 代码R-XDIP-P36
JESD-609代码e0
长度48.1 mm
最大负电源电压-15.75 V
最小负电源电压-14.25 V
标称负供电电压-15 V
位数16
功能数量1
端子数量36
最高工作温度125 °C
最低工作温度-55 °C
封装主体材料UNSPECIFIED
封装代码DIP
封装形状RECTANGULAR
封装形式IN-LINE
峰值回流温度(摄氏度)NOT SPECIFIED
认证状态Not Qualified
筛选级别MIL-PRF-38534
座面最大高度5.69 mm
信号/输出频率1000 Hz
最大供电电压15.75 V
最小供电电压14.25 V
标称供电电压15 V
表面贴装NO
技术HYBRID
温度等级MILITARY
端子面层TIN LEAD
端子形式PIN/PEG
端子节距2.54 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度15.24 mm

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DSC-11524
16-BIT HYBRID D/S AND D/R CONVERTER
PIN PROGRAMMABLE FOR SYNCHRO
OR RESOLVER OUTPUT
DESCRIPTION
The DSC-11524 is a versatile multi-
plying digital-to-analog converter.
The digital input represents an
angle, and the output is pin program-
mable for either resolver, sin/cos, or
three-line synchro type output. The
reference input will accept any wave-
form, even a sawtooth for CRT drive.
Because the reference is DC cou-
pled to the output, the DSC-11524
can be used in many configurations,
such as: a digital-to-synchro/resolver
converter using a sinusoidal refer-
ence as an input; a digital-to-sin/cos
DC converter using a DC reference;
a polar-to-rectangular converter
using a reference input proportional
to the radius vector; a rotating cart-
wheel sweep generator for PPI dis-
plays using a sawtooth reference.
Packaged in a 36-pin DDIP, the
DSC-11524 is a complete D/S and
D/R converter in one hybrid module.
Hybrid technology results in low
weight, low power consumption, very
high reliability, and a wide operating
temperature range. The DSC-11524
circuit design allows for higher accu-
racy and reduces the output scale
factor variation so that the output
can drive displays directly. The out-
put line-to-line voltage can be scaled
by external resistors. Other features
include high ac and DC common
mode rejection at the reference
input, and output short circuit protec-
tion.
FEATURES
15 mA RMS Output
11.8 V
L-L
Synchro, 11.8 V
L-L
Resolver, or 6.81 V
L-L
Resolver
Output
8 Bit/2 Byte Double-Buffered
Transparent Latches
Resolver Output
APPLICATIONS
Because of its high reliability, small
size and low power consumption the
hybrid DSC-11524 is ideal for the
most stringent and severe industrial
and military ground or avionics appli-
cations. All units are available with
MIL-PRF-38534 processing as a
standard option.
Among the many possible applica-
tions are computer-based systems
in which digital information is
processed, such as simulators, flight
trainers, flight instrumentation, fire
control systems, radar and naviga-
tion systems, and PPI displays
including moving target indicators.
Pin Programmable for Synchro or
16-Bit Resolutlon
Complete D/S and D/R Converter
Mate to DSC-36020 IBM
®
PC Card
DC-Coupled Reference Accepts Any
Waveform
Generates Sin/Cos DC or Rotating
PPI Sweep
High-Rel CMOS D/R Chip
No +5 V Supply Required
TEST POINT -R
SYNCHRO OR
RESOLVER
OUTPUT
(PIN JUMPER
PROGRAMMABLE)
S1
HIGH ACCURACY
LOW SCALE FACTOR
VARIATION
REFERENCE
CONDITIONER
BITS 1-16
TRANSPARENT LATCH
TRANSPARENT LATCH
ELECTRONIC
SCOTT-T OR
RESOLVER
SCALING
OUTPUT
AMPLIFIERS
S2
´
S2
S3
S3
´
S4
REFERENCE
INPUTS
100 KΩ
26 V
100 KΩ
5 KΩ
ADJUSTABLE
1.3-26 V
5 KΩ
D/R
CONVERTER
LA
LM
BITS 1-8
BITS 9-16
DIGITAL INPUTS
LL
FIGURE 1. DSC-11524 BLOCK DIAGRAM
© 1995, 1999 Data Device Corporation
® IBM is a registered trademark of International Business Machines Corporation.
TABLE 1. DSC-11524 SPECIFICATIONS
Apply over temperature range, power supply range, reference voltage and frequency range,
and 10% harmonic distortion in the reference.
PARAMETER
RESOLUTION
ACCURACY and DYNAMICS
Output Accuracy
Differential Linearity
Output Setting Time
DIGITAL INPUT
Logic Type
UNIT
Bits
VALUE
16
Minutes ±4 to ±2 min. (See Ordering info.)
LSB
±1 max
µsec
Less than 20 for any digital step change
Natural binary angle, parallel positive
logic CMOS and TTL compatable.
Inputs are CMOS transient protected.
Logic 0 = 0 to +1 V
Logic 1 = +2.2 V to +5 V
20 max to GND (bits 1-16)
20 max to +5 V (LL, LM, LA)
See Timing Diagrams (FIGURES 2A/2B.).
Two differential solid-state inputs: one for
standard 26 V, one programmable.
DC to 1k (to 10k with reduced accuracy)
Standard Input Programmable Input
26 (Note 1)
1.3 minimum for full output;
higher voltages are
scaled by adding two
series resistors
Load Current
µA
REFERENCE INPUT
Type
Frequency Range
Hz
Voltage
V
Input Impedance
n
Single Ended
n
Differential
ANALOG OUTPUT
Type
Output Current
Output Voltage
n
Synchro mode
n
Resolver mode
Transform. Ratio Tol.
Scale Factor Varation
DC Offset
(Each Line to Gnd)
POWER SUPPLIES
Voltage
Max voltage without damage
Max Current or Impedance
TEMPERATURE RANGES (CASE)
Operation
n
-1 Option
n
-3 Option
Storage
PHYSICAL CHARACTERISTICS
Type
Size
Weight
k ohm
k ohm
100 ±0.5%
200 ±0.5%
5 ±0.5%
10 ±0.5%
Pin programmable for synchro or resolver
mA rms 15 max
(Tracks Reference Input Voltage)
Vrms
L-L
11.8 nominal
Vrms
L-L
6.81 or 11.8 nominal
%
±0.5 max
%
±0.1 max
mV
V
mA
±15 max. Varies with input angle.
+15 ± 5%
+18 V
35+ load current
-15 ± 5%
-18 V
35+ load current
°C
°C
°C
-55 to +125
0 to +70
-55 to +135
36-pin DDIP
0.78 x 1.9 x 0.21 (19.7 x 48.3 x 5.3)
0.85 (24)
in.(mm)
oz. (g)
Notes: 1) Maximum reference input voltage for RH/RL is 26 V +10%.
2) Differential is Line-to-Line (L-L); single-ended is Line-to-Ground (L-Gnd).
2
INTRODUCTION
As shown in FIGURE 1, the signal conversion in the DSC-11524
is performed by a high-accuracy digital-to-resolver converter
whose sin and cos outputs have a low scale factor variation as a
function of the digital input angle. This resolver output is either
amplified by scaling amplifiers for resolver output, or is both
amplified and converted to a synchro output by an electronic
Scott-T. In both cases the output line currents can be 15 mA rms
max, which is sufficient for driving S/D converters, solid-state
control transformers and displays. Output power amplifiers will
be required, however, for driving electromechanical devices such
as synchros and resolvers.
The reference conditioner has a differential input with high ac
and DC common mode rejection, so that a reference isolation
transformer will seldom be required. There are two sets of refer-
ence inputs. The RH, RL input provides the maximum synchro or
resolver output voltage for a standard 26 V rms reference input.
The RH´, RL´ input is used to scale the output for other reference
voltage levels. Series resistors can be added to the reference
input as described below, either to accommodate higher refer-
ence levels, or to reduce the output level. The reference condi-
tioner output -R is intended for test purposes. A signal between
6 V and 7.5 V at -R indicates that a reference input signal is pre-
sent.
OUTPUT SCALING AND REF LEVEL ADJUSTMENT
The DSC-11524 operates like a multiplying D/A converter in that
the voltage of each output line is directly proportional to the ref-
erence voltage. The maximum line-to-line levels are determined
by the output amplifiers and are nominally 11.8 V for synchro out-
put and 6.81 V or 11.8 V for resolver output. The RH, RL refer-
ence input is designed to provide this nominal output for the
standard 26 V reference level. The scaling adjustment is made by
two internal 100k ohm resistors in series with the reference con-
ditioner input (see FIGURE 1).
The RH´, RL´ reference input has only 5k ohm internal resistors
in series with the reference conditioner input, so that nominal
line-to-line output is obtained for a reference input of 1.3 V. For
higher reference voltages, two resistors, R’, must be inserted in
series with the inputs as shown in FIGURE 3. These resistors
scale the DSC-11524 to accommodate higher reference levels,
or to reduce the output levels.
The magnitude of the resistors, R´, in ohms is calculated as follows:
R´ = 5000 • (V
R
- 1.3) •
1.3
[
N
OMINAL L
-
L
V
OLTAGE LEVEL
D
ESIRED L
-
L
V
OLTAGE LEVEL
]
DIGITAL INPUT
The converter contains three input latches. The input is con-
trolled by LM and LL. Each of these enable the converter to inter-
face with an 8-bit bus. LM controls bits 1-8 and LL controls bits
9-16. Ensure that the data is stable for 50ns before enabling a
latch (LL, LM), and allow 100ns for the latch to input the data.
Note: The above equation is for scaling the RH´, RL´ inputs. To
calculate R´ to scale the RH, RL input use 100,000 in place of
5,000 in the equation.
8-bit
50 nsec
100 nsec
200 ns MIN
TRANSPARENT
LL / LM / LA LATCHED
LL
50 nsec
DATA 1-16 BITS
,,, ,,
50 ns MIN
100 ns MIN
100 nsec
LM
LA
100 nsec
FIGURE 2A. LL, LM, LA TIMING DIAGRAM (16-BIT)
FIGURE 2B. LL, LM, LA TIMING DIAGRAM (8-BIT)
3
OUTPUT CONFIGURATION
The output amplifier section can be configured for Synchro and
Resolver outputs, as shown in FIGURE 4.
maximum variation in A
o
from all causes is ± 0.5%. The term A(θ)
represents the variation of the amplitude with the digital signal
input angle. A(θ), which is called the scale factor variation, is a
smooth function of (θ) without discontinuities and is less than
±0.1% for all values of (θ). The total maximum variation in A
o
(1
+ A(θ)) is therefore ± 0.6%.
Because the amplitude factor (RH - RL)A
o
(1 + A(θ)) varies simul-
taneously on all output lines, it will not be a source of error when
the DSC-11524 is to drive a ratiometric system such as a syn-
chro or resolver. However, if the outputs are used independently,
as in x-y plotters, the amplitude variations must be taken into
account.
OUTPUT PHASING AND OUTPUT SCALE FACTOR
The analog output signals have the following phasing:
Synchro output:
S3—S1 = (RH - RL)A
o
(1 + A(θ)) sin
θ
S2—S3 = (RH - RL)A
o
(1 + A(θ)) sin(
θ
+ 120°)
S1—S2 = (RH - RL)A
o
(1 + A(θ)) sin(
θ
+ 240°)
Resolver output:
S3—S1 = (RH - RL)A
o
(1 + A(θ)) sin
θ
S2—S4 = (RH - RL)A
o
(1 + A(θ)) cos
θ
The output amplifiers simultaneously track reference voltage
fluctuations because they are proportional to (RH - RL). The
transformation ratio A
o
is 11.8/26 for 11.8 V rms L-L output. The
OUTPUT TRANSFORMER
The DSC-11524 uses the 51538 step-up transformer to drive 90
V
L
-
L
synchro loads. The 51538 transformer specifications are
shown in TABLE 2 and the schematic and mechanical outline
drawings are shown in FIGURE 5.
(V
R
)
REF
INPUT
11 RH´
9 RL´
DSC-11524
FIGURE 3. REFERENCE LEVEL ADJUSTMENT
S3’
S3
S1
DSC-11524
S2
S4
S2’
34
35
32
36
31
33
S3
S1
S2
S4
11.8 V RESOLVER OUTPUT
32
36
33
35
34
35
36
33
S1
S2
DSC-11524
S2’
S3
S3’
S1
S2
S3
S3
DSC-11524
S2
S2’
+SIN
+COS
RTN
11.8 V SYNCHRO OUTPUT
6.81 V RESOLVER OUTPUT
FIGURE 4. OUTPUT PIN PROGRAMMING
4
TABLE 2. ELECTRICAL SPECIFICATIONS FOR THE 51538 TRANSFORMER
Synchro Input
Synchro Output
Input Impedance
Output Impedance
Accuracy
HIPOT
11.8 Vrms line-to-line ±10% at 400 Hz ±10%
90 Vrms ±1% Full Scale with a line-to-line input voltage of 11.8 Vrms
1000 Ohms minimum
500 Ohms maximum
The maximum additional error shall be 1.5 min. loaded with an SDC-14560 (130k Ohm)
Between windings and windings-to-case 900 Vrms at 60 Hz
1.63 MAX
(41.40)
0.042
+0.003
-0.102
DIA PIN
0.23 MIN
(5.842)
8 PLACES
(1.067
-0.102
)
1 2
1.130 MAX
(28.702)
4 5
6 7
3 8
0.800
0.40 (20.32)
(10.16)
+0.076
0.510 MAX
(12.954)
MARKING
DOT THIS SIDE SIDE OPPOSITE PIN 1
0.800
(20.32)
1.00
(25.4)
0.200
(5.08)
0.40
(10.16)
S1
SYNCHRO
OUTPUT
(11.8V)
S3
SIDE VIEW
1
2
T1B
3
7
T1A
5
6
S1
S3
BOTTOM VIEW
SYNCHRO
OUTPUT
(90V)
S2
S2
FIGURE 5. 90 V
L
-
L
, 400 H
Z
SYNCHRO OUTPUT TRANSFORMER (P/N 51538)
5

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