DEMO CIRCUIT 1459B
Harvesting Power Supply
Demonstration Circuit 1459B is an energy harvesting produces a logic high referenced to VOUT on the
power supply featuring the LTC3588-1/LTC3588-2. PGOOD pin when the converter reaches the pro-
The LTC3588 integrates a low-loss full-wave bridge grammed VOUT, signaling that the output is in regula-
with a high efficiency buck converter to form a com- tion.
plete energy harvesting solution optimized for high The LTC3588EMSE-1/LTC3588EMSE-2 are available
output impedance energy sources such as piezoelec- in a 10-lead (3mm × 3mm) MSE surface mount pack-
tric transducers. An ultralow quiescent current under- age with exposed pad.
voltage lockout mode with a wide hysteresis window
allows charge to accumulate on an input capacitor L, LTC, LTM, LT, Burst Mode, OPTI-LOOP, Over-The-Top and PolyPhase are registered
until the buck converter can efficiently transfer a por- trademarks of Linear Technology Corporation. Adaptive Power, C-Load, DirectSense, Easy
Drive, FilterCAD, Hot Swap, LinearView, µModule, Micropower SwitcherCAD, Multimode
tion of the stored charge to the output. Four output Dimming, No Latency ∆Σ, No Latency Delta-Sigma, No RSENSE, Operational Filter, PanelProtect,
PowerPath, PowerSOT, SmartStart, SoftSpan, Stage Shedding, SwitcherCAD, ThinSOT,
voltages are pin selectable with up to 100mA of con- UltraFast and VLDO are trademarks of Linear Technology Corporation. Other product names
tinuous output current. A power good comparator may be trademarks of the companies that manufacture the products.
TABLE 1 LTC3588EMSE-1
PERFORMANCE SUMMARY Specifications are at TA = 25°C
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
VIN Input Voltage Range 4.3 18.0 V
VOUT 1.8V Output Voltage Range D0 = 0, D1=0 1.71 to 1.89 V
VOUT 2.5V Output Voltage Range D0 = 1, D1=0 2.425 to 2.575 V
VOUT 3.3V Output Voltage Range D0 = 0, D1=1 3.201 to 3.399 V
VOUT 3.6V Output Voltage Range D0 = 1, D1=1 3.491 to 3.708 V
PERFORMANCE SUMMARY LTC3588EMSE-2 Specifications are at TA = 25°C
SYMBOL PARAMETER CONDITIONS MIN MAX UNITS
VIN Input Voltage Range 14.0 18.0 V
VOUT 3.45V Output Voltage Range D0 = 0, D1=0 3.346 to 3.554 V
VOUT 4.1V Output Voltage Range D0 = 1, D1=0 3.977 to 4.223 V
VOUT 4.5V Output Voltage Range D0 = 0, D1=1 4.365 to 4.635 V
VOUT 5.0V Output Voltage Range D0 = 1, D1=1 4.850 to 5.150 V
Refer to the block diagram within the LTC3588-1/-2 nected to the CAP and VIN2 pins to serve as energy
data sheet for its operating principle. reservoirs for driving the buck switches.
The buck regulator uses a hysteretic voltage algo-
The LTC3588 is an ultralow quiescent current power rithm to control the output through internal feedback
supply designed specifically for energy harvesting from the VOUT sense pin. The buck converter charges
and/or low current step-down applications. The part an output capacitor through an inductor to a value
is designed to interface directly to a piezoelectric or slightly higher than the regulation point. It does this
alternative A/C energy source, rectify and store the by ramping the inductor current up to 250mA
harvested energy on an external capacitor, bleed off through an internal PMOS switch and then ramping it
any excess energy via an internal shunt regulator, down to 0mA through an internal NMOS switch.
and maintain a regulated output voltage by means of When the buck brings the output voltage into regula-
a nano-power high efficiency synchronous buck reg- tion the converter enters a low quiescent current
ulator. sleep state that monitors the output voltage with a
The LTC3588 has an internal full-wave bridge recti- sleep comparator. During this operating mode load
fier accessible via PZ1 and PZ2 that rectifies AC in- current is provided by the buck output capacitor.
puts such as those from a piezoelectric element. The When the output voltage falls below the regulation
rectified output is stored on a capacitor at the VIN pin point the buck regulator wakes up and the cycle re-
and can be used as an energy reservoir for the buck peats. This hysteretic method of providing a regu-
converter. The bridge is capable of carrying up to lated output reduces losses associated with FET
50mA. switching and maintains an output at light loads. The
When the voltage on VIN crosses the UVLO rising buck delivers a minimum of 100mA average load
threshold the buck converter is enabled and charge current when it is switching.
is transferred from the input capacitor to the output A power good comparator produces a logic high ref-
capacitor. A wide (~1V) UVLO hysteresis window is erenced to VOUT on the PGOOD pin the first time the
employed with a lower threshold approximately converter reaches the programmed VOUT, signaling
200mV above the selected regulated output voltage that the output is in regulation. The PGOOD pin will
to prevent short cycling during buck power-up. remain high until VOUT falls to 92% of the desired
When the input capacitor voltage is depleted below regulated voltage.
the UVLO falling threshold the buck converter is dis-
Two internal rails, CAP and VIN2, are generated from
VIN and are used to drive the high side PMOS and
low side NMOS of the buck converter, respectively.
Additionally the VIN2 rail serves as logic high for out-
put voltage select bits D0 and D1. The VIN2 rail is re-
gulated at 4.8V above GND while the CAP rail is regu-
lated at 4.8V below VIN. These are not intended to be
used as external rails. Capacitors should be con-
QUICK START PROCEDURE
Using short twisted pair leads for any power con- current. If the current remains less than 5mA,
nections, with all loads and power supplies off, refer increase PS1 to 17V. Verify voltage on VOUT
to Figure 1 for the proper measurement and equip- is within the VOUT 1.8V/3.45V range in Table
ment setup. 1.Decrease PS1 to 0V, swap the PZ1 move the
Follow the procedure below: lead connections to PZ2 and repeat the test.
1. Before connecting PS1 to the DC1459B, PS1 Decrease PS1 to 0V and move the connection
must have its current limit set to 50mA. For for PS1 from PZ2 to VIN.
most power supplies with a current limit ad- 6. Set JP1 to 1. Increase PS1 to 17V and set
justment feature the procedure to set the cur- LOAD1 to 100mA. Verify voltage on VOUT is
rent limit is as follows. Turn the voltage and within the VOUT 2.5V/4.1V range in Table 1.
current adjustment to minimum. Short the Verify that the output ripple voltage is between
outputs terminals and turn the voltage ad- 40mV to 90mV.
justment to maximum. Adjust the current
limit to 50mA. Turn the voltage adjustment to 7. Set JP1 to 0 and JP2 to 1. Set LOAD1 to
minimum. The power supply is now current 100mA. Verify voltage on VOUT is within the
limited to 50mA. VOUT 3.3V/4.5V range in Table 1. Verify that
2. Initial Jumper, PS and LOAD 1settings: the output ripple voltage is between 50mV and
JP1 = 0 PS1 = OFF 90mV.
JP2 =0 LOAD1 = OFF 8. Set JP1 to 1 and JP2 to 1. Set LOAD1 to
100mA. Verify voltage on VOUT is within the
3. Connect PS1 to the VIN Terminals, then turn VOUT 3.6V/5.0V range in Table 1. Verify that
on PS1 and slowly increase voltage to 2.0V the output ripple voltage is between 60mV and
while monitoring the input current. If the cur- 110mV.
rent remains less than 5mA, increase PS1 to 9. Decrease LOAD1 to 1mA. Turn off PS1 and
17.0V. insert a 1K ohm resistor between the positive
4. Set LOAD1 to 100mA. Verify voltage on VOUT lead of the PS1 and the VIN turret. Turn on
is within the VOUT 1.8V/3.45V range in Table PS1 and while monitoring the voltage on VIN,
1. Verify that the output ripple voltage is be- increase PS1 until the voltage on VIN is 3V be-
tween 40mV and 90mV. Verify that PGOOD is low the voltage on PS1. Verify input voltage,
high (VOUT). Decrease LOAD1 to 5mA. VIN, VSHUNT of 19.0V to 21.0V.
5. Decrease PS1 to 0V and move the connection 10. Turn off PS1 and LOAD1.
for PS1 from VIN to PZ1. Slowly increase PS1
voltage to 2.0V while monitoring the input
Figure 1. Proper Measurement Equipment Setup
Figure 2: Schematic diagram
Bill of Materials
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