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CDB4216

器件型号:CDB4216
器件类别:半导体    其他集成电路(IC)   
厂商名称:Cirrus Logic
厂商官网:http://www.cirrus.com
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器件描述

SPECIALTY CONSUMER CIRCUIT, PQCC44

专业消费类电路, PQCC44

参数
CDB4216功能数量 1
CDB4216端子数量 44
CDB4216最大工作温度 70 Cel
CDB4216最小工作温度 0.0 Cel
CDB4216最大供电/工作电压 5.25 V
CDB4216最小供电/工作电压 4.75 V
CDB4216加工封装描述 PLASTIC, LCC-44
CDB4216状态 ACTIVE
CDB4216工艺 CMOS
CDB4216包装形状 SQUARE
CDB4216包装尺寸 CHIP CARRIER
CDB4216表面贴装 Yes
CDB4216端子形式 J BEND
CDB4216端子间距 1.27 mm
CDB4216端子涂层 TIN LEAD
CDB4216端子位置 QUAD
CDB4216包装材料 PLASTIC/EPOXY
CDB4216温度等级 COMMERCIAL
CDB4216消费IC类型 CONSUMER CIRCUIT

文档预览

Semiconductor Corporation
CS4216
General Description
The CS4216 is an Mwave
TM
audio codec.
The CS4216 Stereo Audio Codec is a monolithic
CMOS device for computer multimedia, automotive,
and portable audio applications. It performs A/D and
D/A conversion, filtering, and level setting, creating 4
audio inputs and 2 audio outputs for a digital computer
system. The digital interfaces of left and right channels
are multiplexed into a single serial data bus with word
rates up to 50 kHz per channel. Up to 4 CS4216 de-
vices can be attached to a single hardware bus.
Both the ADCs and the DACs use delta-sigma modula-
tion with 64X oversampling. The ADCs include a digital
decimation filter which eliminates the need for external
anti-aliasing filters. The DACs include output smoothing
filters on-chip.
Ordering Information:
CS4216-KL
0° to 70°C
CS4216-KQ
0° to 70°C
CDB4216
Evaluation Board
44-pin PLCC
44-pin TQFP
16-Bit Stereo Audio Codec
Features
CMOS Stereo Audio Input/Output System
Delta-Sigma A/D Converters
Delta-Sigma D/A Converters
Input Anti-Aliasing and Output
Smoothing Filters
Programmable Input Gain and
Output Attenuation
Sample Frequencies of 4 kHz to 50 kHz
CD Quality Noise and Distortion
< 0.01 %THD
Internal 64X Oversampling
Low Power Dissipation: 80 mA
1 mA Power-Down Mode
RESET
POW ER
CONTROL
PDN
D IG IT A L
F IL T E R S
D /A
OUTPUT
A T TE N U A TIO N
LO U T
OUTPUT
MUTE
ROUT
DO 1
M F 5 :D O 2 /IN T
M F 2 :D O 3 /F 2 /C D IN
M F 1 :D O 4 /F 1 /C D O U T
D I1
M F 6 :D I2 /F 1
M F 3 :D I3 /F 3 /C C L K
M F 4 :D I4 /M A /C C S
R EFG N D
R EF BYP
REFBUF
L IN 1
L IN 2
INPUT
GAIN
INPUT
MUX
R IN 1
R IN 2
SM ODE3
SM ODE2
SM ODE1
S D IN
SDOUT
SC LK
SSYNC
D /A
S E R IA L IN T E R F A C E C O N T R O L
V O LTAG E R EFERE NC E
D IG ITA L
F IL T E R S
M F 7:S F S 1 /F 2
M F 8:S F S 2 /F 3
C L K IN
A /D
A /D
VD
VA
DGND
AGND
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
Copyright
©
Crystal Semicondutor Corporation 1993
(All Rights Reserved)
Oct ’93
DS83F2
1
CS4216
RECOMMENDED OPERATING CONDITIONS
spect to 0V.)
Parameter
Power Supplies:
Operating Ambient Temperature
Digital
Analog
(AGND, DGND = 0V, all voltages with re-
Min
4.75
4.75
0
Typ
5.0
5.0
25
Max
5.25
5.25
70
Units
V
V
°C
Symbol
VD
VA
TA
ANALOG CHARACTERISTICS
( T
A
= 25°C; VA, VD = +5V; Input Levels: Logic 0 = 0V,
Logic 1 = VD; 1 kHz Input Sine Wave; CLKIN = 24.576 MHz; SM1; Conversion Rate = 48 kHz; SCLK =
12.288 MHz; Measurement Bandwidth is 10 Hz to 20 kHz; Unless otherwise specified.)
Parameter *
Symbol
Min
Typ
Max
Units
Analog Input Characteristics
- Minimum gain setting (0 dB); unless otherwise specified.
ADC Resolution
ADC Differential Nonlinearity
Instantaneous Dynamic Range
Total Harmonic Distortion
Interchannel Isolation
Interchannel Gain Mismatch
Frequency Response
Programmable Input Gain Span
Gain Step Size
Absolute Gain Step Error
Gain Drift
Offset Error
Full Scale Input Voltage
Input Resistance
Input Capacitance
(Notes 1,2)
(Note 1)
DC Coupled Inputs
AC Coupled Inputs
(Note 1)
(Note 1)
IDR
THD
16
-
80
-
-
-
-0.5
21
-
-
-
-
-
2.5
20
-
-
-
85
-
80
-
-
22.5
1.5
-
100
±10
±150
2.8
-
-
-
±0.9
-
0.01
-
±0.5
+0.2
24
-
0.75
-
±100
±400
3.1
-
15
Bits
LSB
dB
%
dB
dB
dB
dB
dB
dB
ppm/°C
LSB
LSB
Vpp
kΩ
pF
Notes: 1. This specification is guaranteed by characterization, not production testing.
2. Input resistance is for the input selected. Non-selected inputs have a very high (>1MΩ) input resistance.
* Parameter definitions are given at the end of this data sheet.
Mwave
TM
is a trademark of the IBM Corporation.
Specifications are subject to change without notice.
2
DS83F2
CS4216
ANALOG CHARACTERISTICS
Parameter *
(Continued)
Symbol
Min
Typ
Max
Units
Analog Output Characteristics
- Minimum Attenuation; Unless Otherwise Specified.
DAC Resolution
DAC Differential Nonlinearity
Total Dynamic Range
Instantaneous Dynamic Range
Total Harmonic Distortion
Interchannel Isolation
Interchannel Gain Mismatch
Frequency Response
Programmable Output Attenuation Span
Attenuation Step Size
Absolute Attenuation Step Error
Gain Drift
REFBUF Output Voltage
Offset Voltage
Full Scale Output Voltage
Deviation from Linear Phase
Out of Band Energy
(Note 4)
(Note 1)
(22 kHz to 100 kHz)
(Note 5)
Maximum output current= 400
µA
(Note 1)
(Note 3)
(Note 3)
(Note 3)
(Note 4)
(Note 4)
(Note 1)
TDR
IDR
THD
16
-
-
80
-
-
-
-0.5
-45
-
-
-
1.9
-
2.5
-
-
-
-
93
83
-
80
-
-
-46.5
1.5
-
100
2.2
10
2.8
-
-60
-
±0.9
-
-
0.02
-
±0.5
+0.2
-
-
0.75
-
2.5
-
3.1
1
-
Bits
LSB
dB
dB
%
dB
dB
dB
dB
dB
dB
ppm/°C
V
mV
Vpp
Degree
dB
Power Supply
Power Supply Current
Power Supply Rejection
(Note 6)
Operating
Power Down
(1 kHz)
-
-
-
80
-
40
100
1
-
mA
mA
dB
Notes: 3. Tested in SM3, Slave sub-mode, 128 BPF.
4. 10 kΩ, 100 pF load.
5. REFBUF load current must be DC. To drive dynamic loads, REFBUF must be buffered.
AC variations in REFBUF current may degrade ADC and DAC performance.
6. Typically current: VA = 30mA, VD = 50mA. Power supply current does not include output loading.
* Parameter definitions are given at the end of this data sheet.
DS83F2
3
CS4216
SWITCHING CHARACTERISTICS
(T
A
= 25°C; VA, VD = +5V, outputs loaded with 30 pF; Input
Levels: Logic 0 = 0V, Logic 1 = VD)
Parameter
Input clock (CLKIN) frequency
CLKIN low time
CLKIN high time
Sample Rate
DI pins setup time to SCLK edge
DI pins hold time from SCLK edge
DO pins delay from SCLK edge
SCLK and SSYNC output delay
from CLKIN rising
SCLK period
SCLK high time
SCLK low time
SDIN, SSYNC setup time to SCLK edge
SDIN, SSYNC hold time from SCLK edge
SDOUT delay from SCLK edge
Output to Hi-Z state
Output to non-Hi-Z
RESET pulse width low
CCS low to CCLK rising
CDIN setup to CCLK falling
CCLK low to CDIN invalid (hold time)
CCLK high time
CCLK low time
CCLK Period
CCLK rising to CDOUT data valid
CCLK rising to CDOUT Hi-Z
CCLK falling to CCS high
SM4 (Note 1)
SM4 (Note 1)
SM4 (Note 1)
SM4 (Note 1)
SM4 (Note 1)
SM4 (Note 1)
SM4 (Note 1)
SM4 (Note 1)
SM4 (Note 1)
tcslcc
tdiscc
tccdih
tcclhh
tcclhl
tcclkw
tccdov
tccdot
tcccsh
bit 64 (Note 1)
bit 1 (Note 1)
Master Mode (Note 1)
Master Mode (Note 7)
Slave Mode
Slave Mode
Slave Mode
Slave Mode
Slave Mode
(Note 1)
(Note 1)
(Note 1)
SM1:
SM2, SM3, SM4:
Symbol
CLKIN
CLKIN
tckl
tckh
Fs
ts2
th2
tpd2
tpd3
tsckw
tsckh
tsckl
ts1
th1
tpd1
thz
tnz
Min
2.048
1.024
15
15
4
10
8
30
-
-
75
30
30
15
10
-
-
15
500
25
15
10
25
25
75
-
-
0
Typ
24.576
12.288
-
-
-
-
-
-
-
1/(Fs*bpf)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
25.6
12.8
-
-
50
-
-
-
50
-
-
-
-
-
-
28
12
-
-
-
-
-
-
-
-
30
30
-
Units
MHz
MHz
ns
ns
kHz
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 7. When the CS4216 is in master mode (SSYNC and SCLK outputs), the SCLK duty cycle is 50%.
The equation is based on the selected sample frequency (Fs) and the number of bits per frame (bpf).
4
DS83F2
CS4216
Frame Sync
SSYNC
[SM1, SM2\
t sckl
SCLK
[SM1,SM2\
t sckw
SCLK
[SM3,SM4\
t sckh t sckl
t s1
SSYNC
[SM3,SM4\
t s1
SDIN
[SM1,SM2,SM3\
(SM4)
t h1
Bit 1
t pd1
[SM1,SM2,SM3\
SDOUT
(SM4)
t nz
* Optional
Bit 1
Bit 2
t pd1
Bit 2
Bit 32
(Bit 32)
Bit 33
(Bit 1)
Bit 63
(Bit 31)
Bit 64
(Bit 32)
Bit 32
(Bit 32)
Bit 33
(Bit 1)
Bit 63
(Bit 31)
Bit 64
(Bit 32)
t hz
t h1
t sckh
t s1
t h1
t s1
t h1
*Word Sync
*Word Sync
Serial Audio Port Timing
M F 4 :C C S
M F 1 :C D O U T
ADV
t cslcc
t cclkh
t ccd ih
0
1
M SK
2
DO1
3
L A tt4
4
t cclkl
t ccd o v
LCL
M F 3 :C C L K
t disc c
M F 2 :C D IN
t cc lkw
L A tt3
5
L A tt2
6
L A tt1
7
L A tt0
8
R A tt4
9
R A tt3
10
R A tt2
11
M F 4 :C C S
t c ccs h
M F 1 :C D O U T
0
0
1
Err1
Err0
LCL
RCL
D I1
ADV
t cc do t
M F 3 :C C L K
M F 2 :C D IN
R G a in 2 R G ain1 R G ain0
22
23
24
0
25
0
26
0
27
0
28
0
29
0
30
0
31
0
32
Serial Mode 4. Control Data Serial Port Timing
DS83F2
5
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