CC2530F32, CC2530F64, CC2530F128, CC2530F256
www.ti.com .......................................................................................................................................................... SWRS081A APRIL 2009 REVISED APRIL 2009
A True System-on-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee Applications
FEATURES Accurate Digital RSSI/LQI Support
Battery Monitor and Temperature Sensor
1 12-Bit ADC With Eight Channels and
2345 RF/Layout Configurable Resolution
2.4-GHz IEEE 802.15.4 Compliant RF AES Security Coprocessor
Transceiver Two Powerful USARTs With Support for
Excellent Receiver Sensitivity and
Robustness to Interference Several Serial Protocols
Programmable Output Power Up to 4.5 dBm 21 General-Purpose I/O Pins (19 4 mA, 2
Very Few External Components
Only a Single Crystal Needed for Mesh 20 mA)
Network Systems Watchdog Timer
6-mm 6-mm QFN40 Package Development Tools
Suitable for Systems Targeting Compliance CC2530 Development Kit
With Worldwide Radio-Frequency CC2530 ZigBee Development Kit
Regulations: ETSI EN 300 328 and EN 300 CC2530 RemoTITM Development Kit for
440 (Europe), FCC CFR47 Part 15 (US) and
ARIB STD-T-66 (Japan) RF4CE
SmartRFTM Software
Low Power Packet Sniffer
Active-Mode RX (CPU Idle): 24 mA IAR Embedded WorkbenchTM Available
Active Mode TX at 1 dBm (CPU Idle): 29 mA
Power Mode 1 (4 s Wake-Up): 0.2 mA APPLICATIONS
Power Mode 2 (Sleep Timer Running): 1 A
Power Mode 3 (External Interrupts): 0.4 A 2.4-GHz IEEE 802.15.4 Systems
Wide Supply-Voltage Range (2 V3.6 V) RF4CE Remote Control Systems (64-KB Flash
Microcontroller and Higher)
High-Performance and Low-Power 8051 ZigBee Systems (256-KB Flash)
Microcontroller Core With Code Prefetch Home/Building Automation
32-, 64-, 128-, or 256-KB Lighting Systems
In-System-Programmable Flash Industrial Control and Monitoring
8-KB RAM With Retention in All Power Low-Power Wireless Sensor Networks
Modes Consumer Electronics
Hardware Debug Support Health Care
Peripherals
Powerful Five-Channel DMA
IEEE 802.15.4 MAC Timer, General-Purpose
Timers (One 16-Bit, Two 8-Bit)
IR Generation Circuitry
32-kHz Sleep Timer With Capture
CSMA/CA Hardware Support
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
RemoTI, SmartRF, Z-Stack are trademarks of Texas Instruments.
2
IAR Embedded Workbench is a trademark of IAR Systems AB.
3
ZigBee is a registered trademark of the ZigBee Alliance.
4
All other trademarks are the property of their respective owners.
5
PRODUCTION DATA information is current as of publication date. Copyright 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CC2530F32, CC2530F64, CC2530F128, CC2530F256
SWRS081A APRIL 2009 REVISED APRIL 2009 .......................................................................................................................................................... www.ti.com
DESCRIPTION
The CC2530 is a true system-on-chip (SoC) solution for IEEE 802.15.4, Zigbee and RF4CE applications. It
enables robust network nodes to be built with very low total bill-of-material costs. The CC2530 combines the
excellent performance of a leading RF transceiver with an industry-standard enhanced 8051 MCU, in-system
programmable flash memory, 8-KB RAM, and many other powerful features. The CC2530 comes in four different
flash versions: CC2530F32/64/128/256, with 32/64/128/256 KB of flash memory, respectively. The CC2530 has
various operating modes, making it highly suited for systems where ultralow power consumption is required.
Short transition times between operating modes further ensure low energy consumption.
Combined with the industry-leading and golden-unit-status ZigBee protocol stack (Z-StackTM) from Texas
Instruments, the CC2530F256 provides a robust and complete ZigBee solution.
Combined with the golden-unit-status RemoTI stack from Texas Instruments, the CC2530F64 and higher provide
a robust and complete ZigBee RF4CE remote-control solution.
DIGITAL RESET WATCHDOG ON-CHIP VOLTAGE VDD (2 V3.6 V)
ANALOG TIMER REGULATOR DCOUPL
MIXED 32-MHz
CRYSTAL OSC HIGH-SPEED POWER ON RESET
RC-OSC BROWN OUT
RESET_N 32.768-kHz 32-kHz SLEEP TIMER
CRYSTAL OSC RC-OSC SLEEP MODE CONTROLLER
XOSC_Q2
XOSC_Q1 DEBUG CLOCK MUX and
INTERFACE CALIBRATION
P2_4
P2_3 DMA 8051 CPU MEMORY 32/64/128/256-KB
P2_2 CORE ARBITRATOR FLASH
P2_1
P2_0 8-KB SRAM
P1_7 I/O CONTROLLER IRQ CTRL FLASH WRITE
P1_6 FREQUENCY
P1_5 SYNTHESIZERADCAESRADIO REGISTERS
P1_4 AUDIO/DC ENCRYPTION
P1_3 FIFO and FRAME CONTROL8 CHANNELSCSMA/CA STROBE
P1_2 AND PROCESSOR
P1_1 DECRYPTION
P1_0 RADIO DATA INTERFACE
USART 1
P0_7
P0_6 USART 2 DEMODULATOR AGC MODULATOR
P0_5
P0_4 TIMER 1 (16-Bit)
P0_3 TIMER 2
P0_2
P0_1 (IEEE 802.15.4 MAC TIMER)
P0_0
TIMER 3 (8-Bit)
RECEIVE TRANSMIT
CHAIN CHAIN
TIMER 4 (8-Bit)
RF_P RF_N
B0300-02
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
MIN MAX UNIT
Supply voltage All supply pins must have the same voltage 0.3 3.9 V
Voltage on any digital pin
Input RF level All pads, according to human-body model, JEDEC STD 22, method 0.3 VDD + 0.3, V
Storage temperature range A114 3.9
According to charged-device model, JEDEC STD 22, method C101
ESD (2) 10 dBm
40 125 C
2 kV
500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) CAUTION: ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
Operating ambient temperature range, TA 40 125 C
Operating supply voltage
2 3.6 V
ELECTRICAL CHARACTERISTICS
Measured on Texas Instruments CC2530 EM reference design with TA = 25C and VDD = 3 V, unless otherwise noted.
Boldface limits apply over the entire operating range, TA = 40C to 125C, VDD = 2 V to 3.6 V, and fc = 2394 MHz to
2507 MHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Icore Core current consumption
Digital regulator on. 16-MHz RCOSC running. No radio, 3.4 mA
crystals, or peripherals active.
Medium CPU activity: normal flash access(1), no RAM access 6.5 8.9 mA
32-MHz XOSC running. No radio or peripherals active. 20.5 mA
Medium CPU activity: normal flash access(1), no RAM access
24.3 29.6 mA
32-MHz XOSC running, radio in RX mode, 50-dBm input
power, no peripherals active, CPU idle 28.7 mA
32-MHz XOSC running, radio in RX mode at -100-dBm input 33.5 39.6 mA
power (waiting for signal), no peripherals active, CPU idle
0.2 0.3 mA
32-MHz XOSC running, radio in TX mode, 1-dBm output
power, no peripherals active, CPU idle 1 2 A
32-MHz XOSC running, radio in TX mode, 4.5-dBm output 0.4 1 A
power, no peripherals active, CPU idle
Power mode 1. Digital regulator on; 16-MHz RCOSC and
32-MHz crystal oscillator off; 32.768-kHz XOSC, POR, BOD
and sleep timer active; RAM and register retention
Power mode 2. Digital regulator off; 16-MHz RCOSC and
32-MHz crystal oscillator off; 32.768-kHz XOSC, POR, and
sleep timer active; RAM and register retention
Power mode 3. Digital regulator off; no clocks; POR active;
RAM and register retention
(1) Normal flash access means that the code used exceeds the cache storage, so cache misses happen frequently.
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ELECTRICAL CHARACTERISTICS (continued)
Measured on Texas Instruments CC2530 EM reference design with TA = 25C and VDD = 3 V, unless otherwise noted.
Boldface limits apply over the entire operating range, TA = 40C to 125C, VDD = 2 V to 3.6 V, and fc = 2394 MHz to
2507 MHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Peripheral Current Consumption (Adds to core current Icore for each peripheral unit activated)
Timer 1 Timer running, 32-MHz XOSC used 90 A
Timer 2 Timer running, 32-MHz XOSC used 90 A
Timer 3 Timer running, 32-MHz XOSC used 60 A
Iperi Timer 4 Timer running, 32-MHz XOSC used 70 A
Including 32.753-kHz RCOSC
Sleep timer 0.6 A
ADC When converting 1.2 mA
Flash Erase 1 mA
Burst write peak current
6 mA
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GENERAL CHARACTERISTICS
Measured on Texas Instruments CC2530 EM reference design with TA = 25C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
WAKE-UP AND TIMING
Power mode 1 active Digital regulator on, 16-MHz RCOSC and 32-MHz crystal 4 s
oscillator off. Start-up of 16-MHz RCOSC
Power mode 2 or 3 active Digital regulator off, 16-MHz RCOSC and 32-MHz crystal 0.1 ms
oscillator off. Start-up of regulator and 16-MHz RCOSC
Active TX or RX Initially running on 16-MHz RCOSC, with 32-MHz XOSC 0.5 ms
OFF
192 s
With 32-MHz XOSC initially on
RX/TX and TX/RX turnaround 192 s
RADIO PART
RF frequency range Programmable in 1-MHz steps, 5 MHz between channels 2394 2507 MHz
for compliance with [1]
Radio baud rate As defined by [1] 250 kbps
Radio chip rate As defined by [1] 2 MChip/s
RF RECEIVE SECTION
Measured on Texas Instruments CC2530 EM reference design with TA = 25C, VDD = 3 V, and fc = 2440 MHz, unless
otherwise noted.
Boldface limits apply over the entire operating range, TA = 40C to 125C, VDD = 2 V to 3.6 V, and fc = 2394 MHz to
2507 MHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
dBm
Receiver sensitivity PER = 1%, as specified by [1] 97 92
[1] requires 85 dBm 88
Saturation (maximum input level)
PER = 1%, as specified by [1] 10 dBm
Adjacent-channel rejection, 5-MHz [1] requires 20 dBm
channel spacing 49 dB
Wanted signal 82 dBm, adjacent modulated channel at
Adjacent-channel rejection, 5-MHz 5 MHz, PER = 1 %, as specified by [1]. 49 dB
channel spacing [1] requires 0 dB
57 dB
Alternate-channel rejection, 10-MHz Wanted signal 82 dBm, adjacent modulated channel at
channel spacing 5 MHz, PER = 1 %, as specified by [1]. 57 dB
[1] requires 0 dB
Alternate-channel rejection, 10-MHz 57 dB
channel spacing Wanted signal 82 dBm, adjacent modulated channel at
10 MHz, PER = 1%, as specified by [1] 57
Channel rejection [1] requires 30 dB
20 MHz 3 dB
20 MHz Wanted signal 82 dBm, adjacent modulated channel at
10 MHz, PER = 1 %, as specified by [1]
Co-channel rejection [1] requires 30 dB
Blocking/desensitization Wanted signal at 82 dBm. Undesired signal is an IEEE
5 MHz from band edge 802.15.4 modulated channel, stepped through all channels
10 MHz from band edge from 2405 to 2480 MHz. Signal level for PER = 1%.
20 MHz from band edge
50 MHz from band edge Wanted signal at 82 dBm. Undesired signal is 802.15.4
5 MHz from band edge modulated at the same frequency as the desired signal. Signal
10 MHz from band edge level for PER = 1%.
20 MHz from band edge
50 MHz from band edge Wanted signal 3 dB above the sensitivity level, CW jammer, 33
PER = 1%. Measured according to EN 300 440 class 2.
33
32
31 dBm
35
35
34
34
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RF RECEIVE SECTION (continued)
Measured on Texas Instruments CC2530 EM reference design with TA = 25C, VDD = 3 V, and fc = 2440 MHz, unless
otherwise noted.
Boldface limits apply over the entire operating range, TA = 40C to 125C, VDD = 2 V to 3.6 V, and fc = 2394 MHz to
2507 MHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Spurious emission. Only largest spurious Conducted measurement with a 50- single-ended load. < dBm
emission stated within each band. Suitable for systems targeting compliance with EN 300 328, 80
EN 300 440, FCC CFR47 Part 15 and ARIB STD-T-66. 57 ppm
30 MHz1000 MHz ppm
1 GHz12.75 GHz 150
Frequency error tolerance(1) [1] requires minimum 80 ppm 1000
Symbol rate error tolerance(2) [1] requires minimum 80 ppm
(1) Difference between center frequency of the received RF signal and local oscillator frequency.
(2) Difference between incoming symbol rate and the internally generated symbol rate
RF TRANSMIT SECTION
Measured on Texas Instruments CC2530 EM reference design with TA = 25C, VDD = 3 V and fc = 2440 MHz, unless
otherwise noted.
Boldface limits apply over the entire operating range, TA = 40C to 125C, VDD = 2 V to 3.6 V and fc = 2394 MHz to 2507
MHz.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Delivered to a single-ended 50- load through a balun using dBm
Nominal output power maximum-recommended output-power setting 0 4.5 8 dB
[1] requires minimum 3 dBm
Programmable output power 8 10 dBm
range Max recommended output power setting(1)
Spurious emissions 25 MHz1000 MHz (outside restricted bands) 32
Measured conducted 25 MHz2400 MHz (within FCC restricted bands)
according to stated 25 MHz1000 MHz (within ETSI restricted bands) 60
regulations. Only largest 18001900 MHz (ETSI restricted band) 60
spurious emission stated 51505300 MHz (ETSI restricted band) 60
within each band. At 2 fc and 3 fc (FCC restricted band) 57
At 2 fc and 3 fc (ETSI EN 300-440 and EN 300-328)(2) 55
1 GHz12.75 GHz (outside restricted bands) 42
At 2483.5 MHz and above (FCC restricted band) 31
53
fc= 2480 MHz(3)
42
Error vector magnitude (EVM) Measured as defined by [1] using maximum-recommended
Optimum load impedance output-power setting 2%
[1] requires maximum 35%.
69 + j29
Differential impedance as seen from the RF port (RF_P and RF_N)
towards the antenna
(1) Texas Instruments CC2530 EM reference design is suitable for systems targeting compliance with EN 300 328, EN 300 440, FCC
CFR47 Part 15 and ARIB STD-T-66.
(2) Margins for passing conducted requirements at the third harmonic can be improved by using a simple band-pass filter connected
between matching network and RF connector (1.8 pF in parallel with 1.6 nH); this filter must be connected to a good RF ground.
(3) Margins for passing FCC requirements at 2483.5 MHz and above when transmitting at 2480 MHz can be improved by using a lower
output-power setting or having less than 100% duty cycle.
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32-MHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2530 EM reference design with TA = 25C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Crystal frequency 32 MHz
Crystal frequency accuracy 40 40 ppm
requirement (1)
ESR Equivalent series resistance 6 60
C0 Crystal shunt capacitance 1 7 pF
10 16 pF
CL Crystal load capacitance
0.3 ms
Start-up time
The crystal oscillator must be in power down for a
guard time before it is used again. This
Power-down guard time requirement is valid for all modes of operation. The 3 ms
need for power-down guard time can vary with
crystal type and load.
(1) Including aging and temperature dependency, as specified by [1]
32.768-kHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2530 EM reference design with TA = 25C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Crystal frequency 32.768 kHz
Crystal frequency accuracy 40 40 ppm
requirement (1)
ESR Equivalent series resistance 40 130
C0 Crystal shunt capacitance 0.9 2 pF
CL Crystal load capacitance 12 16 pF
Start-up time 0.4 s
(1) Including aging and temperature dependency, as specified by [1]
32-kHz RC OSCILLATOR
Measured on Texas Instruments CC2530 EM reference design with TA = 25C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Calibrated frequency(1)
32.753 kHz
Frequency accuracy after calibration 0.2% %/C
Temperature coefficient(2) 0.4 %/V
Supply-voltage coefficient(3) 3 ms
Calibration time(4) 2
(1) The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.
(2) Frequency drift when temperature changes after calibration
(3) Frequency drift when supply voltage changes after calibration
(4) When the 32-kHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC32K_CALDIS is 0.
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16-MHz RC OSCILLATOR
Measured on Texas Instruments CC2530 EM reference design with TA = 25C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Frequency (1)
16 MHz
Uncalibrated frequency accuracy 18%
Calibrated frequency accuracy 0.6% 1%
Start-up time 10 s
Initial calibration time(2)
50 s
(1) The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.
(2) When the 16-MHz RC oscillator is enabled, it is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator
is performed while SLEEPCMD.OSC_PD is set to 0.
RSSI/CCA CHARACTERISTICS
Measured on Texas Instruments CC2530 EM reference design with TA = 25C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RSSI range 100 dB
Absolute uncalibrated RSSI/CCA accuracy 4 dB
RSSI/CCA offset(1)
73 dB
Step size (LSB value) 1 dB
(1) Real RSSI = Register value offset
FREQEST CHARACTERISTICS
Measured on Texas Instruments CC2530 EM reference design with TA = 25C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQEST range 250 kHz
FREQEST accuracy 40 kHz
FREQEST offset(1)
20 kHz
Step size (LSB value) 7.8 kHz
(1) Real FREQEST = Register value offset
FREQUENCY SYNTHESIZER CHARACTERISTICS
Measured on Texas Instruments CC2530 EM reference design with TA = 25C, VDD = 3 V and fc = 2440 MHz, unless
otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Phase noise, unmodulated carrier At 1-MHz offset from carrier
At 2-MHz offset from carrier 110
At 5-MHz offset from carrier
117 dBc/Hz
122
ANALOG TEMPERATURE SENSOR
Measured on Texas Instruments CC2530 EM reference design with TA = 25C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output at 25C 1480 12-bit ADC
Temperature coefficient 4.5 /10C
Voltage coefficient Measured using integrated ADC using 1 /0.1 V
internal bandgap voltage reference and
Initial accuracy without calibration maximum resolution 10 C
Accuracy using 1-point calibration (entire 5 C
temperature range)
Current consumption when enabled (ADC 0.5 mA
current not included)
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ADC CHARACTERISTICS
TA = 25C and VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
Input voltage VDD is voltage on AVDD5 pin 0 VDD V
V
External reference voltage VDD is voltage on AVDD5 pin 0 VDD k
V
External reference voltage differential VDD is voltage on AVDD5 pin 0 VDD
bits
Input resistance, signal Using 4-MHz clock speed 197
Full-scale signal(1) Peak-to-peak, defines 0 dBFS kHz
2.97 dB
Single-ended input, 7-bit setting 5.7 dB
Single-ended input, 9-bit setting 7.5 dB
Single-ended input, 10-bit setting 9.3
ENOB(1) Effective number of bits Single-ended input, 12-bit setting 10.8
Differential input, 7-bit setting
6.5
Differential input, 9-bit setting 8.3
Differential input, 10-bit setting 10.0
Differential input, 12-bit setting 11.5
Useful power bandwidth 7-bit setting, both single and differential 020
Single-ended input, 12-bit setting, 6 dBFS 75.
2
THD (1) Total harmonic distortion
Differential input, 12-bit setting, 6 dBFS 86.
6
Single-ended input, 12-bit setting 70.2
Differential input, 12-bit setting
Signal to nonharmonic ratio(1) Single-ended input, 12-bit setting, 6 dBFS 79.3
Differential input, 12-bit setting, 6 dBFS
Differential input, 12-bit setting, 1-kHz sine (0 78.8
dBFS), limited by ADC resolution
Single-ended input, 12-bit setting, 1-kHz sine (0 88.9
dBFS), limited by ADC resolution
CMRR Common-mode rejection ratio Midscale >84
Crosstalk
DNL (1) Offset 12-bit setting, mean >84 dB
INL (1) Gain error 12-bit setting, maximum
Differential nonlinearity 12-bit setting, mean 3 mV
12-bit setting, maximum
Integral nonlinearity Single-ended input, 7-bit setting 0.68 %
Single-ended input, 9-bit setting
Single-ended input, 10-bit setting 0.05
Single-ended input, 12-bit setting LSB
Differential input, 7-bit setting
Differential input, 9-bit setting 0.9
Differential input, 10-bit setting
Differential input, 12-bit setting 4.6
7-bit setting LSB
9-bit setting
10-bit setting 13.3
12-bit setting
35.4
46.8
57.5
SINAD (1) Signal-to-noise-and-distortion 66.6
(THD+N) dB
40.7
51.6
61.8
70.8
20
Conversion time 36
s
Power consumption
Internal reference voltage 68
132
1.2 mA
1.15 V
(1) Measured with 300-Hz sine-wave input and VDD as reference.
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ADC CHARACTERISTICS (continued) TEST CONDITIONS MIN TYP MAX UNIT
TA = 25C and VDD = 3 V, unless otherwise noted. 4 mV/V
PARAMETER
0.4 mV/10C
Internal reference VDD coefficient
Internal reference temperature coefficient
CONTROL INPUT AC CHARACTERISTICS
TA = 40C to 125C, VDD = 2 V to 3.6 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
16 32 MHz
System clock, fSYSCLK The undivided system clock is 32 MHz when crystal oscillator is used.
tSYSCLK = 1/fSYSCLK The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
RESET_N low duration See item 1, Figure 1. This is the shortest pulse that is recognized as 1 s
a complete reset pin request. Note that shorter pulses may be
recognized but might not lead to complete reset of all modules within
the chip.
Interrupt pulse duration See item 2, Figure 1.This is the shortest pulse that is recognized as 20 ns
an interrupt request.
RESET_N 1 2
Px.n
T0299-01
Figure 1. Control Input AC Characteristics
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SPI AC CHARACTERISTICS
TA = 40C to 125C, VDD = 2 V to 3.6 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t1 SCK period Master, Rx and Tx 250 ns
SCK duty cycle Master
50%
t2 SSN low to SCK Master 63 ns
t3 SCK to SSN high Master
t4 MO early out Master, load = 10 pF 63 ns
t7 MO late out Master, load 10 = pF
t6 MI setup Master 7 ns
t5 MI hold Master
t1 SCK period Slave, Rx and Tx 10 ns
Slave
SCK duty cycle 90 ns
10 ns
250 ns
50%
t2 SSN low to SCK Slave 63 ns
t3 SCK to SSN high Slave
t6 MO setup Slave 63 ns
t5 MO hold Slave
t5 MI late out Slave, load = 10 pF 35 ns
Master, Tx only
10 ns
95 ns
8
Operating frequency Master, Rx and Tx 4
Slave, Rx only MHz
8
Slave, Rx and Tx 4
t1
SCK
t2 t3
SSN
MO t4 t7
(Master Out,
Slave In)
MI
(Master In,
Slave Out)
t5 T0439-01
t6
Figure 2. SPI AC Characteristics
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DEBUG INTERFACE AC CHARACTERISTICS
TA = 40C to 125C, VDD = 2 V to 3.6 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fclk_dbg Debug clock frequency (see Figure 3) 12 MHz
t1 Allowed high pulse on clock (see Figure 3)
t2 Allowed low pulse on clock (see Figure 3) 35 ns
EXT_RESET_N low to first falling edge on
t3 debug clock (see Figure 4) 35 ns
167 ns
t4 Falling edge on clock to EXT_RESET_N high 83 ns
(see Figure 4)
t5 EXT_RESET_N high to first debug command 83 ns
(see Figure 4)
t6 Debug data setup (see Figure 5) 2 ns
t7 Debug data hold (see Figure 5) 4 ns
t8 Clock-to-data delay (see Figure 5) Load = 10 pF 30 ns
Time
DEBUG_ CLK
P2_2
t1 t2
1/fclk_dbg
Figure 3. Debug Clock Basic Timing T0436-01
Time
DEBUG_ CLK
P2_2
RESET_N
t3 t4 t5
T0437-01
Figure 4. Data Setup and Hold Timing
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Time
DEBUG_ CLK
P2_2
DEBUG_DATA
(to CC2530)
P2_1
DEBUG_DATA
(from CC2530)
P2_1
t6 t7 t8
Figure 5. Debug Enable Timing T0438-01
TIMER INPUTS AC CHARACTERISTICS MIN TYP MAX UNIT
tSYSCLK
TA = 40C to 125C, VDD = 2 V to 3.6 V, unless otherwise noted.
1.5
PARAMETER TEST CONDITIONS
Synchronizers determine the shortest input pulse that can be
Input capture pulse duration recognized. The synchronizers operate at the current system
clock rate (16 or 32 MHz).
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DC CHARACTERISTICS
TA = 25C, VDD = 3 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Logic-0 input voltage 0.5 V
Logic-1 input voltage 2.5 V
Logic-0 input current Input equals 0 V 50 50 nA
Logic-1 input current Input equals VDD 50 50 nA
I/O-pin pullup and pulldown resistors 20 k
Logic-0 output voltage, 4-mA pins Output load 4 mA 0.5 V
Logic-1 output voltage, 4-mA pins Output load 4 mA 2.4 V
Logic-0 output voltage, 20-mA pins Output load 20 mA 0.5 V
Logic-1 output voltage, 20-mA pins Output load 20 mA 2.4 V
DEVICE INFORMATION
PIN DESCRIPTIONS
The CC2530 pinout is shown in Figure 6 and a short description of the pins follows.
CC2530
RHA Package
(Top View)
DCOUPL
DVDD1
P1_6
P1_7
P2_0
P2_1
P2_2
P2_3/XOSC32K_Q2
P2_4/XOSC32K_Q1
AVDD6
GND 40 39 38 37 36 35 34 33 32 31 RBIAS
GND 1 30 AVDD4
GND AVDD1
GND 2 29 AVDD2
P1_5 RF_N
P1_4 3 28 RF_P
P1_3 AVDD3
P1_2 4 27 XOSC_Q2
P1_1 XOSC_Q1
DVDD2 5 GND 26 AVDD5
6 Ground Pad 25
7 24
8 23
9 22
P1_0
P0_710 21
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
RESET_N
11 12 13 14 15 16 17 18 19 20
P0076-02
NOTE: The exposed ground pad must be connected to a solid ground plane, as this is the ground connection for the chip.
Figure 6. Pinout Top View
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PIN NAME PIN PIN TYPE Pin Descriptions
AVDD1 28 Power (analog)
AVDD2 27 Power (analog) DESCRIPTION
AVDD3 24 Power (analog) 2-V3.6-V analog power-supply connection
AVDD4 29 Power (analog) 2-V3.6-V analog power-supply connection
AVDD5 21 Power (analog) 2-V3.6-V analog power-supply connection
AVDD6 31 Power (analog) 2-V3.6-V analog power-supply connection
DCOUPL 40 Power (digital) 2-V3.6-V analog power-supply connection
DVDD1 39 Power (digital) 2-V3.6-V analog power-supply connection
DVDD2 10 Power (digital) 1.8-V digital power-supply decoupling. Do not use for supplying external circuits.
GND -- Ground 2-V3.6-V digital power-supply connection
GND 1, 2, 3, 4 Unused pins 2-V3.6-V digital power-supply connection
P0_0 19 Digital I/O The ground pad must be connected to a solid ground plane.
P0_1 18 Digital I/O Connect to GND
P0_2 17 Digital I/O Port 0.0
P0_3 16 Digital I/O Port 0.1
P0_4 15 Digital I/O Port 0.2
P0_5 14 Digital I/O Port 0.3
P0_6 13 Digital I/O Port 0.4
P0_7 12 Digital I/O Port 0.5
P1_0 11 Digital I/O Port 0.6
P1_1 9 Digital I/O Port 0.7
P1_2 8 Digital I/O Port 1.0 20-mA drive capability
P1_3 7 Digital I/O Port 1.1 20-mA drive capability
P1_4 6 Digital I/O Port 1.2
P1_5 5 Digital I/O Port 1.3
P1_6 38 Digital I/O Port 1.4
P1_7 37 Digital I/O Port 1.5
P2_0 36 Digital I/O Port 1.6
P2_1 35 Digital I/O Port 1.7
P2_2 34 Digital I/O Port 2.0
P2_3/ Digital I/O, Port 2.1
XOSC32K_Q2 33 Analog I/O Port 2.2
P2_4/ Digital I/O, Port 2.3/32.768 kHz XOSC
XOSC32K_Q1 32 Analog I/O
RBIAS Analog I/O Port 2.4/32.768 kHz XOSC
RESET_N 30 Digital input
20 External precision bias resistor for reference current
RF_N RF I/O Reset, active-low
26 Negative RF input signal to LNA during RX
RF_P RF I/O Negative RF output signal from PA during TX
25 Positive RF input signal to LNA during RX
XOSC_Q1 Analog I/O Positive RF output signal from PA during TX
XOSC_Q2 22 Analog I/O 32-MHz crystal oscillator pin 1 or external-clock input
23 32-MHz crystal oscillator pin 2
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CIRCUIT DESCRIPTION
DIGITAL
ANALOG
MIXED
RESET_N RESET WATCHDOG ON-CHIP VOLTAGE VDD (2 V3.6 V)
TIMER REGULATOR DCOUPL
XOSC_Q2
XOSC_Q1 32-MHz CLOCK MUX POWER ON RESET
CRYSTAL OSC and BROWN OUT
P2_4
P2_3 32.768-kHz CALIBRATION SFR Bus
P2_2 CRYSTAL OSC
P2_1 SLEEP TIMER
P2_0 DEBUG
INTERFACE HIGH- 32-kHz POWER MANAGEMENT CONTROLLER
P1_7 SPEED RC-OSC
P1_6 RC-OSC
P1_5
P1_4 8051 CPU PDATA RAM 8-KB SRAM
P1_3 CORE XRAM
P1_2 IRAM
P1_1 SFR MEMORY
P1_0 ARBITRATOR
P0_7 FLASH 32/64/128/256-KB
P0_6 FLASH
P0_5
P0_4 DMA UNIFIED
P0_3
P0_2 IRQ CTRL FLASH CTRL
P0_1
P0_0 I/O CONTROLLER ADC AES RADIO REGISTERS
AUDIO/DC ENCRYPTION CSMA/CA STROBE PROCESSOR
AND
DECRYPTION
RADIO DATA INTERFACE FIFO and FRAME CONTROL
USART 0 SFR Bus AGC DEMODULATOR SYNTH MODULATOR
USART 1
TIMER 1 (16-Bit) RECEIVE FREQUENCY TRANSMIT
CHAIN SYNTHESIZER CHAIN
TIMER 2
(IEEE 802.15.4 MAC TIMER)
TIMER 3 (8-Bit)
TIMER 4 (8-Bit) RF_P RF_N
Figure 7. CC2530 Block Diagram B0301-02
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A block diagram of the CC2530 is shown in Figure 7. The modules can be roughly divided into one of three
categories: CPU- and memory-related modules; modules related to peripherals, clocks, and power management;
and radio-related modules. In the following subsections, a short description of each module that appears in
Figure 7 is given.
For more details about the modules and their usage, see the corresponding chapters in the CC253x User's
Guide (SWRU191).
CPU and Memory
The 8051 CPU core used in the CC253x device family is a single-cycle 8051-compatible core. It has three
different memory-access buses (SFR, DATA and CODE/XDATA) with single-cycle access to SFR, DATA, and
the main SRAM. It also includes a debug interface and an 18-input extended interrupt unit.
The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. Any interrupt service request is serviced also when the device is
in idle mode by going back to active mode. Some interrupts can also wake up the device from sleep mode
(power modes 13).
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory access points, access
of which can map to one of three physical memories: an 8-KB SRAM, flash memory, and XREG/SFR registers. It
is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
physical memory.
The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The 8-KB
SRAM is an ultralow-power SRAM that retains its contents even when the digital part is powered off (power
modes 2 and 3). This is an important feature for low-power applications.
The 32/64/128/256 KB flash block provides in-circuit programmable non-volatile program memory for the
device, and maps into the CODE and XDATA memory spaces. In addition to holding program code and
constants, the non-volatile memory allows the application to save data that must be preserved such that it is
available after restarting the device. Using this feature one can, e.g., use saved network-specific data to avoid
the need for a full start-up and network find-and-join process .
Clocks and Power Management
The digital core and peripherals are powered by a 1.8-V low-dropout voltage regulator. It provides power
management functionality that enables low power operation for long battery life using different power modes.
Five different reset sources exist to reset the device.
Peripherals
The CC2530 includes many different peripherals that allow the application designer to develop advanced
applications.
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to perform an erasure of the entire flash memory, control which
oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051
core, set code breakpoints, and single-step through instructions in the code. Using these techniques, it is
possible to perform in-circuit debugging and external flash programming elegantly.
The device contains flash memory for storage of program code. The flash memory is programmable from the
user software and through the debug interface. The flash controller handles writing and erasing the embedded
flash memory. The flash controller allows page-wise erasure and 4-bytewise programming.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
as an input or output and if a pullup or pulldown resistor in the pad is connected. CPU interrupts can be enabled
on each pin individually. Each peripheral that connects to the I/O pins can choose between two different I/O pin
locations to ensure flexibility in various applications.
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A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors anywhere in
memory. Many of the hardware peripherals (AES core, flash controller, USARTs, timers, ADC interface) achieve
highly efficient operation by using the DMA controller for data transfers between SFR or XREG addresses and
flash/SRAM.
Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR Generation Mode where it counts Timer 3 periods and the output is ANDed with
the output of Timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
The MAC timer (Timer 2) is specially designed for supporting an IEEE 802.15.4 MAC or other time-slotted
protocol in software. The timer has a configurable timer period and an 8-bit overflow counter that can be used to
keep track of the number of periods that have transpired. A 16-bit capture register is also used to record the
exact time at which a start-of-frame delimiter is received/transmitted or the exact time at which transmission
ends, as well as a 16-bit output compare register that can produce various command strobes (start RX, start TX,
etc.) at specific times to the radio modules.
Timer 3 and Timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable
prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of
the counter channels can be used as a PWM output.
The sleep timer is an ultralow-power timer that counts 32-kHz crystal oscillator or 32-kHz RC oscillator periods.
The sleep timer runs continuously in all operating modes except power mode 3. Typical applications of this timer
are as a real-time counter or as a wake-up timer to get out of power mode 1 or 2.
The ADC supports 7 to 12 bits of resolution in a 30 kHz to 4 kHz bandwidth, respectively. DC and audio
conversions with up to eight input channels (Port 0) are possible. The inputs can be selected as single-ended or
differential. The reference voltage can be internal, AVDD, or a single-ended or differential external signal. The
ADC also has a temperature-sensor input channel. The ADC can automate the process of periodic sampling or
conversion over a sequence of channels.
The random-number generator uses a 16-bit LFSR to generate pseudorandom numbers, which can be read by
the CPU or used directly by the command strobe processor. The random numbers can, e.g., be used to generate
random keys used for security.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The core is able to support the AES operations required by IEEE 802.15.4 MAC security, the
ZigBee network layer, and the application layer.
A built-in watchdog timer allows the CC2530 to reset itself in case the firmware hangs. When enabled by
software, the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out. It can
alternatively be configured for use as a general 32-kHz timer.
USART 0 and USART 1 are each configurable as either a SPI master/slave or a UART. They provide double
buffering on both RX and TX and hardware flow control and are thus well suited to high-throughput full-duplex
applications. Each has its own high-precision baud-rate generator, thus leaving the ordinary timers free for other
uses.
Radio
The CC2530 features an IEEE 802.15.4-compliant radio transceiver. The RF core controls the analog radio
modules. In addition, it provides an interface between the MCU and the radio which makes it possible to issue
commands, read status, and automate and sequence radio events. The radio also includes a packet-filtering and
address-recognition module.
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TYPICAL CHARACTERISTICS
RX CURRENT (100 dBm INPUT) TX CURRENT (TXPOWER = 0xF5)
vs vs
TEMPERATURE TEMPERATURE
28 36
27
35
26
RX Current - mA TX Current - mA
25 34
24
33
23
22 0 40 80 120 32 0 40 80 120
-40 -40
T - Temperature - C G001 T - Temperature - C G002
26.0 34.4
Figure 8. Figure 9.
RX CURRENT (100 dBm INPUT) TX CURRENT (TXPOWER = 0xF5)
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
25.5 34.2
RX Current - mA 25.0 TX Current - mA 34.0
24.5 33.8
24.0 2.4 2.8 3.2 3.6 33.6 2.4 2.8 3.2 3.6
2.0 2.0
G003 G004
VCC - Supply Voltage - V VCC - Supply Voltage - V
Figure 10. Figure 11.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT POWER (TXPOWER = 0xF5) INTERFERER REJECTION (802.15.4 INTERFERER)
vs vs
FREQUENCY INTERFERER FREQUENCY (CARRIER AT 82 dBm, 2440
MHz)
6.0
75
PO - Output Power - dBm 5.5 Interferer Rejection - dB
50
5.0
25
4.5
0
4.0
3.5 -25 2420 2440 2460 2480
2394 2414 2434 2454 2474 2494 2400
Interferer Frequency - MHz G006
f - Frequency - MHz 8
Figure 13.
G005
OUTPUT POWER (TXPOWER = 0xF5)
Figure 12. vs
SENSITIVITY TEMPERATURE
vs
TEMPERATURE
-92
-93
6
-94 PO - Output Power - dBm
Sensitivity - dBm -95 4
-96 2
-97
0
-98
-99 0 40 80 120 -2 0 40 80 120
-40 -40
G007 G008
T - Temperature - C T - Temperature - C
Figure 14. Figure 15.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT POWER (TXPOWER = 0xF5) SENSITIVITY
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
5.0 -94
4.8 -95
PO - Output Power - dBm
Sensitivity - dBm
-96
4.6
-97
4.4
-98
4.2
-99
4.0 2.4 2.8 3.2 3.6 -100 2.4 2.8 3.2 3.6
2.0 2.0
G009 G010
VCC - Supply Voltage - V VCC - Supply Voltage - V
Figure 16. Figure 17.
Table 1. Recommended Output Power Settings(1)
TXPOWER Register Setting Typical Output Power (dBm) Typical Current Consumption (mA)
0xF5 4.5 34
0xE5 2.5 31
0xD5 1 29
0xC5 0.5 28
0xB5 1.5 27
0xA5 3 27
0x95 4 26
0x85 6 26
0x75 8 25
0x65 10 25
0x55 12 25
0x45 14 25
0x35 16 25
0x25 18 24
0x15 20 24
0x05 22 23
28 23
0x05 and TXCTRL = 0x09
(1) Measured on Texas Instruments CC2530 EM reference design with TA = 25C, VDD = 3 V and fc = 2440 MHz, unless otherwise noted.
See [2] for recommended register settings.
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APPLICATION INFORMATION
Few external components are required for the operation of the CC2530. A typical application circuit is shown in
Figure 18. Typical values and description of external components are shown in Table 2.
2-V to 3.6-V Optional 32-kHz Crystal
Power Supply
C331
C401 XTAL2
C321
DCOUPL 40 R301
DVDD1 39
1 GND P1_6 38 RBIAS 30 C251 L252 Antenna
2 GND P1_7 37 AVDD4 29 C252 (50 W)
3 GND P2_0 36 AVDD1 28
4 GND P2_1 35 AVDD2 27 C253
5 P1_5 P2_2 34
6 P1_4 RF_N 26
7 P1_3 P2_3/XOSC32K_Q2 33 RF_P 25
8 P1_2 P2_4/XOSC32K_Q1 32 AVDD3 24
9 P1_1 XOSC_Q2 23
10 DVDD2 AVDD6 31 XOSC_Q1 22
AVDD5 21
CC2530 C261
DIE ATTACH PAD
L261
C262
11 P1_0
12 P0_7
13 P0_6
14 P0_5
15 P0_4
16 P0_3
17 P0_2
18 P0_1
19 P0_0
20 RESET_N
XTAL1
Power Supply Decoupling Capacitors are Not Shown C221 C231
Digital I/O Not Connected
S0383-01
Figure 18. CC2530 Application Circuit
Table 2. Overview of External Components (Excluding Supply Decoupling
Capacitors)
Component Description Value
C251 Part of the RF matching network 18 pF
C261 Part of the RF matching network 18 pF
L252 Part of the RF matching network 2 nH
L261 Part of the RF matching network 2 nH
C262 Part of the RF matching network 1 pF
C252 Part of the RF matching network 1 pF
C253 Part of the RF matching network 2.2 pF
C331 32kHz xtal loading capacitor 15 pF
C321 32kHz xtal loading capacitor 15 pF
C231 32MHz xtal loading capacitor 27 pF
C221 32MHz xtal loading capacitor 27 pF
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Table 2. Overview of External Components (Excluding Supply Decoupling
Capacitors) (continued)
Component Description Value
C401 Decoupling capacitor for the internal digital regulator 1 F
R301 Resistor used for internal biasing 56 k
Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The
balun can be implemented using low-cost discrete inductors and capacitors. The recommended balun shown
consists of C262, L261, C252, and L252.
If a balanced antenna such as a folded dipole is used, the balun can be omitted.
Crystal
An external 32-MHz crystal, XTAL1, with two loading capacitors (C221 and C231) is used for the 32-MHz crystal
oscillator. See the 32-MHz Crystal Oscillator section for details. The load capacitance seen by the 32-MHz
crystal is given by:
CL = 1 + Cparasitic
11
C221 + C231
(1)
XTAL2 is an optional 32.768-kHz crystal, with two loading capacitors (C321 and C331) used for the 32.768-kHz
crystal oscillator. The 32.768-kHz crystal oscillator is used in applications where both very low sleep-current
consumption and accurate wake-up times are needed. The load capacitance seen by the 32.768-kHz crystal is
given by:
CL = 1 1 1 + Cparasitic
+
C321 C331
(2)
A series resistor may be used to comply with the ESR requirement.
On-Chip 1.8-V Voltage-Regulator Decoupling
The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor
(C401) for stable operation.
Power-Supply Decoupling and Filtering
Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in an
application. TI provides a compact reference design that should be followed very closely.
References
1. IEEE Std. 802.15.4-2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications
for Low-Rate Wireless Personal Area Networks (LR-WPANs)
http://standards.ieee.org/getieee802/download/802.15.4-2006.pdf
2. CC253x User's Guide CC253x System-on-Chip Solution for 2.4 GHz IEEE 802.15.4 and ZigBee
Applications (SWRU191)
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Additional Information
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24 Submit Documentation Feedback Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): CC2530F32 CC2530F64 CC2530F128 CC2530F256
PACKAGE OPTION ADDENDUM
www.ti.com 18-May-2009
PACKAGING INFORMATION
Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ACTIVE Type Drawing Qty
CC2530F128RHAR
QFN RHA 40 2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
CC2530F128RHAT no Sb/Br)
CC2530F256RHAR ACTIVE QFN RHA 40 250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
CC2530F256RHAT
ACTIVE QFN RHA 40 2500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
CC2530F32RHAR no Sb/Br)
CC2530F32RHAT
CC2530F64RHAR ACTIVE QFN RHA 40 250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
CC2530F64RHAT no Sb/Br)
PREVIEW QFN RHA 40 2500 TBD Call TI Call TI
PREVIEW QFN RHA
PREVIEW QFN RHA 40 250 TBD Call TI Call TI
PREVIEW QFN RHA
40 2500 TBD Call TI Call TI
40 250 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
www.ti.com PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION 18-May-2009
*All dimensions are nominal
Device Package Package Pins SPQ Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Type Drawing Diameter Width
2500 6.3 6.3 (mm) (mm) Quadra
250 (mm) W1 (mm) 6.3 6.3
CC2530F128RHAR QFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2
CC2530F128RHAT QFN RHA 40 250 6.3 6.3
CC2530F256RHAR QFN RHA 40 330.0 16.4 1.5 12.0 16.0 Q2
CC2530F256RHAT QFN RHA 40
330.0 16.4 1.5 12.0 16.0 Q2
330.0 16.4 1.5 12.0 16.0 Q2
Pack Materials-Page 1
www.ti.com PACKAGE MATERIALS INFORMATION
18-May-2009
*All dimensions are nominal Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
Device QFN 2500 333.2 345.9 28.6
QFN RHA 40 250 333.2 345.9 28.6
CC2530F128RHAR QFN 2500 333.2 345.9 28.6
CC2530F128RHAT QFN RHA 40 250 333.2 345.9 28.6
CC2530F256RHAR
CC2530F256RHAT RHA 40
RHA 40
Pack Materials-Page 2
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Amplifiers dataconverter.ti.com Audio www.ti.com/automotive
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Clocks and Timers interface.ti.com Medical www.ti.com/military
Interface logic.ti.com Military www.ti.com/opticalnetwork
Logic power.ti.com Optical Networking www.ti.com/security
Power Mgmt microcontroller.ti.com Security www.ti.com/telephony
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RFID www.ti.com/lprf Video & Imaging www.ti.com/wireless
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