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CAT1025YI-30-T3

器件型号:CAT1025YI-30-T3
器件类别:电源/电源管理    电源电路   
厂商名称:ON Semiconductor(安森美)
厂商官网:http://www.onsemi.cn
标准:
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器件描述

1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, ROHS COMPLIANT, MO-153, TSSOP-8

参数
是否无铅不含铅
是否Rohs认证符合
厂商名称ON Semiconductor(安森美)
零件包装代码TSSOP
包装说明TSSOP,
针数8
Reach Compliance Codecompliant
ECCN代码EAR99
其他特性RESET THRESHOLD VOLTAGE IS 3.075V; MANUAL RESET INPUT
可调阈值NO
模拟集成电路 - 其他类型POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码R-PDSO-G8
JESD-609代码e3
长度4.4 mm
湿度敏感等级1
信道数量1
功能数量1
端子数量8
最高工作温度85 °C
最低工作温度-40 °C
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)260
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)2.7 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin (Sn)
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
处于峰值回流温度下的最长时间40
宽度3 mm
Base Number Matches1

文档预览

CAT1024, CAT1025
Supervisory Circuits with I C Serial 2k-bit
CMOS EEPROM and Manual Reset
FEATURES
Precision Power Supply Voltage Monitor
— 5 V, 3.3 V and 3 V systems
— Five threshold voltage options
Active High or Low Reset
— Valid reset guaranteed at V
CC
= 1 V
400 kHz I
2
C Bus
2.7 V to 5.5 V Operation
Low power CMOS technology
16-Byte Page Write Buffer
Built-in inadvertent write protection
— WP pin (CAT1025)
1,000,000 Program/Erase cycles
Manual Reset Input
100 year data retention
Industrial and extended temperature ranges
Green packages available with NiPdAu Lead
finished
2
DESCRIPTION
The CAT1024 and CAT1025 are complete memory
and supervisory solutions for microcontroller-based
systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection
are integrated together in low power CMOS techno–
logy. Memory interface is via a 400 kHz I
2
C bus.
The CAT1025 provides a precision V
CC
sense circuit
and two open drain outputs: one (RESET) drives high
¯¯¯¯¯¯
and the other (RESET) drives low whenever V
CC
falls
below the reset threshold voltage. The CAT1025 also
has a Write Protect input (WP). Write operations are
disabled if WP is connected to a logic high.
The CAT1024 also provides a precision V
CC
sense
¯¯¯¯¯¯
circuit, but has only a RESET output and does not
have a Write Protect input.
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5 V, 3.3 V and 3 V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 200 ms after the supply
voltage exceeds the reset threshold level. With both
active high and low reset signals, interface to
microcontrollers and other ICs is simple. In addition,
¯¯¯¯¯¯
the RESET pin or a separate input, ¯¯¯, can be used
MR
as an input for push-button manual reset capability.
The CAT1024/25 memory features a 16-byte page. In
addition, hardware data protection is provided by a
V
CC
sense circuit that prevents writes to memory
whenever V
CC
falls below the reset threshold or until
V
CC
reaches the reset threshold during power up.
Available packages include an 8-pin PDIP and a
surface mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN
and 8-pin MSOP packages. The TDFN package thick-
ness is 0.8 mm maximum. TDFN footprint is 3 x 3 mm.
For Ordering Information details, see page 19.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-3008 Rev. R
CAT1024, CAT1025
BLOCK DIAGRAM
EXTERNA LOAD
L
DOUT
ACK
VCC
VSS
WORDADDRESS
BUFFERS
START/STOP
LOGIC
2kbit
EEPROM
COLUMN
DECODERS
SENSEAMPS
SHIFT REGISTERS
THRESHOLD VOLTAGE OPTION
Part Dash
Number
-45
-42
-30
-28
-25
Minimum
Threshold
4.50
4.25
3.00
2.85
2.55
Maximum
Threshold
4.75
4.50
3.15
3.00
2.70
SDA
XDEC
WP*
CONTR
OL
LOGIC
DATA IN STORAGE
HIGHVOLTAGE/
TIMING CONTR
OL
RESET Controller
MR
Precision
Vcc Monitor
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
RESET*
* CAT1025 Only
RESET
PIN CONFIGURATION
DIP Package (L)
SOIC Package (W)
TSSOP Package (Y)
MSOP Package (Z)
¯¯¯
MR
¯¯¯¯¯¯
RESET
NC
V
SS
¯¯¯
MR
¯¯¯¯¯¯
RESET
RESET
V
SS
1
2
3
4
CAT1024
8
7
6
5
V
CC
NC
SCL
SDA
(Bottom View)
TDFN Package: 3 mm x 3 mm
0.8mm maximum height - (ZD4)
V
CC
8
NC 7
CAT1024
SCL 6
SDA 5
V
CC
8
WDI 7
CAT1025
SCL 6
SDA 5
1
¯¯¯
MR
¯¯¯¯¯¯
2
RESET
3 NC
4 V
SS
1
¯¯¯
MR
¯¯¯¯¯¯
2
RESET
3 RESET
4 V
SS
1
2
3
4
CAT1025
8
7
6
5
V
CC
WP
SCL
SDA
Doc. No. MD-3008 Rev. R
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1024, CAT1025
PIN DESCRIPTION
¯¯¯¯¯¯
RESET/RESET:
RESET OUTPUTs
(RESET CAT1025 Only)
¯¯¯¯¯¯
These are open drain pins and RESET can be used
as a manual reset trigger input. By forcing a reset
condition on the pin the device will initiate and
maintain a reset condition. The RESET pin must be
connected through a pull-down resistor, and the
¯¯¯¯¯¯
RESET pin must be connected through a pull-up
resistor.
SDA:
SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
SCL:
SERIAL CLOCK
Serial clock input.
¯¯¯:
MANUAL RESET INPUT
MR
Manual Reset input is a debounced input that can be
connected to an external source for Manual Reset.
Pulling the MR input low will generate a Reset
condition. Reset outputs are active while ¯¯¯ input is
MR
low and for the reset timeout period after ¯¯¯ returns
MR
to high. The input has an internal pull up resistor.
WP (CAT1025 Only):
WRITE PROTECT INPUT
When WP input is tied to V
SS
or left unconnected write
operations to the entire array are allowed. When tied
to V
CC
, the entire array is protected. This input has an
internal pull down resistor.
PIN FUNCTION
Pin
Name
NC
¯¯¯¯¯¯
RESET
V
SS
SDA
SCL
RESET
V
CC
WP
¯¯¯
MR
Function
No Connect
Active Low Reset Input/Output
Ground
Serial Data/Address
Clock Input
Active High Reset Output
(CAT1025 only)
Power Supply
Write Protect (CAT1025 only)
Manual Reset Input
OPERATING TEMPERATURE RANGE
Industrial
Extended
-40ºC to 85ºC
-40ºC to 125ºC
CAT10XX FAMILY OVERVIEW
Device
CAT1021
CAT1022
CAT1023
CAT1024
CAT1025
CAT1026
CAT1027
WDI
Manual
Reset
Input Pin
Watchdog
Watchdog
Monitor
Pin
SDA
SDA
WDI
Write
Protection
Pin
Independent
Auxiliary
Voltage Sense
RESET:
Active High
and LOW
EEPROM
2k
2k
2k
2k
2k
2k
2k
For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-3008 Rev. R
CAT1024, CAT1025
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground
(2)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 s)
Output Short Circuit Current
(3)
Ratings
–55 to +125
–65 to +150
–2.0 to V
CC
+ 2.0
–2.0 to 7.0
1.0
300
100
Units
ºC
ºC
V
V
W
ºC
mA
D.C. OPERATING CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
SB
V
IL(4)
V
IH(4)
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Power Supply Current (Write)
Power Supply Current (Read)
Standby Current
Input Low Voltage
Input High Voltage
Output Low Voltage
¯¯¯¯¯¯
(SDA, RESET)
Output High Voltage
(RESET)
I
OL
= 3 mA
V
CC
= 2.7 V
I
OH
= -0.4 mA
V
CC
= 2.7V
CAT102x-45
(V
CC
= 5.0 V)
CAT102x-42
(V
CC
= 5.0 V)
V
TH
Reset Threshold
CAT102x-30
(V
CC
= 3.3 V)
CAT102x-28
(V
CC
= 3.3 V)
CAT102x-25
(V
CC
= 3.0 V)
V
RVALID
V
RT
(5)
Test Conditions
V
IN
= GND to V
CC
V
IN
= GND to V
CC
f
SCL
= 400 kHz
V
CC
= 5.5 V
f
SCL
= 400 kHz
V
CC
= 5.5 V
Vcc = 5.5 V,
V
IN
= GND or V
CC
Min
-2
-10
Typ
Max
10
10
3
1
40
Units
µA
µA
mA
mA
µA
V
V
V
V
-0.5
0.7 x Vcc
0.3 x V
CC
V
CC
+ 0.5
0.4
V
CC
- 0.75
4.50
4.25
3.00
2.85
2.55
1.00
15
4.75
4.50
3.15
3.00
2.70
V
Reset Output Valid V
CC
Voltage
Reset Threshold Hysteresis
V
mV
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) V
IL
min and V
IH
max are reference values only and are not tested.
(5) This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Doc. No. MD-3008 Rev. R
4
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT1024, CAT1025
CAPACITANCE
T
A
= 25ºC, f = 1.0 MHz, V
CC
= 5 V
Symbol
C
OUT (1)
C
IN(1)
Test
Output Capacitance
Input Capacitance
Test Conditions
V
OUT
= 0 V
V
IN
= 0 V
Max
8
6
Units
pF
pF
AC CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle
(2)
Symbol
f
SCL
t
SP
t
LOW
t
HIGH
t
R(1)
t
F
(1)
Parameter
Clock Frequency
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
Min
Max
400
100
Units
kHz
ns
µs
µs
1.3
0.6
300
300
0.6
0.6
0
100
0.6
900
50
1.3
5
ns
ns
µs
µs
ns
ns
µs
ns
ns
µs
ms
t
HD; STA
t
SU; STA
t
HD; DAT
t
SU; DAT
t
SU; STO
t
AA
t
DH
t
BUF
(1)
t
WC(3)
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-3008 Rev. R
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