Features 8-bit
Microcontroller
High Performance, Low Power AVR 8-Bit Microcontroller with 4/8/16/32K
Advanced RISC Architecture Bytes In-System
Programmable
131 Powerful Instructions Most Single Clock Cycle Execution Flash
32 x 8 General Purpose Working Registers
Fully Static Operation ATmega48A
Up to 20 MIPS Throughput at 20 MHz ATmega48PA
On-chip 2-cycle Multiplier ATmega88A
High Endurance Non-volatile Memory Segments ATmega88PA
4/8/16/32K Bytes of In-System Self-Programmable Flash program memory ATmega168A
256/512/512/1K Bytes EEPROM ATmega168PA
512/1K/1K/2K Bytes Internal SRAM ATmega328
Write/Erase Cycles: 10,000 Flash/100,000 EEPROM ATmega328P
Data retention: 20 years at 85C/100 years at 25C(1)
Optional Boot Code Section with Independent Lock Bits Summary
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Programming Lock for Software Security
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
Real Time Counter with Separate Oscillator
Six PWM Channels
8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement
6-channel 10-bit ADC in PDIP Package
Temperature Measurement
Programmable Serial USART
Master/Slave SPI Serial Interface
Byte-oriented 2-wire Serial Interface (Philips I2C compatible)
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Interrupt and Wake-up on Pin Change
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
I/O and Packages
23 Programmable I/O Lines
28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
Operating Voltage:
1.8 - 5.5V
Temperature Range:
-40C to 85C
Speed Grade:
0 - 4 MHz@1.8 - 5.5V, 0 - 10 MHz@2.7 - 5.5.V, 0 - 20 MHz @ 4.5 - 5.5V
Power Consumption at 1 MHz, 1.8V, 25C
Active Mode: 0.2 mA
Power-down Mode: 0.1 A
Power-save Mode: 0.75 A (Including 32 kHz RTC)
Rev. 8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
1. Pin Configurations
Figure 1-1. Pinout ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
TQFP Top View PDIP
32 PD2 (INT0/PCINT18) (PCINT14/RESET) PC6 1 28 PC5 (ADC5/SCL/PCINT13)
31 PD1 (TXD/PCINT17) (PCINT16/RXD) PD0 2 27 PC4 (ADC4/SDA/PCINT12)
30 PD0 (RXD/PCINT16) (PCINT17/TXD) PD1 3 26 PC3 (ADC3/PCINT11)
29 PC6 (RESET/PCINT14) (PCINT18/INT0) PD2 4 25 PC2 (ADC2/PCINT10)
28 PC5 (ADC5/SCL/PCINT13) 24 PC1 (ADC1/PCINT9)
27 PC4 (ADC4/SDA/PCINT12) (PCINT19/OC2B/INT1) PD3 5 23 PC0 (ADC0/PCINT8)
26 PC3 (ADC3/PCINT11) (PCINT20/XCK/T0) PD4 6 22 GND
25 PC2 (ADC2/PCINT10) VCC 7 21 AREF
GND 8 20 AVCC
(PCINT19/OC2B/INT1) PD3 1 24 PC1 (ADC1/PCINT9) 19 PB5 (SCK/PCINT5)
(PCINT20/XCK/T0) PD4 2 23 PC0 (ADC0/PCINT8) (PCINT6/XTAL1/TOSC1) PB6 9 18 PB4 (MISO/PCINT4)
GND 3 22 ADC7 (PCINT7/XTAL2/TOSC2) PB7 10 17 PB3 (MOSI/OC2A/PCINT3)
VCC 4 21 GND 16 PB2 (SS/OC1B/PCINT2)
GND 5 20 AREF (PCINT21/OC0B/T1) PD5 11 15 PB1 (OC1A/PCINT1)
VCC 6 19 ADC6 (PCINT22/OC0A/AIN0) PD6 12
18 AVCC
(PCINT6/XTAL1/TOSC1) PB6 7 17 PB5 (SCK/PCINT5) (PCINT23/AIN1) PD7 13
(PCINT7/XTAL2/TOSC2) PB7 8 (PCINT0/CLKO/ICP1) PB0 14
(PCINT21/OC0B/T1) PD5 9
(PCINT22/OC0A/AIN0) PD6 10
(PCINT23/AIN1) PD7 11
(PCINT0/CLKO/ICP1) PB0 12
(PCINT1/OC1A) PB1 13
(PCINT2/SS/OC1B) PB2 14
(PCINT3/OC2A/MOSI) PB3 15
(PCINT4/MISO) PB4 16
28 MLF Top View 32 MLF Top View
28 PD2 (INT0/PCINT18) 32 PD2 (INT0/PCINT18)
27 PD1 (TXD/PCINT17) 31 PD1 (TXD/PCINT17)
26 PD0 (RXD/PCINT16) 30 PD0 (RXD/PCINT16)
25 PC6 (RESET/PCINT14) 29 PC6 (RESET/PCINT14)
24 PC5 (ADC5/SCL/PCINT13) 28 PC5 (ADC5/SCL/PCINT13)
23 PC4 (ADC4/SDA/PCINT12) 27 PC4 (ADC4/SDA/PCINT12)
22 PC3 (ADC3/PCINT11) 26 PC3 (ADC3/PCINT11)
25 PC2 (ADC2/PCINT10)
(PCINT19/OC2B/INT1) PD3 1 21 PC2 (ADC2/PCINT10) (PCINT19/OC2B/INT1) PD3 1 24 PC1 (ADC1/PCINT9)
(PCINT20/XCK/T0) PD4 2 20 PC1 (ADC1/PCINT9) (PCINT20/XCK/T0) PD4 2 23 PC0 (ADC0/PCINT8)
VCC 3 19 PC0 (ADC0/PCINT8) GND 3 22 ADC7
GND 4 18 GND VCC 4 21 GND
17 AREF GND 5 20 AREF
(PCINT6/XTAL1/TOSC1) PB6 5 16 AVCC VCC 6 19 ADC6
(PCINT7/XTAL2/TOSC2) PB7 6 15 PB5 (SCK/PCINT5) 18 AVCC
(PCINT6/XTAL1/TOSC1) PB6 7 17 PB5 (SCK/PCINT5)
(PCINT21/OC0B/T1) PD5 7 (PCINT22/OC0A/AIN0) PD6 8 (PCINT7/XTAL2/TOSC2) PB7 8
(PCINT23/AIN1) PD7 9
NOTE: Bottom pad should be soldered to ground. (PCINT21/OC0B/T1) PD5 9
(PCINT0/CLKO/ICP1) PB0 10 (PCINT22/OC0A/AIN0) PD6 10
(PCINT1/OC1A) PB1 11 NOTE: Bottom pad should be soldered to ground.
(PCINT23/AIN1) PD7 11
(PCINT2/SS/OC1B) PB2 12 (PCINT0/CLKO/ICP1) PB0 12
(PCINT3/OC2A/MOSI) PB3 13
(PCINT1/OC1A) PB1 13
(PCINT4/MISO) PB4 14 (PCINT2/SS/OC1B) PB2 14
(PCINT3/OC2A/MOSI) PB3 15
(PCINT4/MISO) PB4 16
2
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
1.1 Pin Descriptions
1.1.1 VCC
Digital supply voltage.
1.1.2 GND
Ground.
1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil-
lator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting
Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7...6 is used as
TOSC2...1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in and "System Clock and Clock Options"
on page 26.
1.1.4 Port C (PC5:0)
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PC5...0 output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
1.1.5 PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-
acteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 28-12 on page 323. Shorter pulses are not guaran-
teed to generate a Reset.
The various special features of Port C are elaborated in "Alternate Functions of Port C" on page
86.
1.1.6 Port D (PD7:0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
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8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
The various special features of Port D are elaborated in "Alternate Functions of Port D" on page
89.
1.1.7 AVCC AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally
AREF connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
1.1.8 through a low-pass filter. Note that PC6...4 use digital supply voltage, VCC.
1.1.9
AREF is the analog reference pin for the A/D Converter.
ADC7:6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter.
These pins are powered from the analog supply and serve as 10-bit ADC channels.
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8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
2. Overview
The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P is a low-power CMOS 8-bit microcon-
troller based on the AVR enhanced RISC architecture. By executing powerful instructions in a
single clock cycle, the ATmega48A/48PA/88A/88PA/168A/168PA/328/328P achieves through-
puts approaching 1 MIPS per MHz allowing the system designer to optimize power consumption
versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
GND
VCC
Watchdog Power debugWIRE
Timer Supervision
POR / BOD & PROGRAM
Watchdog LOGIC
Oscillator RESET
SRAM
Oscillator Flash
Circuits /
CPU
Clock
Generation
EEPROM
AVCC
AREF
GND
8bit T/C 0 16bit T/C 1 2
8bit T/C 2
Analog A/D Conv.
Comp.
DATABUS Internal 6
Bandgap
USART 0 SPI TWI
PORT D (8) PORT B (8) PORT C (7)
RESET
XTAL[1..2]
PD[0..7] PB[0..7] PC[0..6] ADC[6..7]
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
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8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P provides the following features:
4K/8K bytes of In-System Programmable Flash with Read-While-Write capabilities,
256/512/512/1K bytes EEPROM, 512/1K/1K/2K bytes SRAM, 23 general purpose I/O lines, 32
general purpose working registers, three flexible Timer/Counters with compare modes, internal
and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface,
an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a pro-
grammable Watchdog Timer with internal Oscillator, and five software selectable power saving
modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire
Serial Interface, SPI port, and interrupt system to continue functioning. The Power-down mode
saves the register contents but freezes the Oscillator, disabling all other chip functions until the
next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run,
allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC
Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC,
to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up com-
bined with low power consumption.
The device is manufactured using Atmel's high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-
gram running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega48A/48PA/88A/88PA/168A/168PA/328/328P is a powerful
microcontroller that provides a highly flexible and cost effective solution to many embedded con-
trol applications.
The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P AVR is supported with a full suite of
program and system development tools including: C Compilers, Macro Assemblers, Program
Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
2.2 Comparison Between Processors
The ATmega48A/48PA/88A/88PA/168A/168PA/328/328P differ only in memory sizes, boot
loader support, and interrupt vector sizes. Table 2-1 summarizes the different memory and inter-
rupt vector sizes for the devices.
Table 2-1. Memory Size Summary
Device Flash EEPROM RAM Interrupt Vector Size
512 Bytes 1 instruction word/vector
ATmega48A 4K Bytes 256 Bytes 512 Bytes 1 instruction word/vector
1K Bytes 1 instruction word/vector
ATmega48PA 4K Bytes 256 Bytes 1K Bytes 1 instruction word/vector
1K Bytes 2 instruction words/vector
ATmega88A 8K Bytes 512 Bytes
ATmega88PA 8K Bytes 512 Bytes
ATmega168A 16K Bytes 512 Bytes
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8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
Table 2-1. Memory Size Summary
Device Flash EEPROM RAM Interrupt Vector Size
1K Bytes 2 instruction words/vector
ATmega168PA 16K Bytes 512 Bytes 2K Bytes 2 instruction words/vector
2K Bytes 2 instruction words/vector
ATmega328 32K Bytes 1K Bytes
ATmega328P 32K Bytes 1K Bytes
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P support a real Read-While-Write Self-Pro-
gramming mechanism. There is a separate Boot Loader Section, and the SPM instruction can
only execute from there. In ATmega 48A/48PA there is no Read-While-Write support and no
separate Boot Loader Section. The SPM instruction can execute from the entire Flash.
3. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
Note: 1.
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8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
4. Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xFF) Reserved 196
(0xFE) Reserved 200
(0xFD) Reserved 200
(0xFC) Reserved 198/213
(0xFB) Reserved
(0xFA) Reserved 8
(0xF9) Reserved
(0xF8) Reserved
(0xF7) Reserved
(0xF6) Reserved
(0xF5) Reserved
(0xF4) Reserved
(0xF3) Reserved
(0xF2) Reserved
(0xF1) Reserved
(0xF0) Reserved
(0xEF) Reserved
(0xEE) Reserved
(0xED) Reserved
(0xEC) Reserved
(0xEB) Reserved
(0xEA) Reserved
(0xE9) Reserved
(0xE8) Reserved
(0xE7) Reserved
(0xE6) Reserved
(0xE5) Reserved
(0xE4) Reserved
(0xE3) Reserved
(0xE2) Reserved
(0xE1) Reserved
(0xE0) Reserved
(0xDF) Reserved
(0xDE) Reserved
(0xDD) Reserved
(0xDC) Reserved
(0xDB) Reserved
(0xDA) Reserved
(0xD9) Reserved
(0xD8) Reserved
(0xD7) Reserved
(0xD6) Reserved
(0xD5) Reserved
(0xD4) Reserved
(0xD3) Reserved
(0xD2) Reserved
(0xD1) Reserved
(0xD0) Reserved
(0xCF) Reserved
(0xCE) Reserved
(0xCD) Reserved
(0xCC) Reserved
(0xCB) Reserved
(0xCA) Reserved
(0xC9) Reserved
(0xC8) Reserved
(0xC7) Reserved
(0xC6)
(0xC5) UDR0
(0xC4) UBRR0H UMSEL01 UMSEL00 UPM01 UCPOL0
(0xC3) UBRR0L
(0xC2) Reserved
UCSR0C
USART I/O Data Register
USART Baud Rate Register High
USART Baud Rate Register Low
UPM00 USBS0 UCSZ01 /UDORD0 UCSZ00 / UCPHA0
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 197
(0xC0) UCSR0A RXC0 TXC0 U2X0 MPCM0 196
(0xBF) Reserved UDRE0 FE0 DOR0 UPE0 245
(0xBE) Reserved 242
(0xBD) TWAMR 244
(0xBC) TWAM6 TWAM5 TWAM0 245
(0xBB) TWCR TWINT TWEA TWIE 244
(0xBA) TWDR 242
(0xB9) TWAR TWA6 TWA5 TWAM4 TWAM3 TWAM2 TWAM1 TWA0 TWGCE 165
(0xB8) TWSR TWS7 TWS6 TWPS1 TWPS0 163
(0xB7) TWBR TWSTA TWSTO TWWC TWEN 163
(0xB6) Reserved EXCLK 163
(0xB5) ASSR 2-wire Serial Interface Data Register TCR2AUB TCR2BUB 162
(0xB4) Reserved 159
(0xB3) OCR2B FOC2B TWA4 TWA3 TWA2 TWA1
(0xB2) OCR2A FOC2A COM2A0 139
(0xB1) TCNT2 COM2A1 TWS5 TWS4 TWS3 CS21 CS20 139
(0xB0) TCCR2B WGM21 WGM20 139
(0xAF) TCCR2A 2-wire Serial Interface Bit Rate Register 139
(0xAE) Reserved 139
(0xAD) Reserved 139
(0xAC) Reserved 139
(0xAB) Reserved AS2 TCN2UB OCR2AUB OCR2BUB 139
(0xAA) Reserved 138
(0xA9) Reserved 137
(0xA8) Reserved 135
(0xA7) Reserved Timer/Counter2 Output Compare Register B
(0xA6) Reserved 9
(0xA5) Reserved Timer/Counter2 Output Compare Register A
(0xA4) Reserved
(0xA3) Reserved Timer/Counter2 (8-bit)
(0xA2) Reserved
(0xA1) Reserved WGM22 CS22
(0xA0) Reserved
(0x9F) Reserved COM2B1 COM2B0
(0x9E) Reserved
(0x9D) Reserved
(0x9C) Reserved
(0x9B) Reserved
(0x9A) Reserved
(0x99) Reserved
(0x98) Reserved
(0x97) Reserved
(0x96) Reserved
(0x95) Reserved
(0x94) Reserved
(0x93) Reserved
(0x92) Reserved
(0x91) Reserved
(0x90) Reserved
(0x8F) Reserved
(0x8E) Reserved
(0x8D) Reserved
(0x8C) Reserved
(0x8B) Reserved
(0x8A) OCR1BH FOC1B
(0x89) OCR1BL FOC1A ICES1
(0x88) OCR1AH ICNC1 COM1A0
(0x87) OCR1AL COM1A1 CS11 CS10
(0x86) ICR1H WGM11 WGM10
(0x85) ICR1L
(0x84) TCNT1H
(0x83) TCNT1L
(0x82) Reserved
(0x81) TCCR1C
(0x80) TCCR1B
TCCR1A
Timer/Counter1 - Output Compare Register B High Byte
Timer/Counter1 - Output Compare Register B Low Byte
Timer/Counter1 - Output Compare Register A High Byte
Timer/Counter1 - Output Compare Register A Low Byte
Timer/Counter1 - Input Capture Register High Byte
Timer/Counter1 - Input Capture Register Low Byte
Timer/Counter1 - Counter Register High Byte
Timer/Counter1 - Counter Register Low Byte
WGM13 WGM12 CS12
COM1B1 COM1B0
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0x7F) DIDR1 AIN1D AIN0D 250
(0x7E) DIDR0 ADC1D ADC0D 267
(0x7D) Reserved ADC5D ADC4D ADC3D ADC2D 263
(0x7C) ADMUX REFS1 REFS0 266
(0x7B) ADCSRB ACME MUX1 MUX0 264
(0x7A) ADCSRA ADEN ADSC ADTS1 ADTS0 266
(0x79) ADCH ADLAR MUX3 MUX2 ADPS1 ADPS0 266
(0x78) ADCL
(0x77) Reserved ADTS2 164
(0x76) Reserved 140
(0x75) Reserved ADATE ADIF ADIE ADPS2 112
(0x74) Reserved 75
(0x73) Reserved ADC Data Register High byte 75
(0x72) Reserved 75
(0x71) Reserved ADC Data Register Low byte 72
(0x70) TIMSK2
(0x6F) TIMSK1 37
(0x6E) TIMSK0 PCINT23 PCINT22 42
(0x6D) PCMSK2 PCINT14
(0x6C) PCMSK1 PCINT7 PCINT6 37
(0x6B) PCMSK0 55
(0x6A) Reserved 9
(0x69) EICRA 12
(0x68) PCICR OCIE2A TOIE2 12
(0x67) Reserved OCIE1A TOIE1
(0x66) OSCCAL OCIE0A TOIE0 294
(0x65) Reserved PRTWI PRTIM2 PCINT17 PCINT16 45/69/93
(0x64) PRR PCINT9 PCINT8
(0x63) Reserved PCINT1 PCINT0 55
(0x62) Reserved 40
(0x61) CLKPR CLKPCE OCIE2B ISC01 ISC00
(0x60) WDTCSR WDIF WDIE PCIE1 PCIE0 248
0x3F (0x5F) SREG I T ICIE1 OCIE1B 176
0x3E (0x5E) SPH 175
0x3D (0x5D) SP7 SP6 OCIE0B 174
0x3C (0x5C) SPL 25
0x3B (0x5B) Reserved PCINT21 PCINT20 PCINT19 PCINT18 25
0x3A (0x5A) Reserved
0x39 (0x59) Reserved PCINT13 PCINT12 PCINT11 PCINT10 144/166
0x38 (0x58) Reserved 21
0x37 (0x57) Reserved SPMIE (RWWSB)5. PCINT5 PCINT4 PCINT3 PCINT2 21
0x36 (0x56) SPMCSR 21
0x35 (0x55) Reserved BODS(6) 21
0x34 (0x54) MCUCR 25
0x33 (0x53) MCUSR ISC11 ISC10
0x32 (0x52)
0x31 (0x51) SMCR PCIE2
0x30 (0x50) Reserved ACD ACBG
0x2F (0x4F) Reserved
0x2E (0x4E)
0x2D (0x4D) ACSR SPIF WCOL Oscillator Calibration Register
0x2C (0x4C) Reserved SPIE SPE
0x2B (0x4B)
0x2A (0x4A) SPDR PRUSART0 PRADC
0x29 (0x49) SPSR PRTIM0 PRTIM1 PRSPI
0x28 (0x48) SPCR FOC0A FOC0B
0x27 (0x47) GPIOR2 COM0A1 COM0A0
0x26 (0x46) GPIOR1 CLKPS1 CLKPS0
0x25 (0x45) Reserved TSM WDP1 WDP0
0x24 (0x44) OCR0B Z C
0x23 (0x43) OCR0A CLKPS3 CLKPS2 SP9 SP8
0x22 (0x42) TCNT0 SP1 SP0
0x21 (0x41) TCCR0B WDP3 WDCE WDE WDP2
0x20 (0x40) TCCR0A
0x1F (0x3F) GTCCR H S V N
0x1E (0x3E) EEARH
EEARL (SP10) 5.
EEDR PGERS SELFPRGEN
EECR SP5 SP4 SP3 SP2
GPIOR0 IVSEL IVCE
EXTRF PORF
SM0 SE
ACIS1 ACIS0
(RWWSRE)5. BLBSET PGWRT
BODSE(6) PUD
WDRF BORF
SM2 SM1
ACO ACI ACIE ACIC
SPI Data Register
SPI2X
SPR1 SPR0
DORD MSTR CPOL CPHA
General Purpose I/O Register 2
General Purpose I/O Register 1
Timer/Counter0 Output Compare Register B
Timer/Counter0 Output Compare Register A
Timer/Counter0 (8-bit)
WGM02 CS02 CS01 CS00
WGM01 WGM00
COM0B1 COM0B0 PSRASY PSRSYNC
(EEPROM Address Register High Byte) 5.
EEPROM Address Register Low Byte
EEPROM Data Register
EEPM1 EEPM0 EERIE EEMPE EEPE EERE
General Purpose I/O Register 0
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8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x1D (0x3D) EIMSK INT1 INT0 73
0x1C (0x3C) EIFR INTF1 INTF0 73
0x1B (0x3B) PCIFR PCIF2 PCIF1 PCIF0
0x1A (0x3A) Reserved
0x19 (0x39) Reserved
0x18 (0x38) Reserved
0x17 (0x37) TIFR2 OCF2B OCF2A TOV2 164
0x16 (0x36) TIFR1 ICF1 OCF1B OCF1A TOV1 140
0x15 (0x35) TIFR0 OCF0B OCF0A TOV0
0x14 (0x34) Reserved
0x13 (0x33) Reserved
0x12 (0x32) Reserved
0x11 (0x31) Reserved
0x10 (0x30) Reserved
0x0F (0x2F) Reserved
0x0E (0x2E) Reserved
0x0D (0x2D) Reserved
0x0C (0x2C) Reserved
0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 94
0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 94
0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 94
0x08 (0x28) PORTC PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 93
0x07 (0x27) DDRC DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 93
0x06 (0x26) PINC PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 93
0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 93
0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 93
0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 93
0x02 (0x22) Reserved
0x01 (0x21) Reserved
0x0 (0x20) Reserved
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P is a complex microcontroller with more peripheral units than can be
supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60
- 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
5. Only valid for ATmega88A/88PA/168A/168PA/328/328P.
6. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA/328P
11
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
5. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS Rd Rd + Rr Z,C,N,V,H 1
Rd Rd + Rr + C Z,C,N,V,H 1
ADD Rd, Rr Add two Registers Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2
Rd Rd - Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd Rd - K Z,C,N,V,H 1
Rd Rd - Rr - C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rd Rd - K - C Z,C,N,V,H 1
Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd Rd Rr Z,N,V 1
Rd Rd K Z,N,V 1
SUBI Rd, K Subtract Constant from Register Rd Rd v Rr Z,N,V 1
Rd Rd v K Z,N,V 1
SBC Rd, Rr Subtract with Carry two Registers Rd Rd Rr Z,N,V 1
Rd 0xFF - Rd Z,C,N,V 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd 0x00 - Rd Z,C,N,V,H 1
Rd Rd v K Z,N,V 1
SBIW Rdl,K Subtract Immediate from Word Rd Rd (0xFF - K) Z,N,V 1
Rd Rd + 1 Z,N,V 1
AND Rd, Rr Logical AND Registers Rd Rd - 1 Z,N,V 1
Rd Rd Rd Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd Rd Rd Z,N,V 1
Rd 0xFF None 1
OR Rd, Rr Logical OR Registers R1:R0 Rd x Rr Z,C 2
R1:R0 Rd x Rr Z,C 2
ORI Rd, K Logical OR Register and Constant R1:R0 Rd x Rr Z,C 2
R1:R0 (Rd x Rr) << 1 Z,C 2
EOR Rd, Rr Exclusive OR Registers R1:R0 (Rd x Rr) << 1 Z,C 2
R1:R0 (Rd x Rr) << 1 Z,C 2
COM Rd One's Complement
PC PC + k + 1 None 2
NEG Rd Two's Complement PC Z None 2
PC k None 3
SBR Rd,K Set Bit(s) in Register PC PC + k + 1 None 3
PC Z None 3
CBR Rd,K Clear Bit(s) in Register PC k None 4
PC STACK None 4
INC Rd Increment PC STACK I 4
if (Rd = Rr) PC PC + 2 or 3 None 1/2/3
DEC Rd Decrement Rd - Rr Z, N,V,C,H 1
Rd - Rr - C Z, N,V,C,H 1
TST Rd Test for Zero or Minus Rd - K Z, N,V,C,H 1
if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3
CLR Rd Clear Register if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3
if (P(b)=0) PC PC + 2 or 3 None 1/2/3
SER Rd Set Register if (P(b)=1) PC PC + 2 or 3 None 1/2/3
if (SREG(s) = 1) then PCPC+k + 1 None 1/2
MUL Rd, Rr Multiply Unsigned if (SREG(s) = 0) then PCPC+k + 1 None 1/2
if (Z = 1) then PC PC + k + 1 None 1/2
MULS Rd, Rr Multiply Signed if (Z = 0) then PC PC + k + 1 None 1/2
if (C = 1) then PC PC + k + 1 None 1/2
MULSU Rd, Rr Multiply Signed with Unsigned if (C = 0) then PC PC + k + 1 None 1/2
if (C = 0) then PC PC + k + 1 None 1/2
FMUL Rd, Rr Fractional Multiply Unsigned if (C = 1) then PC PC + k + 1 None 1/2
if (N = 1) then PC PC + k + 1 None 1/2
FMULS Rd, Rr Fractional Multiply Signed if (N = 0) then PC PC + k + 1 None 1/2
if (N V= 0) then PC PC + k + 1 None 1/2
FMULSU Rd, Rr Fractional Multiply Signed with Unsigned if (N V= 1) then PC PC + k + 1 None 1/2
if (H = 1) then PC PC + k + 1 None 1/2
BRANCH INSTRUCTIONS if (H = 0) then PC PC + k + 1 None 1/2
if (T = 1) then PC PC + k + 1 None 1/2
RJMP k Relative Jump if (T = 0) then PC PC + k + 1 None 1/2
if (V = 1) then PC PC + k + 1 None 1/2
IJMP Indirect Jump to (Z) if (V = 0) then PC PC + k + 1 None 1/2
Direct Jump
JMP(1) k
RCALL k Relative Subroutine Call
ICALL Indirect Call to (Z)
Direct Subroutine Call
CALL(1) k
RET Subroutine Return
RETI Interrupt Return
CPSE Rd,Rr Compare, Skip if Equal
CP Rd,Rr Compare
CPC Rd,Rr Compare with Carry
CPI Rd,K Compare Register with Immediate
SBRC Rr, b Skip if Bit in Register Cleared
SBRS Rr, b Skip if Bit in Register is Set
SBIC P, b Skip if Bit in I/O Register Cleared
SBIS P, b Skip if Bit in I/O Register is Set
BRBS s, k Branch if Status Flag Set
BRBC s, k Branch if Status Flag Cleared
BREQ k Branch if Equal
BRNE k Branch if Not Equal
BRCS k Branch if Carry Set
BRCC k Branch if Carry Cleared
BRSH k Branch if Same or Higher
BRLO k Branch if Lower
BRMI k Branch if Minus
BRPL k Branch if Plus
BRGE k Branch if Greater or Equal, Signed
BRLT k Branch if Less Than Zero, Signed
BRHS k Branch if Half Carry Flag Set
BRHC k Branch if Half Carry Flag Cleared
BRTS k Branch if T Flag Set
BRTC k Branch if T Flag Cleared
BRVS k Branch if Overflow Flag is Set
BRVC k Branch if Overflow Flag is Cleared
12
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
Mnemonics Operands Description Operation Flags #Clocks
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2
Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2
BRID k
Set Bit in I/O Register I/O(P,b) 1 None 2
BIT AND BIT-TEST INSTRUCTIONS Clear Bit in I/O Register I/O(P,b) 0 None 2
Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1
SBI P,b Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1
Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1
CBI P,b Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1
Arithmetic Shift Right Rd(n) Rd(n+1), n=0...6 Z,C,N,V 1
LSL Rd Swap Nibbles Rd(3...0)Rd(7...4),Rd(7...4)Rd(3...0) None 1
Flag Set SREG(s) 1 SREG(s) 1
LSR Rd Flag Clear SREG(s) 0 SREG(s) 1
Bit Store from Register to T T Rr(b) T 1
ROL Rd Bit load from T to Register Rd(b) T None 1
Set Carry C1 C 1
ROR Rd Clear Carry C0 C 1
Set Negative Flag N1 N 1
ASR Rd Clear Negative Flag N0 N 1
Set Zero Flag Z1 Z 1
SWAP Rd Clear Zero Flag Z0 Z 1
Global Interrupt Enable I1 I 1
BSET s Global Interrupt Disable I0 I 1
Set Signed Test Flag S1 S 1
BCLR s Clear Signed Test Flag S0 S 1
Set Twos Complement Overflow. V1 V 1
BST Rr, b Clear Twos Complement Overflow V0 V 1
Set T in SREG T1 T 1
BLD Rd, b Clear T in SREG T0 T 1
Set Half Carry Flag in SREG H1 H 1
SEC Clear Half Carry Flag in SREG H0 H 1
CLC Move Between Registers Rd Rr None 1
Copy Register Word Rd+1:Rd Rr+1:Rr None 1
SEN Load Immediate Rd K None 1
Load Indirect Rd (X) None 2
CLN Load Indirect and Post-Inc. Rd (X), X X + 1 None 2
Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2
SEZ Load Indirect Rd (Y) None 2
Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2
CLZ Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2
Load Indirect with Displacement Rd (Y + q) None 2
SEI Load Indirect Rd (Z) None 2
Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2
CLI Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2
Load Indirect with Displacement Rd (Z + q) None 2
SES Load Direct from SRAM Rd (k) None 2
Store Indirect (X) Rr None 2
CLS Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2
Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2
SEV Store Indirect (Y) Rr None 2
Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2
CLV Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2
Store Indirect with Displacement (Y + q) Rr None 2
SET Store Indirect (Z) Rr None 2
Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2
CLT Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2
Store Indirect with Displacement (Z + q) Rr None 2
SEH Store Direct to SRAM (k) Rr None 2
Load Program Memory R0 (Z) None 3
CLH Load Program Memory Rd (Z) None 3
Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3
DATA TRANSFER INSTRUCTIONS Store Program Memory (Z) R1:R0 None -
In Port Rd P None 1
MOV Rd, Rr Out Port P Rr None 1
Push Register on Stack STACK Rr None 2
MOVW Rd, Rr
LDI Rd, K
LD Rd, X
LD Rd, X+
LD Rd, - X
LD Rd, Y
LD Rd, Y+
LD Rd, - Y
LDD Rd,Y+q
LD Rd, Z
LD Rd, Z+
LD Rd, -Z
LDD Rd, Z+q
LDS Rd, k
ST X, Rr
ST X+, Rr
ST - X, Rr
ST Y, Rr
ST Y+, Rr
ST - Y, Rr
STD Y+q,Rr
ST Z, Rr
ST Z+, Rr
ST -Z, Rr
STD Z+q,Rr
STS k, Rr
LPM
LPM Rd, Z
LPM Rd, Z+
SPM
IN Rd, P
OUT P, Rr
PUSH Rr
13
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
Mnemonics Operands Description Operation Flags #Clocks
POP Rd Pop Register from Stack Rd STACK None 2
MCU CONTROL INSTRUCTIONS No Operation (see specific descr. for Sleep function) None 1
Sleep (see specific descr. for WDR/timer) None 1
NOP Watchdog Reset For On-chip Debug Only None 1
Break None N/A
SLEEP
WDR
BREAK
Note: 1. These instructions are only available in ATmega168PA and ATmega328P.
14
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
6. Ordering Information
6.1 ATmega48A
Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range
20(3) 1.8 - 5.5
ATmega48A-AU 32A Industrial
ATmega48A-AUR(5) 32A (-40C to 85C)
ATmega48A-MMH(4) 28M1
ATmega48A-MMHR(4)(5) 28M1
ATmega48A-MU 32M1-A
ATmega48A-MUR(5) 32M1-A
ATmega48A-PU 28P3
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See "Speed Grades" on page 321.
4. NiPdAu Lead Finish.
5. Tape & Reel.
32A Package Type
28M1 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
32M1-A 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
15
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
6.2 ATmega48PA
Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range
20(3) 1.8 - 5.5
ATmega48PA-AU 32A Industrial
ATmega48PA-AUR(5) 32A (-40C to 85C)
ATmega48PA-MMH(4) 28M1
ATmega48PA-MMHR(4)(5) 28M1
ATmega48PA-MU 32M1-A
ATmega48PA-MUR(5) 32M1-A
ATmega48PA-PU 28P3
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See "Speed Grades" on page 321.
4. NiPdAu Lead Finish.
5. Tape & Reel.
32A Package Type
28M1 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
32M1-A 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
16
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
6.3 ATmega88A
Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range
20(3) 1.8 - 5.5
ATmega88A-AU 32A Industrial
ATmega88A-AUR(5) 32A (-40C to 85C)
ATmega88A-MMH(4) 28M1
ATmega88A-MMHR(4)(5) 28M1
ATmega88A-MU 32M1-A
ATmega88A-MUR(5) 32M1-A
ATmega88A-PU 28P3
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See "Speed Grades" on page 321.
4. NiPdAu Lead Finish.
5. Tape & Reel.
32A Package Type
28M1 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
32M1-A 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
17
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
6.4 ATmega88PA
Speed (MHz) Power Supply (V) Ordering Code(2) Package(1) Operational Range
20(3) 1.8 - 5.5
ATmega88PA-AU 32A Industrial
ATmega88PA-AUR(5) 32A (-40C to 85C)
ATmega88PA-MMH(4) 28M1
ATmega88PA-MMHR(4)(5) 28M1
ATmega88PA-MU 32M1-A
ATmega88PA-MUR(5) 32M1-A
ATmega88PA-PU 28P3
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See "Speed Grades" on page 321.
4. NiPdAu Lead Finish.
5. Tape & Reel.
32A Package Type
28M1 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
32M1-A 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
18
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
6.5 ATmega168A
Speed (MHz)(3) Power Supply (V) Ordering Code(2) Package(1) Operational Range
20 1.8 - 5.5
ATmega168A-AU 32A Industrial
ATmega168A-AUR(5) 32A (-40C to 85C)
ATmega168A-MMH(4) 28M1
ATmega168A-MMHR(4)(5) 28M1
ATmega168A-MU 32M1-A
ATmega168A-MUR(5) 32M1-A
ATmega168A-PU 28P3
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See "Speed Grades" on page 321
4. NiPdAu Lead Finish.
5. Tape & Reel.
32A Package Type
28M1 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
32M1-A 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
19
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
6.6 ATmega168PA
Speed (MHz)(3) Power Supply (V) Ordering Code(2) Package(1) Operational Range
20 1.8 - 5.5
ATmega168PA-AU 32A Industrial
ATmega168PA-AUR(5) 32A (-40C to 85C)
ATmega168PA-MMH(4) 28M1
ATmega168PA-MMHR(4)(5) 28M1
ATmega168PA-MU 32M1-A
ATmega168PA-MUR(5) 32M1-A
ATmega168PA-PU 28P3
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See "Speed Grades" on page 321.
4. NiPdAu Lead Finish.
5. Tape & Reel.
32A Package Type
28M1 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
32M1-A 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
6.7 ATmega328
Speed (MHz) Power Supply (V) Ordering Code(2) Package(1) Operational Range
20(3) 1.8 - 5.5
ATmega328-AU 32A Industrial
ATmega328-AUR(4) 32A (-40C to 85C)
ATmega328-MU 32M1-A
ATmega328-MUR(4) 32M1-A
ATmega328-PU 28P3
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See Figure 28-1 on page 321.
4. Tape & Reel
32A Package Type
28P3 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
32M1-A 28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
21
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
6.8 ATmega328P
Speed (MHz) Power Supply Ordering Code(2) Package(1) Operational Range
20(3) 1.8 - 5.5
ATmega328P-AU 32A Industrial
ATmega328P-AUR(4) 32A (-40C to 85C)
ATmega328P-MU 32M1-A
ATmega328P-MUR(4) 32M1-A
ATmega328P-PU 28P3
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also
Halide free and fully Green.
3. See Figure 28-1 on page 321.
4. Tape & Reel.
32A Package Type
28P3 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
32M1-A 28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
22
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
7. Packaging Information
7.1 32A
PIN 1 PIN 1 IDENTIFIER B
e E1 E
D1
D
C 0~7
A1 A2 A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1.20
A 0.15 Note 2
1.05 Note 2
A1 0.05 1.00 9.25
9.00 7.10
A2 0.95 7.00 9.25
9.00 7.10
D 8.75 7.00 0.45
0.20
D1 6.90 0.75
E 8.75
0.80 TYP
Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. E1 6.90
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
B 0.30
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch. C 0.09
3. Lead coplanarity is 0.10 mm maximum.
L 0.45
e
2325 Orchard Parkway TITLE 10/5/2001
R San Jose, CA 95131 DRAWING NO. REV.
32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 32A B
23
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
7.2 28M1
D
1 C
SIDE VIEW
2 Pin 1 ID
3
E
TOP VIEW A1
A
y
K D2
0.45 COMMON DIMENSIONS
(Unit of Measure = mm)
1
R 0.20 2 SYMBOL MIN NOM MAX NOTE
3 A
A1 0.80 0.90 1.00
E2 b
C 0.00 0.02 0.05
D
b D2 0.17 0.22 0.27
E
E2 0.20 REF
e
L 3.95 4.00 4.05
y
L K 2.35 2.40 2.45
3.95 4.00 4.05
e 2.35 2.40 2.45
BOTTOM VIEW
0.4 Ref 0.45
(4x)
0.35 0.40 0.45
0.00 0.08
Note: The terminal #1 ID is a Laser-marked Feature. 0.20
TITLE GPC 10/24/08
28M1, 28-pad, 4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm, ZBV DRAWING NO. REV.
2.4 x 2.4 mm Exposed Pad, Thermally Enhanced
Package Drawing Contact: Plastic Very Thin Quad Flat No Lead Package (VQFN) 28M1 B
packagedrawings@atmel.com
24
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
7.3 32M1-A
D
D1
1 0
2
3 Pin 1 ID
E1 E SIDE VIEW
TOP VIEW A3
A1
A2
K A
0.08 C COMMON DIMENSIONS
(Unit of Measure = mm)
P
P D2 SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00
Pin #1 Notch 1 A1 0.02 0.05
(0.20 R) 2 A2 0.65 1.00
3 A3 0.20 REF
b 0.23 0.30
E2 D 0.18 5.00 5.10
D1 4.90 4.75 4.80
K D2 4.70 3.10 3.25
E 2.95 5.00 5.10
b e L E1 4.90 4.75 4.80
E2 4.70 3.10 3.25
BOTTOM VIEW e 2.95 0.50 BSC
L 0.40 0.50
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. P 0.30 0.60
12o
0
K 0.20
5/25/06
TITLE DRAWING NO. REV.
2325 Orchard Parkway 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,
R San Jose, CA 95131 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) 32M1-A E
25
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
7.4 28P3
D PIN
1
E1
A
SEATING PLANE A1
B2
L
e B1 B (4 PLACES)
E
C 0 ~ 15 REF COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
eB A 4.5724
A1 0.508
D 34.544 34.798 Note 1
E 7.620 8.255
E1 7.112 7.493 Note 1
B 0.381 0.533
Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. B1 1.143 1.397
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B2 0.762 1.143
L 3.175 3.429
C 0.203 0.356
eB 10.160
e 2.540 TYP
09/28/01
TITLE DRAWING NO. REV.
2325 Orchard Parkway 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual
R San Jose, CA 95131 Inline Package (PDIP) 28P3 B
26
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
8. Errata
8.1 Errata ATmega48A
The revision letter in this section refers to the revision of the ATmega48A device.
8.1.1 Rev. D
Analog MUX can be turned off when setting ACME bit
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in
ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
8.2 Errata ATmega48PA
The revision letter in this section refers to the revision of the ATmega48PA device.
8.2.1 Rev. D
Analog MUX can be turned off when setting ACME bit
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in
ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
8.3 Errata ATmega88A
The revision letter in this section refers to the revision of the ATmega88A device.
8.3.1 Rev. F
Analog MUX can be turned off when setting ACME bit
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in
ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
27
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
8.4 Errata ATmega88PA
The revision letter in this section refers to the revision of the ATmega88PA device.
8.4.1 Rev. F
Analog MUX can be turned off when setting ACME bit
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in
ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
8.5 Errata ATmega168A
The revision letter in this section refers to the revision of the ATmega168A device.
8.5.1 Rev. E
Analog MUX can be turned off when setting ACME bit
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in
ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
8.6 Errata ATmega168PA
The revision letter in this section refers to the revision of the ATmega168PA device.
8.6.1 Rev E
Analog MUX can be turned off when setting ACME bit
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in
ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
28
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
8.7 Errata ATmega328
The revision letter in this section refers to the revision of the ATmega328 device.
8.7.1 Rev D
Analog MUX can be turned off when setting ACME bit
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in
ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
8.7.2 Rev C
Not sampled.
8.7.3 Rev B
Analog MUX can be turned off when setting ACME bit
Unstable 32 kHz Oscillator
1. Unstable 32 kHz Oscillator
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in
ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
2. Unstable 32 kHz Oscillator
The 32 kHz oscillator does not work as system clock. The 32 kHz oscillator used as asyn-
chronous timer is inaccurate.
Problem Fix/ Workaround
None.
8.7.4 Rev A
Analog MUX can be turned off when setting ACME bit
Unstable 32 kHz Oscillator
1. Unstable 32 kHz Oscillator
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in
ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
2. Unstable 32 kHz Oscillator
The 32 kHz oscillator does not work as system clock. The 32 kHz oscillator used as asyn-
chronous timer is inaccurate.
Problem Fix/ Workaround
None.
29
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
8.8 Errata ATmega328P
The revision letter in this section refers to the revision of the ATmega328P device.
8.8.1 Rev D
Analog MUX can be turned off when setting ACME bit
1. Analog MUX can be turned off when setting ACME bit
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in
ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
8.8.2 Rev C
Not sampled.
8.8.3 Rev B
Analog MUX can be turned off when setting ACME bit
Unstable 32 kHz Oscillator
1. Unstable 32 kHz Oscillator
If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in
ADMUX is '1' (ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.
Problem Fix/Workaround
Clear the MUX3 bit before setting the ACME bit.
2. Unstable 32 kHz Oscillator
The 32 kHz oscillator does not work as system clock. The 32 kHz oscillator used as asyn-
chronous timer is inaccurate.
Problem Fix/ Workaround
None.
8.8.4 Rev A
Unstable 32 kHz Oscillator
1. Unstable 32 kHz Oscillator
The 32 kHz oscillator does not work as system clock. The 32 kHz oscillator used as asyn-
chronous timer is inaccurate.
Problem Fix/ Workaround
None.
30
8271BSAVR04/10
ATmega48A/48PA/88A/88PA/168A/168PA/328/328P
9. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
9.1 Rev. 8271B-04/10
1. Updated Table 8-8 with correct value for timer oscilliator at xtal2/tos2
2. Corrected use of SBIS instructions in assembly code examples.
3. Corrected BOD and BODSE bits to R/W in Section 9.11.2 on page 45, Section 11.5 on page 69
and Section 13.4 on page 93
4. Figures for bandgap characterization added, Figure 29-34 on page 349, Figure 29-81 on page
374, Figure 29-128 on page 399, Figure 29-175 on page 424, Figure 29-222 on page 449, Fig-
ure 29-269 on page 474, Figure 29-316 on page 499 and Figure 29-363 on page 523.
5. Updated "Packaging Information" on page 546 by replacing 28M1 with a correct corresponding
package.
9.2 Rev. 8271A-12/09
1. New datasheet 8271 with merged information for ATmega48PA, ATmega88PA,
ATmega168PA and ATmega48A, ATmega88A andATmega168A. Also included
information on ATmega328 and ATmega328P
2 Changes done:
New devices added: ATmega48A/ATmega88A/ATmega168A and
ATmega328
Updated Feature Description
Updated Table 2-1 on page 6
Added note for BOD Disable on page 40.
Added note on BOD and BODSE in "MCUCR MCU Control Register" on
page 93 and "Register Description" on page 294
Added limitation informatin for the application "Boot Loader Support
Read-While-Write Self-Programming" on page 279
Added limitiation information for "Program And Data Memory Lock Bits" on
page 296
Added specified DC characteristice per processor
Added typical characteristics per processor
Removed execption information in "Address Match Unit" on page 223.
31
8271BSAVR04/10
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