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ATF1502ASL-25JJ84

器件型号:ATF1502ASL-25JJ84
器件类别:可编程逻辑器件    可编程逻辑   
厂商名称:Atmel (Microchip)
标准:
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器件描述

EE PLD, 25ns, PQCC44, PLASTIC, MS-018AC, LCC-44

参数
是否Rohs认证符合
零件包装代码LPCC
包装说明PLASTIC, MS-018AC, LCC-44
针数44
Reach Compliance Codecompliant
最大时钟频率60 MHz
JESD-30 代码S-PQCC-J44
JESD-609代码e3
长度16.5862 mm
湿度敏感等级2
专用输入次数
I/O 线路数量32
端子数量44
最高工作温度85 °C
最低工作温度-40 °C
组织0 DEDICATED INPUTS, 32 I/O
输出函数MACROCELL
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装形状SQUARE
封装形式CHIP CARRIER
峰值回流温度(摄氏度)245
可编程逻辑类型EE PLD
传播延迟25 ns
认证状态Not Qualified
座面最大高度4.57 mm
最大供电电压5.5 V
最小供电电压4.5 V
标称供电电压5 V
表面贴装YES
温度等级INDUSTRIAL
端子面层MATTE TIN
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
处于峰值回流温度下的最长时间40
宽度16.5862 mm
Base Number Matches1

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Features
High-density, High-performance, Electrically-erasable Complex Programmable Logic
Device
– 32 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44 pin
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation Up To 125 MHz
– Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
– D/T/Latch Configurable Flip Flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic utilization by burying a register with a COM output
Advanced Power Management Features
– Automatic 3 mA Stand-By for “L” Version
– Pin-Controlled 4 mA Standby Mode (Typical)
– Programmable Pin-Keeper Inputs and I/Os
– Reduced-power Feature Per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-pin PLCC, TQFP, and PQFP
Advanced EEPROM Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-Up Immunity
JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
3.3 or 5.0V I/O pins
Security Fuse Feature
High-
performance
EEPROM CPLD
ATF1502AS
Preliminary
Enhanced Features
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D - Latch Mode
Combinatorial Output with Registered Feedback within any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-Keeper” Option
V
CC
Power-Up Reset Option
Pull-Up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge Controlled Power Down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Rev. 0995C–09/99
1
44-lead TQFP/PQFP
Top View
I/O
I/O
I/O/PD1
VCC/PD2
I/OE2/GCK2
GCLR/I
I/OE1
GCK1/I
GND
GCK3
I/O
44-lead PLCC
Top View
I/O
I/O
I/O/PD1
VCC/PD2
GCK2/OE2/I
GCLR/I
OE1/I
GCK1/I
GND
I/O/GCLK3
I/O
33
32
31
30
29
28
27
26
25
24
23
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
44
43
42
41
40
39
38
37
36
35
34
I/O/TDI
I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
VCC
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Description
The ATF1502AS is a high performance, high density Com-
plex Programmable Logic Device (CPLD) which utilizes
Atmel’s proven electrically erasable technology. With 32
logic macrocells and up to 36 inputs, it easily integrates
logic from several TTL, SSI,MSI, LSI and classic PLDs.
The ATF1502AS’s enhanced routing switch matrices
increase usable gate count, and the odds of successful pin-
locked design modifications.
The ATF1502AS has up to 32 bi-directional I/O pins and 4
dedicated input pins, depending on the type of device pack-
age selected. Each dedicated pin can also serve as a
global control signal; register clock, register reset or output
enable. Each of these control signals can be selected for
use individually within each macrocell.
2
ATF1502AS
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
18
19
20
21
22
23
24
25
26
27
28
TDI/I/O
I/O
I/O
GND
PD1/I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
ATF1502AS
Block Diagram
B
32
Each of the 32 macrocells generates a buried feedback,
which goes to the global bus. Each input and I/O pin also
feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus.
Each macrocell also generates a foldback logic term, which
goes to a regional bus. Cascade logic between macrocells
in the ATF1502AS allows fast, efficient generation of com-
plex logic functions. The ATF1502AS contains four such
logic chains, each capable of creating sum term logic with a
fan in of up to 40 product terms.
The ATF1502AS macrocell shown in Figure 1, is flexible
enough to support highly complex logic functions operating
at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer;
OR/XOR/CASCADE logic; a flip-flop; output select and
enable; and logic array inputs.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A Security Fuse,
when programmed, protects the contents of the
ATF1502AS. Two bytes (16-bits) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision or date. The User Signature is
accessible regardless of the state of the Security Fuse.
The ATF1502AS device is an In-System Programmable
(ISP) device. It uses the industry standard 4-pin JTAG
interface (IEEE Std. 1149.1), and is fully compliant with
JTAG’s Boundary Scan Description Language (BSDL). ISP
allows the device to be programmed without removing it
from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to
be made in the field via software.
3
Figure 1.
ATF1502AS Macrocell
Product Terms and Select MUX
Each ATF1502AS macrocell has five product terms. Each
product term receives as its inputs all signals from both the
global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is deter-
mined by the design compiler, which selects the optimum
macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1502AS’s logic structure is designed to efficiently
support all types of logic. Within a single macrocell, all the
product terms can be routed to the OR gate, creating a 5-
input AND/OR sum term. With the addition of the CASIN
from neighboring macrocells, this can be expanded to as
many as 40 product terms with a very small additional
delay.
The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato-
rial outputs, the fixed level input allows polarity selection.
For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used
to emulate T- and JK-type flip-flops.
Flip Flop
The ATF1502AS’s flip flop has very flexible data and con-
trol functions. The data input can come from either the XOR
gate, from a separate product term or directly from the I/O
pin. Selecting the separate product term allows creation of
a buried registered feedback within a combinatorial output
macrocell. (This feature is automatically implemented by
the fitter software). In addition to D, T, JK and SR opera-
tion, the flip flop can also be configured as a flow-through
latch. In this mode, data passes through when the clock is
high and is latched when the clock is low.
The clock itself can either be one of the Global CLK Signal
GCK[0 : 2] or an individual product term. The flip flop
changes state on the clock’s rising edge. When the GCK
signal is used as the clock, one of the macrocell product
terms can be selected as a clock enable. When the clock
enable function is active and the enable signal (product
term) is low, all clock edges are ignored. The flip flop’s
asynchronous reset signal (AR) can be either the Global
Clear (GCLEAR), a product term, or always off. AR can
also be a logic OR of GCLEAR with a product term. The
asynchronous preset (AP) can be a product term or always
off.
Output Select and Enable
The ATF1502AS macrocell output can be selected as reg-
istered or combinatorial. The buried feedback signal can be
either combinatorial or registered signal regardless of
whether the output is combinatorial or registered.
4
ATF1502AS
ATF1502AS
The output enable multiplexer (MOE) controls the output
enable signals. Any buffer can be permanently enabled for
simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configu-
ration all the macrocell resources are still available,
including the buried feedback, expander and CASCADE
logic. The output enable for each macrocell can be
selected as either of the two dedicated OE input pins as an
I/O pin configured as an input, or as an individual product
term.
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well
as the buried feedback signal from all 32 macrocells. The
Switch Matrix in each Logic Block receives as its inputs all
signals from the global bus. Under software control, up to
40 of these signals can be selected as inputs to the Logic
Block.
Foldback Bus
Each macrocell also generates a foldback product term.
This signal goes to the regional bus and is available to 4
macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 4 foldback terms in each
region allows generation of high fan-in sum terms (up to 9
product terms) with a small additional delay.
Input Diagram
I/O Diagram
Programmable Pin-Keeper Option for
Inputs and I/Os
The ATF1502AS offers the option of programming all input
and I/O pins so that pin keeper circuits can be utilized.
When any pin is driven high or low and then subsequently
left floating, it will stay at that previous high or low level.
This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which cause unnec-
essary power consumption and system noise. The keeper
circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
Speed/Power Management
The ATF1502AS has several built-in speed and power
management features. The ATF1502AS contains circuitry
that automatically puts the device into a low power stand-
by mode when no logic transitions are occurring. This not
only reduces power consumption during inactive periods,
but also provides a proportional power savings for most
applications running at system speeds below 50 MHz. This
feature may be selected as a design option.
To further reduce power, each ATF1502AS macrocell has
a Reduced Power bit feature. This feature allows individual
macrocells to be configured for maximum power savings.
This feature may be selected as a design option.
The ATF1502ASs also has an optional power down mode.
In this mode, current drops to below 10 mA. When the
power down option is selected, either PD1 or PD2 pins (or
both) can be used to power down the part. The power down
option is selected in the design source file. When enabled,
the device goes into power down when either PD1 or PD2
is high. In the power down mode, all internal logic signals
are latched and held, as are any enabled outputs.
5
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