Features 32-bit Atmel
AVR
High-performance, Low-power 32-bit Atmel AVR Microcontroller Microcontroller
Compact Single-cycle RISC Instruction Set Including DSP Instructions
Read-modify-write Instructions and Atomic Bit Manipulation AT32UC3L0256
Performance AT32UC3L0128
Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State)
Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State) Summary
Memory Protection Unit (MPU)
Secure Access Unit (SAU) providing User-defined Peripheral Protection
picoPower Technology for Ultra-low Power Consumption
Multi-hierarchy Bus System
High-performance Data Transfers on Separate Buses for Increased Performance
12 Peripheral DMA Channels Improve Speed for Peripheral Communication
Internal High-speed Flash
256Kbytes and 128Kbytes Versions
Single-cycle Access up to 25MHz
FlashVault Technology Allows Pre-programmed Secure Library Support for End
User Applications
Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
100,000 Write Cycles, 15-year Data Retention Capability
Flash Security Locks and User-defined Configuration Area
Internal High-speed SRAM, Single-cycle Access at Full Speed
32Kbytes
Interrupt Controller (INTC)
Autovectored Low-latency Interrupt Service with Programmable Priority
External Interrupt Controller (EIC)
Peripheral Event System for Direct Peripheral to Peripheral Communication
System Functions
Power and Clock Manager
SleepWalking Power Saving Control
Internal System RC Oscillator (RCSYS)
32 KHz Oscillator
Multipurpose Oscillator, Phase Locked Loop (PLL), and Digital Frequency Locked
Loop (DFLL)
Windowed Watchdog Timer (WDT)
Asynchronous Timer (AST) with Real-time Clock Capability
Counter or Calendar Mode Supported
Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
Six 16-bit Timer/Counter (TC) Channels
External Clock Inputs, PWM, Capture, and Various Counting Capabilities
PWM Channels on All I/O Pins (PWMA)
8-bit PWM with a Source Clock up to 150MHz
Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
Independent Baudrate Generator, Support for SPI
Support for Hardware Handshaking
One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals
Up to 15 SPI Slaves can be Addressed
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Two Master and Two Slave Two-wire Interfaces (TWI), 400kbit/s I2C-compatible
One 8-channel Analog-to-digital Converter (ADC) with up to 12 Bits Resolution
Internal Temperature Sensor
Eight Analog Comparators (AC) with Optional Window Detection
Capacitive Touch (CAT) Module
Hardware-assisted Atmel AVR QTouch and Atmel AVR QMatrix Touch Acquisition
Supports QTouch and QMatrix Capture from Capacitive Touch Sensors
QTouch Library Support
Capacitive Touch Buttons, Sliders, and Wheels
QTouch and QMatrix Acquisition
On-chip Non-intrusive Debug System
Nexus Class 2+, Runtime Control, Non-intrusive Data and Program Trace
aWire Single-pin Programming Trace and Debug Interface Muxed with Reset Pin
NanoTrace Provides Trace Capabilities through JTAG or aWire Interface
48-pin TQFP/QFN/TLLGA (36 GPIO Pins)
Five High-drive I/O Pins
Single 1.62-3.6 V Power Supply
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1. Description
The Atmel AVR AT32UC3L0128/256 is a complete system-on-chip microcontroller based on
the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-per-
formance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications,
with particular emphasis on low power consumption, high code density, and high performance.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-
troller for supporting modern and real-time operating systems. The Secure Access Unit (SAU) is
used together with the MPU to provide the required security and integrity.
Higher computation capability is achieved using a rich set of DSP instructions.
The AT32UC3L0128/256 embeds state-of-the-art picoPower technology for ultra-low power con-
sumption. Combined power control techniques are used to bring active current consumption
down to 174A/MHz, and leakage down to 220nA while still retaining a bank of backup regis-
ters. The device allows a wide range of trade-offs between functionality and power consumption,
giving the user the ability to reach the lowest possible power consumption with the feature set
required for the application.
The Peripheral Direct Memory Access (DMA) controller enables data transfers between periph-
erals and memories without processor involvement. The Peripheral DMA controller drastically
reduces processing overhead when transferring continuous and large data streams.
The AT32UC3L0128/256 incorporates on-chip Flash and SRAM memories for secure and fast
access. The FlashVault technology allows secure libraries to be programmed into the device.
The secure libraries can be executed while the CPU is in Secure State, but not read by non-
secure software in the device. The device can thus be shipped to end customers, who will be
able to program their own code into the device to access the secure libraries, but without risk of
compromising the proprietary secure code.
The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each
external interrupt has its own interrupt request and can be individually masked.
The Peripheral Event System allows peripherals to receive, react to, and send peripheral events
without CPU intervention. Asynchronous interrupts allow advanced peripheral operation in low
power sleep modes.
The Power Manager (PM) improves design flexibility and security. The Power Manager supports
SleepWalking functionality, by which a module can be selectively activated based on peripheral
events, even in sleep modes where the module clock is stopped. Power monitoring is supported
by on-chip Power-on Reset (POR), Brown-out Detector (BOD), and Supply Monitor (SM). The
device features several oscillators, such as Phase Locked Loop (PLL), Digital Frequency
Locked Loop (DFLL), Oscillator 0 (OSC0), and system RC oscillator (RCSYS). Either of these
oscillators can be used as source for the system clock. The DFLL is a programmable internal
oscillator from 20 to 150MHz. It can be tuned to a high accuracy if an accurate reference clock is
running, e.g. the 32KHz crystal oscillator.
The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the soft-
ware. This allows the device to recover from a condition that has caused the system to be
unstable.
The Asynchronous Timer (AST) combined with the 32KHz crystal oscillator supports powerful
real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in
counter mode or calendar mode.
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The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it
to a known reference clock.
The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde-
pendently programmed to perform frequency measurement, event counting, interval
measurement, pulse generation, delay timing, and pulse width modulation.
The Pulse Width Modulation controller (PWMA) provides 8-bit PWM channels which can be syn-
chronized and controlled from a common timer. One PWM channel is available for each I/O pin
on the device, enabling applications that require multiple PWM outputs, such as LCD backlight
control. The PWM channels can operate independently, with duty cycles set individually, or in
interlinked mode, with multiple channels changed at the same time.
The AT32UC3L0128/256 also features many communication interfaces, like USART, SPI, and
TWI, for communication intensive applications. The USART supports different communication
modes, like SPI Mode and LIN Mode.
A general purpose 8-channel ADC is provided, as well as eight analog comparators (AC). The
ADC can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering
up to 12-bit resolution. The ADC also provides an internal temperature sensor input channel.
The analog comparators can be paired to detect when the sensing voltage is within or outside
the defined reference window.
The Capacitive Touch (CAT) module senses touch on external capacitive touch sensors, using
the QTouch technology. Capacitive touch sensors use no external mechanical components,
unlike normal push buttons, and therefore demand less maintenance in the user application.
The CAT module allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced.
All touch sensors can be configured to operate autonomously without software interaction,
allowing wakeup from sleep modes when activated.
Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers
robust sensing and includes fully debounced reporting of touch keys as well as Adjacent Key
Suppression (AKS) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications.
The AT32UC3L0128/256 integrates a class 2+ Nexus 2.0 On-chip Debug (OCD) System, with
non-intrusive real-time trace and full-speed read/write memory access, in addition to basic run-
time control. The NanoTrace interface enables trace feature for aWire- or JTAG-based
debuggers. The single-pin aWire interface allows all features available through the JTAG inter-
face to be accessed through the RESET pin, allowing the JTAG pins to be used for GPIO or
peripherals.
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2. Overview
2.1 Block Diagram
Figure 2-1. Block Diagram
MCKO MEMORY INTERFACE LOCAL BUS LOCAL BUS
MDO[5..0] INTERFACE
MSEO[1..0] AVR32UC CPU
TCK EVTI_N NEXUS MEMORY PROTECTION UNIT 32 KB
TDO EVTO_N CLASS 2+ SRAM
TDI
TMS JTAG OCD
INTERFACE
DATAOUT INSTR DATA
RESET_N aWire
INTERFACE INTERFACE
M M M S
HIGH SPEED FLASH 128/256 KB
CONTROLLER FLASH
SAU S/M BUS MATRIX S
S S M
CONFIGURATION REGISTERS BUS
HSB-PB HSB-PB PERIPHERAL
BRIDGE B BRIDGE A DMA
CONTROLLER
GENERALPURPOSE I/Os POWER MANAGER DMA CAPACITIVE TOUCH DIS
MODULE VDIVEN
PA CLOCK CSA[16:0]
PB USART0 CSB[16:0]
CONTROLLER USART1
USART2 SMP
SLEEP DMA USART3 SYNC
CONTROLLER
SPI RXD
RESET TXD
CONTROLLER CLK
RTS, CTS
GCLK_IN[1..0] DMA GENERAL PURPOSE I/Os
GCLK[4..0] SCK
MISO, MOSI
RCSYS NPCS[3..0]
RC32OUT RC32K
TWCK PA
RC120M SYSTEM CONTROL DMA TWI MASTER 0 TWD PB
OSC32K INTERFACE
XIN32 TWI MASTER 1 TWALM
XOUT32 OSC0 INTERRUPT
DFLL CONTROLLER TWI SLAVE 0 TWCK
XIN0 EXTERNAL INTERRUPT TWI SLAVE 1 TWD
XOUT0 CONTROLLER TWALM
DMA
PLL
DMA 8-CHANNEL ADC ADP[1..0]
INTERFACE TRIGGER
EXTINT[5..1]
NMI TIMER/COUNTER 0 AD[8..0]
TIMER/COUNTER 1 ADVREFP
PWMA[35..0] PWM CONTROLLER
A[2..0]
ASYNCHRONOUS B[2..0]
TIMER CLK[2..0]
WATCHDOG AC INTERFACE ACBP[3..0]
TIMER ACBN[3..0]
GLUE LOGIC ACAP[3..0]
FREQUENCY METER CONTROLLER ACAN[3..0]
ACREFN
OUT[1:0]
IN[7..0]
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2.2 Configuration Summary
Table 2-1. Configuration Summary
Feature AT32UC3L0256 AT32UC3L0128
Flash 256 KB 128 KB
SRAM 32 KB
GPIO 36
High-drive pins 5
External Interrupts 6
TWI 2
USART 4
Peripheral DMA Channels 12
Peripheral Event System 1
SPI 1
Asynchronous Timers 1
Timer/Counter Channels 6
PWM channels 36
Frequency Meter 1
Watchdog Timer 1
Power Manager 1
Secure Access Unit 1
Glue Logic Controller 1
Oscillators Digital Frequency Locked Loop 20-150 MHz (DFLL)
Phase Locked Loop 40-240 MHz (PLL)
Crystal Oscillator 0.45-16 MHz (OSC0)
Crystal Oscillator 32 KHz (OSC32K)
RC Oscillator 120MHz (RC120M)
RC Oscillator 115 kHz (RCSYS)
RC Oscillator 32 kHz (RC32K)
ADC 8-channel 12-bit
Temperature Sensor 1
Analog Comparators 8
Capacitive Touch Module 1
JTAG 1
aWire 1
Max Frequency 50 MHz
Packages TQFP48/QFN48/TLLGA48
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3. Package and Pinout
3.1 Package
The device pins are multiplexed with peripheral functions as described in Section 3.2.1.
Figure 3-1. TQFP48/QFN48 Pinout
PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20
36 35 34 33 32 31 30 29 28 27 26 25
PA15 37 24 PA21
PA16 38 23 PB10
PA17 39 22 RESET_N
PA19 40 21 PB04
PA18 41 20 PB05
VDDIO 42 19 GND
GND 43 18 VDDCORE
PB11 44 17 VDDIN
GND 45 16 PB01
PA10 46 15 PA07
PA12 47 14 PA01
VDDIO 48 13 PA02
1 2 3 4 5 6 7 8 9 10 11 12
GND PA09 PA08 PA03 PB12 PB00 PB02 PB03 PA22 PA06 PA00 PA05
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Figure 3-2. TLLGA48 Pinout
PA15 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20
37 36 35 34 33 32 31 30 29 28 27 26 25
PA16 38 24 PA21
PA17 39 23 PB10
PA19 40 22 RESET_N
PA18 41 21 PB04
VDDIO 42 20 PB05
GND 43 19 GND
PB11 44 18 VDDCORE
GND 45 17 VDDIN
PA10 46 16 PB01
PA12 47 15 PA07
VDDIO 48 14 PA01
1 2 3 4 5 6 7 8 9 10 11 12 13
GND PA09 PA08 PA03 PB12 PB00 PB02 PB03 PA22 PA06 PA00 PA05 PA02
3.2 Peripheral Multiplexing on I/O Lines
3.2.1 Multiplexed Signals
Each GPIO line can be assigned to one of the peripheral functions. The following table
describes the peripheral signals multiplexed to the GPIO lines.
Table 3-1. GPIO Controller Function Multiplexing
G GPIO Function
P
48- I Pin
pin PIN O Supply Type A B C D E F G H
11 PA00 0 VDDIO Normal USART0 USART1 SPI USART1 PWMA ACIFB SCIF CAT
I/O TXD RTS NPCS[2] CLK PWMA[0] ACAP[0] GCLK[0] CSA[2]
14 PA01 1 VDDIO Normal USART0 USART1 SPI PWMA TWIMS0 CAT
I/O RXD CTS NPCS[3] PWMA[1] TWALM CSA[1]
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Table 3-1. GPIO Controller Function Multiplexing
13 PA02 2 VDDIO High- USART0 ADCIFB USART2 TC0 PWMA ACIFB USART0 CAT
drive I/O RTS TRIGGER TXD A0 PWMA[2] ACBP[0] CLK CSA[3]
TC0 ACIFB
4 PA03 3 VDDIO Normal USART0 SPI USART2 B0 PWMA ACBN[3] USART0 CAT
I/O CTS NPCS[1] TXD TC0 PWMA[3] ACIFB CLK CSB[3]
B1 ACBP[1]
28 PA04 4 VDDIO Normal SPI TWIMS0 USART1 TC0 PWMA ACIFB TWIMS0 CAT
I/O MISO TWCK RXD A1 PWMA[4] ACBN[0] TWD CSA[7]
12 PA05 5 VDDIO Normal SPI TWIMS1 USART1 TC0 PWMA EIC CAT
I/O (TWI) MOSI TWCK TXD B0 PWMA[5] EXTINT[2] CSB[7]
High- USART1 TWIMS0 PWMA ACIFB
CLK TWCK PWMA[6] ACAN[0]
10 PA06 6 VDDIO drive I/O, SPI USART2 SCIF CAT
5V SCK TXD TWIMS1 ADCIFB PWMA SCIF GCLK[1] CSB[1]
TWALM ADP[0] PWMA[7] GCLK[2]
tolerant ADCIFB ACIFB
TC0 ADP[1] PWMA ACAP[1]
15 PA07 7 VDDIO Normal SPI USART2 A2 PWMA[8] EIC CAT
I/O (TWI) NPCS[0] RXD TC0 CAT NMI CSB[2]
B2 SMP PWMA (EXTINT[0])
3 PA08 8 VDDIO High- USART1 SPI TC0 SCIF PWMA[9] CAT
drive I/O TXD NPCS[2] A0 GCLK[2] EIC CSA[4]
CAT PWMA EXTINT[1]
2 PA09 9 VDDIO High- USART1 SPI TC0 SMP PWMA[10] CAT
drive I/O RXD NPCS[3] CLK1 GLOC SCIF CSB[4]
TC0 IN[6] PWMA GCLK[2]
46 PA10 10 VDDIO Normal TWIMS0 USART2 GLOC PWMA[11] CAT
I/O TWD CLK A0 IN[5] CSA[5]
GLOC USART2 TWIMS1 PWMA
27 PA11 11 VDDIN Normal IN[7] TWD PWMA[12]
I/O TC0 RTS GLOC
CLK2 IN[4] PWMA
47 PA12 12 VDDIO Normal TC0 USART2 TWIMS1 PWMA[13] ACIFB SCIF CAT
I/O CLK1 CTS TWALM ACAN[1] GCLK[3] CSB[5]
TC0 GLOC PWMA
26 PA13 13 VDDIN Normal GLOC CLK0 TC0 IN[3] PWMA[14] CAT EIC CAT
I/O OUT[0] TC0 A2 SMP EXTINT[2] CSA[0]
A1 TC0 PWMA
36 PA14 14 VDDIO Normal ADCIFB TC0 A1 PWMA[15] CAT SCIF CAT
I/O AD[0] B1 SYNC GCLK[4] CSA[6]
TC0 PWMA ACIFB
37 PA15 15 VDDIO Normal ADCIFB TWIMS0 B1 PWMA[16] ACREFN EIC CAT
I/O AD[1] TWD CAT EXTINT[3] CSB[6]
TC0 PWMA SMP
38 PA16 16 VDDIO Normal ADCIFB USART2 B2 PWMA[17] CAT EIC CAT
I/O AD[2] CLK SPI SYNC EXTINT[4] CSA[8]
NPCS[0] PWMA SCIF
39 PA17 17 VDDIO Normal ADCIFB SPI PWMA[18] GCLK_IN[0] CAT CAT
I/O (TWI) ADP[0] SCK SCIF DIS CSB[8]
ADCIFB SPI PWMA RC32OUT
41 PA18 18 VDDIO Normal ADCIFB ADP[1] MISO PWMA[19] EIC CAT
I/O AD[4] USART3 EXTINT[5] CSB[0]
PWMA
40 PA19 19 VDDIO Normal ADCIFB CLK PWMA[20] CAT CAT
I/O AD[5] SYNC CSA[10]
25 PA20 20 VDDIN Normal USART2 CAT
I/O TXD CSA[12]
Normal
24 PA21 21 VDDIN I/O (TWI, USART2 ADCIFB PWMA PWMA SCIF CAT
5V RXD
TRIGGER PWMA[21] PWMAOD[21] GCLK[0] SMP
tolerant,
SMBus)
9 PA22 22 VDDIO Normal USART0 CAT PWMA ACIFB CAT
I/O CTS CSB[10]
SMP PWMA[22] ACBN[2]
CAT
6 PB00 32 VDDIO Normal USART3 TC0 PWMA ACIFB TC1 CSA[9]
I/O TXD A0
A1 PWMA[23] ACAP[2] CAT
TC1 CSB[9]
16 PB01 33 VDDIO High- USART3 TC0 PWMA A1
drive I/O RXD CAT
B1 PWMA[24] SCIF CSB[11]
GCLK[1]
7 PB02 34 VDDIO Normal USART3 TC0 PWMA ACIFB
I/O RTS
A2 PWMA[25] ACAN[2]
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Table 3-1. GPIO Controller Function Multiplexing
8 PB03 35 VDDIO Normal USART3 USART3 SPI TC0 PWMA ACIFB TC1 CAT
I/O CTS CLK MOSI
B2 PWMA[26] ACBP[2] A2 CSA[11]
USART1
Normal CLK
I/O (TWI, TC1 USART1 TWIMS0 PWMA PWMA TWIMS1 CAT
A0 RTS TWALM PWMA[27] PWMAOD[27] TWCK CSA[14]
21 PB04 36 VDDIN 5V
tolerant,
SMBus)
Normal
I/O (TWI, TC1 USART1 USART1 TWIMS0 PWMA PWMA SCIF CAT
B0 CTS CLK TWCK PWMA[28] PWMAOD[28] GCLK[3] CSB[14]
20 PB05 37 VDDIN 5V
tolerant,
SMBus)
30 PB06 38 VDDIO Normal TC1 USART3 ADCIFB GLOC PWMA ACIFB EIC CAT
I/O A1 TXD AD[6] IN[2] PWMA[29] ACAN[3] NMI CSB[13]
(EXTINT[0])
31 PB07 39 VDDIO Normal TC1 USART3 ADCIFB GLOC PWMA ACIFB CAT
I/O B1 RXD AD[7] IN[1] PWMA[30] ACAP[3] EIC CSA[13]
ADCIFB GLOC EXTINT[1]
32 PB08 40 VDDIO Normal TC1 USART3 AD[8] IN[0] PWMA CAT CAT
I/O A2 RTS USART3 PWMA[31] SYNC EIC CSB[12]
CLK GLOC EXTINT[2]
29 PB09 41 VDDIO Normal TC1 USART3 USART3 OUT[1] PWMA ACIFB CAT
I/O B2 CTS CLK ADCIFB PWMA[32] ACBN[1] EIC CSB[15]
TRIGGER EXTINT[3]
23 PB10 42 VDDIN Normal TC1 USART1 TWIMS1 PWMA SCIF CAT
I/O CLK0 TXD TWALM CAT PWMA[33] GCLK_IN[1] EIC CSB[16]
SYNC EXTINT[4]
44 PB11 43 VDDIO Normal TC1 USART1 PWMA CAT CAT
I/O CLK1 RXD PWMA[34] VDIVEN EIC CSA[16]
EXTINT[5]
5 PB12 44 VDDIO Normal TC1 PWMA ACIFB CAT
I/O CLK2 PWMA[35] ACBP[3] SCIF CSA[15]
GCLK[4]
See Section 3.3 for a description of the various peripheral signals.
Refer to "Electrical Characteristics" on page 41 for a description of the electrical properties of the
pin types used.
3.2.2 TWI, 5V Tolerant, and SMBUS Pins
Some normal I/O pins offer TWI, 5V tolerance, and SMBUS features. These features are only
available when either of the TWI functions or the PWMAOD function in the PWMA are selected
for these pins.
Refer to the "TWI Pin Characteristics(1)" on page 48 for a description of the electrical properties
of the TWI, 5V tolerance, and SMBUS pins.
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3.2.3 Peripheral Functions
Each GPIO line can be assigned to one of several peripheral functions. The following table
describes how the various peripheral functions are selected. The last listed function has priority
in case multiple functions are enabled on the same pin.
Table 3-2. Peripheral Functions Description
Function GPIO and GPIO peripheral selection A to H
GPIO Controller Function multiplexing OCD trace system
Nexus OCD AUX port connections aWire output in two-pin mode
aWire DATAOUT JTAG debug port
JTAG port connections OSC0, OSC32
Oscillators
3.2.4 JTAG Port Connections
If the JTAG is enabled, the JTAG will take control over a number of pins, irrespectively of the I/O
Controller configuration.
Table 3-3. JTAG Pinout Pin name JTAG pin
48-pin PA00 TCK
11 PA01 TMS
14 PA02 TDO
13 PA03 TDI
4
3.2.5 Nexus OCD AUX Port Connections
If the OCD trace system is enabled, the trace system will take control over a number of pins, irre-
spectively of the I/O Controller configuration. Two different OCD trace pin mappings are
possible, depending on the configuration of the OCD AXS register. For details, see the AVR32
UC Technical Reference Manual.
Table 3-4. Nexus OCD AUX Port Connections
Pin
EVTI_N AXS=1 AXS=0
MDO[5]
MDO[4] PA05 PB08
MDO[3]
MDO[2] PA10 PB00
MDO[1]
MDO[0] PA18 PB04
PA17 PB05
PA16 PB03
PA15 PB02
PA14 PB09
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Table 3-4. Nexus OCD AUX Port Connections
Pin
EVTO_N AXS=1 AXS=0
MCKO
MSEO[1] PA04 PA04
MSEO[0]
PA06 PB01
PA07 PB11
PA11 PB12
3.2.6 Oscillator Pinout
The oscillators are not mapped to the normal GPIO functions and their muxings are controlled
by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more
information about this.
Table 3-5. Oscillator Pinout
48-pin
Pin Name Oscillator Pin
3 PA08 XIN0
46 PA10 XIN32
26 PA13
2 PA09 XIN32_2
47 PA12 XOUT0
25 PA20 XOUT32
XOUT32_2
3.2.7 Other Functions
The functions listed in Table 3-6 are not mapped to the normal GPIO functions. The aWire DATA
pin will only be active after the aWire is enabled. The aWire DATAOUT pin will only be active
after the aWire is enabled and the 2_PIN_MODE command has been sent. The WAKE_N pin is
always enabled. Please refer to Section 6.1.4 on page 40 for constraints on the WAKE_N pin.
Table 3-6. Other Functions Pin Function
48-pin PA11 WAKE_N
27 RESET_N aWire DATA
22 PA00 aWire DATAOUT
11
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3.3 Signal Descriptions
The following table gives details on signal names classified by peripheral.
Table 3-7. Signal Descriptions List
Signal Name Function Type Active Comments
Level
Analog Comparator Interface - ACIFB
ACAN3 - ACAN0 Negative inputs for comparators "A" Analog
ACAP3 - ACAP0 Positive inputs for comparators "A" Analog
ACBN3 - ACBN0 Negative inputs for comparators "B" Analog
ACBP3 - ACBP0 Positive inputs for comparators "B" Analog
ACREFN Common negative reference Analog
ADC Interface - ADCIFB
AD8 - AD0 Analog Signal Analog
ADP1 - ADP0 Drive Pin for resistive touch screen Output
TRIGGER External trigger Input
aWire - AW
DATA aWire data I/O
DATAOUT aWire data output for 2-pin mode I/O
Capacitive Touch Module - CAT
CSA16 - CSA0 Capacitive Sense A I/O
CSB16 - CSB0 Capacitive Sense B I/O
DIS Discharge current control Analog
SMP SMP signal Output
SYNC Synchronize signal Input
VDIVEN Voltage divider enable Output
External Interrupt Controller - EIC
NMI (EXTINT0) Non-Maskable Interrupt Input
EXTINT5 - EXTINT1 External interrupt Input
Glue Logic Controller - GLOC
IN7 - IN0 Inputs to lookup tables Input
OUT1 - OUT0 Outputs from lookup tables Output
JTAG module - JTAG
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
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Table 3-7. Signal Descriptions List
Power Manager - PM
RESET_N Reset Input Low
Pulse Width Modulation Controller - PWMA
PWMA35 - PWMA0 PWMA channel waveforms Output
PWMAOD35 - PWMA channel waveforms, open drain Output Not all channels support open
PWMAOD0 mode drain mode
System Control Interface - SCIF
GCLK4 - GCLK0 Generic Clock Output Output
GCLK_IN1 - GCLK_IN0 Generic Clock Input Input
RC32OUT RC32K output at startup Output
XIN0 Crystal 0 Input Analog/
Digital
XIN32 Crystal 32 Input (primary location) Analog/
Digital
XIN32_2 Crystal 32 Input (secondary location) Analog/
Digital
XOUT0 Crystal 0 Output Analog
XOUT32 Crystal 32 Output (primary location) Analog
XOUT32_2 Crystal 32 Output (secondary location) Analog
Serial Peripheral Interface - SPI
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
NPCS3 - NPCS0 SPI Peripheral Chip Select I/O Low
SCK Clock I/O
Timer/Counter - TC0, TC1
A0 Channel 0 Line A I/O
A1 Channel 1 Line A I/O
A2 Channel 2 Line A I/O
B0 Channel 0 Line B I/O
B1 Channel 1 Line B I/O
B2 Channel 2 Line B I/O
CLK0 Channel 0 External Clock Input Input
CLK1 Channel 1 External Clock Input Input
CLK2 Channel 2 External Clock Input Input
Two-wire Interface - TWIMS0, TWIMS1
TWALM SMBus SMBALERT I/O Low
TWCK Two-wire Serial Clock I/O
TWD Two-wire Serial Data I/O
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Table 3-7. Signal Descriptions List
CLK Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3
CTS
RTS Clock I/O
RXD
TXD Clear To Send Input Low
Request To Send Output Low
Receive Data Input
Transmit Data Output
Note: 1. ADCIFB: AD3 does not exist.
Table 3-8. Signal Description List, Continued
Signal Name Function Type Active
Level Comments
Power
VDDCORE Core Power Supply / Voltage Regulator Output Power 1.62V to 1.98V
Input/Output
VDDIO I/O Power Supply Power Input 1.62V to 3.6V. VDDIO should
always be equal to or lower than
VDDIN.
VDDANA Analog Power Supply Power Input 1.62V to 1.98V
ADVREFP Analog Reference Voltage Power Input 1.62V to 1.98V
VDDIN Voltage Regulator Input Power Input 1.62V to 3.6V (1)
GNDANA Analog Ground Ground
GND Ground Ground
Auxiliary Port - AUX
MCKO Trace Data Output Clock Output
MDO5 - MDO0 Trace Data Output Output
MSEO1 - MSEO0 Trace Frame Control Output
EVTI_N Event In Input Low
EVTO_N Event Out Output Low
General Purpose I/O pin
PA22 - PA00 Parallel I/O Controller I/O Port 0 I/O
PB12 - PB00 Parallel I/O Controller I/O Port 1 I/O
1. See Section 6.1 on page 36
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3.4 I/O Line Considerations
3.4.1 JTAG Pins
The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI
pins have pull-up resistors when JTAG is enabled. The TCK pin always has pull-up enabled dur-
ing reset. The TDO pin is an output, driven at VDDIO, and has no pull-up resistor. The JTAG
pins can be used as GPIO pins and multiplexed with peripherals when the JTAG is disabled.
Please refer to Section 3.2.4 on page 11 for the JTAG port connections.
3.4.2 PA00
Note that PA00 is multiplexed with TCK. PA00 GPIO function must only be used as output in the
application.
3.4.3 RESET_N Pin
The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIN. As
the product integrates a power-on reset detector, the RESET_N pin can be left unconnected in
case no reset from the system needs to be applied to the product.
The RESET_N pin is also used for the aWire debug protocol. When the pin is used for debug-
ging, it must not be driven by external circuitry.
3.4.4 TWI Pins PA21/PB04/PB05
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have
the same characteristics as other GPIO pins. Selected pins are also SMBus compliant (refer to
Section 3.2.1 on page 8). As required by the SMBus specification, these pins provide no leakage
path to ground when the AT32UC3L0128/256 is powered down. This allows other devices on
the SMBus to continue communicating even though the AT32UC3L0128/256 is not powered.
After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the
GPIO Module Configuration chapter for details.
3.4.5 TWI Pins PA05/PA07/PA17
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have
the same characteristics as other GPIO pins.
After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the
GPIO Module Configuration chapter for details.
3.4.6 GPIO Pins
All the I/O lines integrate a pull-up resistor. Programming of this pull-up resistor is performed
independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as
inputs with pull-up resistors disabled, except PA00 which has the pull-up resistor enabled. PA20
selects SCIF-RC32OUT (GPIO Function F) as default enabled after reset.
3.4.7 High-drive Pins
The five pins PA02, PA06, PA08, PA09, and PB01 have high-drive output capabilities. Refer to
Section 7. on page 41 for electrical characteristics.
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3.4.8 RC32OUT Pin
3.4.8.1 Clock output at startup
After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20,
even when the device is still reset by the Power-On Reset Circuitry. This clock can be used by
the system to start other devices or to clock a switching regulator to rise the power supply volt-
age up to an acceptable value.
The clock will be available on PA20, but will be disabled if one of the following conditions are
true:
PA20 is configured to use a GPIO function other than F (SCIF-RC32OUT)
PA20 is configured as a General Purpose Input/Output (GPIO)
The bit FRC32 in the Power Manager PPCR register is written to zero (refer to the Power
Manager chapter)
The maximum amplitude of the clock signal will be defined by VDDIN.
Once the RC32K output on PA20 is disabled it can never be enabled again.
3.4.8.2 XOUT32_2 function
PA20 selects RC32OUT as default enabled after reset. This function is not automatically dis-
abled when the user enables the XOUT32_2 function on PA20. This disturbs the oscillator and
may result in the wrong frequency. To avoid this, RC32OUT must be disabled when XOUT32_2
is enabled.
3.4.9 ADC Input Pins
These pins are regular I/O pins powered from the VDDIO. However, when these pins are used
for ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures
that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins
are not used for ADC inputs, the pins may be driven to the full I/O voltage range.
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4. Processor and Architecture
Rev: 2.1.2.0
This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the
AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre-
sented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical
Reference Manual.
4.1 Features
32-bit load/store AVR32A RISC architecture
15 general-purpose 32-bit registers
32-bit Stack Pointer, Program Counter and Link Register reside in register file
Fully orthogonal instruction set
Privileged and unprivileged modes enabling efficient and secure operating systems
Innovative instruction set together with variable instruction length ensuring industry leading
code density
DSP extension with saturating arithmetic, and a wide variety of multiply instructions
3-stage pipeline allowing one instruction per clock cycle for most instructions
Byte, halfword, word, and double word memory access
Multiple interrupt priority levels
MPU allows for operating systems with memory protection
Secure State for supporting FlashVault technology
4.2 AVR32 Architecture
AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for cost-
sensitive embedded applications, with particular emphasis on low power consumption and high
code density. In addition, the instruction set architecture has been tuned to allow a variety of
microarchitectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance
processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications.
Through a quantitative approach, a large set of industry recognized benchmarks has been com-
piled and analyzed to achieve the best code density in its class. In addition to lowering the
memory requirements, a compact code size also contributes to the core's low power characteris-
tics. The processor supports byte and halfword data types without penalty in code size and
performance.
Memory load and store operations are provided for byte, halfword, word, and double word data
with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely
linked to the architecture and is able to exploit code optimization features, both for size and
speed.
In order to reduce code size to a minimum, some instructions have multiple addressing modes.
As an example, instructions with immediates often have a compact format with a smaller imme-
diate, and an extended format with a larger immediate. In this way, the compiler is able to use
the format giving the smallest code size.
Another feature of the instruction set is that frequently used instructions, like add, have a com-
pact format with two operands as well as an extended format with three operands. The larger
format increases performance, allowing an addition and a data move in the same instruction in a
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single cycle. Load and store instructions have several different formats in order to reduce code
size and speed up execution.
The register file is organized as sixteen 32-bit registers and includes the Program Counter, the
Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values
from function calls and is used implicitly by some instructions.
4.3 The AVR32UC CPU
The AVR32UC CPU targets low- and medium-performance applications, and provides an
advanced On-Chip Debug (OCD) system, no caches, and a Memory Protection Unit (MPU).
Java acceleration hardware is not implemented.
AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch,
one High Speed Bus master for data access, and one High Speed Bus slave interface allowing
other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the
CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing.
Also, power consumption is reduced by not needing a full High Speed Bus access for memory
accesses. A dedicated data RAM interface is provided for communicating with the internal data
RAMs.
A local bus interface is provided for connecting the CPU to device-specific high-speed systems,
such as floating-point units and I/O controller ports. This local bus has to be enabled by writing a
one to the LOCEN bit in the CPUCR system register. The local bus is able to transfer data
between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated
memory range allocated to it, and data transfers are performed using regular load and store
instructions. Details on which devices that are mapped into the local bus space is given in the
CPU Local Bus section in the Memories chapter.
Figure 4-1 on page 20 displays the contents of AVR32UC.
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Figure 4-1. Overview of the AVR32UC CPU
Interrupt controller interface Power/
OCD interface Reset
Reset interfacecontrol
OCD
system
AVR32UC CPU pipeline
MPU
Instruction memory controller Data memory controller
High Speed Bus master
High Speed High CPU Local CPU RAM
Bus master Speed Bus
Bus slave
master
High Speed Bus
High Speed Bus
High Speed Bus
CPU Local Bus
4.3.1 Pipeline Overview
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 4-2 on page 21 shows an overview of the AVR32UC pipeline stages.
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Figure 4-2. The AVR32UC Pipeline
MUL Multiply unit
IF ID Regfile ALU Regfile ALU unit
Read write
Prefetch unit Decode unit
LS Load-store
unit
4.3.2 AVR32A Microarchitecture Compliance
AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar-
geted at cost-sensitive, lower-end applications like smaller microcontrollers. This
microarchitecture does not provide dedicated hardware registers for shadowing of register file
registers in interrupt contexts. Additionally, it does not provide hardware registers for the return
address registers and return status registers. Instead, all this information is stored on the system
stack. This saves chip area at the expense of slower interrupt handling.
4.3.2.1 Interrupt Handling
Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These
registers are pushed regardless of the priority level of the pending interrupt. The return address
and status register are also automatically pushed to stack. The interrupt handler can therefore
use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are
restored, and execution continues at the return address stored popped from stack.
The stack is also used to store the status register and return address for exceptions and scall.
Executing the rete or rets instruction at the completion of an exception or system call will pop
this status register and continue execution at the popped return address.
4.3.2.2 Java Support
AVR32UC does not provide Java hardware acceleration.
4.3.2.3 Memory Protection
4.3.2.4 The MPU allows the user to check all memory accesses for privilege violations. If an access is
attempted to an illegal memory address, the access is aborted and an exception is taken. The
MPU in AVR32UC is specified in the AVR32UC Technical Reference manual.
Unaligned Reference Handling
AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is
able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an
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address exception. Doubleword-sized accesses with word-aligned pointers will automatically be
performed as two word-sized accesses.
The following table shows the instructions with support for unaligned addresses. All other
instructions require aligned addresses.
Table 4-1. Instructions with Unaligned Reference Support
Instruction Supported Alignment
ld.d Word
st.d Word
4.3.2.5 Unimplemented Instructions
4.3.2.6 The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented
Instruction Exception if executed:
All SIMD instructions
All coprocessor instructions if no coprocessors are present
retj, incjosp, popjc, pushjc
tlbr, tlbs, tlbw
cache
CPU and Architecture Revision
Three major revisions of the AVR32UC CPU currently exist. The device described in this
datasheet uses CPU revision 3.
The Architecture Revision field in the CONFIG0 system register identifies which architecture
revision is implemented in a specific device.
AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled
for revision 1 or 2 is binary-compatible with revision 3 CPUs.
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4.4 Programming Model
4.4.1 Register File Configuration
The AVR32UC register file is shown below.
Figure 4-3. The AVR32UC Register File
Application Supervisor INT0 INT1 INT2 INT3 Exception NMI Secure
Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0
PC PC PC PC PC PC PC PC PC
LR LR LR LR LR LR LR LR LR
SP_APP SP_SYS SP_SYS SP_SYS SP_SYS SP_SYS SP_SYS SP_SYS SP_SEC
R12 R12 R12 R12 R12 R12 R12 R12 R12
R11 R11 R11 R11 R11 R11 R11 R11 R11
R10 R10 R10 R10 R10 R10 R10 R10 R10
R9 R9 R9 R9 R9 R9 R9 R9 R9
R8 R8 R8 R8 R8 R8 R8 R8 R8
INTR07PC INTR07PC INTR07PC INTR07PC INTR07PC INTR07PC INTR07PC INTR07PC INTR07PC
INTR16PC INTR16PC INTR16PC INTR16PC INTR16PC INTR16PC INTR16PC INTR16PC INTR16PC
FINRT5PC FINRT5PC FINRT5PC FINRT5PC FINRT5PC FINRT5PC FINRT5PC FINRT5PC FINRT5PC
SMRP4 C SMRP4 C SMRP4 C SMRP4 C SMRP4 C SMRP4 C SMRP4 C SMRP4 C SMRP4 C
R3 R3 R3 R3 R3 R3 R3 R3 R3
R2 R2 R2 R2 R2 R2 R2 R2 R2
R1 R1 R1 R1 R1 R1 R1 R1 R1
R0 R0 R0 R0 R0 R0 R0 R0 R0
SR SR SR SR SR SR SR SR SR
SS_STATUS
SS_ADRF
SS_ADRR
SS_ADR0
SS_ADR1
SS_SP_SYS
SS_SP_APP
SS_RAR
SS_RSR
4.4.2 Status Register Configuration
The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 4-4
and Figure 4-5. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T,
and L bits, while the upper halfword contains information about the mode and state the proces-
sor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 4-4. The Status Register High Halfword
Bit 31 Bit 16
LC - M 2 M 1 M 0 EM I3M IF2EM I1M I0M G M B it nam e
SS 1- - - DM D
000 0 0 0 0 0 0 1 1 0 0 0 0 1 Initial value
Global Interrupt Mask
Interrupt Level 0 Mask
Interrupt Level 1 Mask
Interrupt Level 2 Mask
Interrupt Level 3 Mask
Exception Mask
Mode Bit 0
Mode Bit 1
Mode Bit 2
Reserved
Debug State
Debug State Mask
Reserved
Secure State
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Figure 4-5. The Status Register Low Halfword
Bit 15 Bit 0
- T - - - - - - - - L Q V N Z C Bit name
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value
Carry
Zero
Sign
Overflow
Saturation
Lock
Reserved
Scratch
Reserved
4.4.3 Processor States
4.4.3.1 Normal RISC State
The AVR32 processor supports several different execution contexts as shown in Table 4-2.
Table 4-2. Overview of Execution Modes, their Priorities and Privilege Levels.
Priority Mode Security Description
1 Non Maskable Interrupt Privileged Non Maskable high priority interrupt mode
2 Exception Privileged Execute exceptions
3 Interrupt 3 Privileged General purpose interrupt mode
4 Interrupt 2 Privileged General purpose interrupt mode
5 Interrupt 1 Privileged General purpose interrupt mode
6 Interrupt 0 Privileged General purpose interrupt mode
N/A Supervisor Privileged Runs supervisor calls
N/A Application Unprivileged Normal program execution mode
4.4.3.2 Mode changes can be made under software control, or can be caused by external interrupts or
exception processing. A mode can be interrupted by a higher priority mode, but never by one
with lower priority. Nested exceptions can be supported with a minimal software overhead.
When running an operating system on the AVR32, user processes will typically execute in the
application mode. The programs executed in this mode are restricted from executing certain
instructions. Furthermore, most system registers together with the upper halfword of the status
register cannot be accessed. Protected memory areas are also not available. All other operating
modes are privileged and are collectively called System Modes. They have full access to all priv-
ileged and unprivileged resources. After a reset, the processor will be in supervisor mode.
Debug State
The AVR32 can be set in a debug state, which allows implementation of software monitor rou-
tines that can read out and alter system information for use during application development. This
implies that all system and application registers, including the status registers and program
counters, are accessible in debug state. The privileged instructions are also available.
All interrupt levels are by default disabled when debug state is entered, but they can individually
be switched on by the monitor routine by clearing the respective mask bit in the status register.
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Debug state can be entered as described in the AVR32UC Technical Reference Manual.
Debug state is exited by the retd instruction.
4.4.3.3 Secure State
The AVR32 can be set in a secure state, that allows a part of the code to execute in a state with
higher security levels. The rest of the code can not access resources reserved for this secure
code. Secure State is used to implement FlashVault technology. Refer to the AVR32UC Techni-
cal Reference Manual for details.
4.4.4 System Registers
The system registers are placed outside of the virtual memory space, and are only accessible
using the privileged mfsr and mtsr instructions. The table below lists the system registers speci-
fied in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is
responsible for maintaining correct sequencing of any instructions following a mtsr instruction.
For detail on the system registers, refer to the AVR32UC Technical Reference Manual.
Table 4-3. System Registers
Reg #
0 Address Name Function
1 Status Register
2 0 SR Exception Vector Base Address
3 Application Call Base Address
4 4 EVBA CPU Control Register
5 Exception Cause Register
6 8 ACBA Unused in AVR32UC
7 Unused in AVR32UC
8 12 CPUCR Unused in AVR32UC
9 Unused in AVR32UC
10 16 ECR Unused in AVR32UC
11 Unused in AVR32UC
12 20 RSR_SUP Unused in AVR32UC
13 Return Status Register for Debug mode
14 24 RSR_INT0 Unused in AVR32UC
15 Unused in AVR32UC
16 28 RSR_INT1 Unused in AVR32UC
17 Unused in AVR32UC
18 32 RSR_INT2 Unused in AVR32UC
19 Unused in AVR32UC
20 36 RSR_INT3 Unused in AVR32UC
21 Return Address Register for Debug mode
22 40 RSR_EX Unused in AVR32UC
23 Unused in AVR32UC
44 RSR_NMI Unused in AVR32UC
48 RSR_DBG
52 RAR_SUP
56 RAR_INT0
60 RAR_INT1
64 RAR_INT2
68 RAR_INT3
72 RAR_EX
76 RAR_NMI
80 RAR_DBG
84 JECR
88 JOSP
92 JAVA_LV0
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Table 4-3. System Registers (Continued)
Reg #
24 Address Name Function
25
26 96 JAVA_LV1 Unused in AVR32UC
27
28 100 JAVA_LV2 Unused in AVR32UC
29
30 104 JAVA_LV3 Unused in AVR32UC
31
32 108 JAVA_LV4 Unused in AVR32UC
33-63
64 112 JAVA_LV5 Unused in AVR32UC
65
66 116 JAVA_LV6 Unused in AVR32UC
67
68 120 JAVA_LV7 Unused in AVR32UC
69
70 124 JTBA Unused in AVR32UC
71
72 128 JBCR Unused in AVR32UC
73
74 132-252 Reserved Reserved for future use
75
76 256 CONFIG0 Configuration register 0
77
78 260 CONFIG1 Configuration register 1
79
80 264 COUNT Cycle Counter register
81
82 268 COMPARE Compare register
83
84 272 TLBEHI Unused in AVR32UC
85
86 276 TLBELO Unused in AVR32UC
87
88 280 PTBR Unused in AVR32UC
89
284 TLBEAR Unused in AVR32UC
288 MMUCR Unused in AVR32UC
292 TLBARLO Unused in AVR32UC
296 TLBARHI Unused in AVR32UC
300 PCCNT Unused in AVR32UC
304 PCNT0 Unused in AVR32UC
308 PCNT1 Unused in AVR32UC
312 PCCR Unused in AVR32UC
316 BEAR Bus Error Address Register
320 MPUAR0 MPU Address Register region 0
324 MPUAR1 MPU Address Register region 1
328 MPUAR2 MPU Address Register region 2
332 MPUAR3 MPU Address Register region 3
336 MPUAR4 MPU Address Register region 4
340 MPUAR5 MPU Address Register region 5
344 MPUAR6 MPU Address Register region 6
348 MPUAR7 MPU Address Register region 7
352 MPUPSR0 MPU Privilege Select Register region 0
356 MPUPSR1 MPU Privilege Select Register region 1
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Table 4-3. System Registers (Continued)
Reg #
90 Address Name Function
91
92 360 MPUPSR2 MPU Privilege Select Register region 2
93
94 364 MPUPSR3 MPU Privilege Select Register region 3
95
96 368 MPUPSR4 MPU Privilege Select Register region 4
97
98 372 MPUPSR5 MPU Privilege Select Register region 5
99
100 376 MPUPSR6 MPU Privilege Select Register region 6
101
102 380 MPUPSR7 MPU Privilege Select Register region 7
103
104 384 MPUCRA Unused in this version of AVR32UC
105
106 388 MPUCRB Unused in this version of AVR32UC
107
108 392 MPUBRA Unused in this version of AVR32UC
109
110 396 MPUBRB Unused in this version of AVR32UC
111
112-191 400 MPUAPRA MPU Access Permission Register A
192-255
404 MPUAPRB MPU Access Permission Register B
408 MPUCR MPU Control Register
412 SS_STATUS Secure State Status Register
416 SS_ADRF Secure State Address Flash Register
420 SS_ADRR Secure State Address RAM Register
424 SS_ADR0 Secure State Address 0 Register
428 SS_ADR1 Secure State Address 1 Register
432 SS_SP_SYS Secure State Stack Pointer System Register
436 SS_SP_APP Secure State Stack Pointer Application Register
440 SS_RAR Secure State Return Address Register
444 SS_RSR Secure State Return Status Register
448-764 Reserved Reserved for future use
768-1020 IMPL IMPLEMENTATION DEFINED
4.5 Exceptions and Interrupts
In the AVR32 architecture, events are used as a common term for exceptions and interrupts.
AVR32UC incorporates a powerful event handling scheme. The different event sources, like Ille-
gal Op-code and interrupt requests, have different priority levels, ensuring a well-defined
behavior when multiple events are received simultaneously. Additionally, pending events of a
higher priority class may preempt handling of ongoing events of a lower priority class.
When an event occurs, the execution of the instruction stream is halted, and execution is passed
to an event handler at an address specified in Table 4-4 on page 31. Most of the handlers are
placed sequentially in the code space starting at the address specified by EVBA, with four bytes
between each handler. This gives ample space for a jump instruction to be placed there, jump-
ing to the event routine itself. A few critical handlers have larger spacing between them, allowing
the entire event routine to be placed directly at the address specified by the EVBA-relative offset
generated by hardware. All interrupt sources have autovectored interrupt service routine (ISR)
addresses. This allows the interrupt controller to directly specify the ISR address as an address
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4.5.1 relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384
4.5.2 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset),
not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up
appropriately. The same mechanisms are used to service all different types of events, including
interrupt requests, yielding a uniform event handling scheme.
An interrupt controller does the priority handling of the interrupts and provides the autovector off-
set to the CPU.
System Stack Issues
Event handling in AVR32UC uses the system stack pointed to by the system stack pointer,
SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event
code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section,
since the timing of accesses to this memory section is both fast and deterministic.
The user must also make sure that the system stack is large enough so that any event is able to
push the required registers to stack. If the system stack is full, and an event occurs, the system
will enter an UNDEFINED state.
Exceptions and Interrupt Requests
When an event other than scall or debug request is received by the core, the following actions
are performed atomically:
1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and
GM bits in the Status Register are used to mask different events. Not all events can be
masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and
Bus Error) can not be masked. When an event is accepted, hardware automatically
sets the mask bits corresponding to all sources with equal or lower priority. This inhibits
acceptance of other events of the same or lower priority, except for the critical events
listed above. Software may choose to clear some or all of these bits after saving the
necessary state if other priority schemes are desired. It is the event source's respons-
ability to ensure that their events are left pending until accepted by the CPU.
2. When a request is accepted, the Status Register and Program Counter of the current
context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, reg-
isters R8-R12 and LR are also automatically stored to stack. Storing the Status
Register ensures that the core is returned to the previous execution mode when the
current event handling is completed. When exceptions occur, both the EM and GM bits
are set, and the application may manually enable nested exceptions if desired by clear-
ing the appropriate bit. Each exception handler has a dedicated handler address, and
this address uniquely identifies the exception source.
3. The Mode bits are set to reflect the priority of the accepted event, and the correct regis-
ter file bank is selected. The address of the event handler, as shown in Table 4-4 on
page 31, is loaded into the Program Counter.
The execution of the event handler routine then continues from the effective address calculated.
The rete instruction signals the end of the event. When encountered, the Return Status Register
and Return Address Register are popped from the system stack and restored to the Status Reg-
ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3,
registers R8-R12 and LR are also popped from the system stack. The restored Status Register
contains information allowing the core to resume operation in the previous execution mode. This
concludes the event handling.
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4.5.3 Supervisor Calls
4.5.4 The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is
4.5.5 designed so that privileged routines can be called from any context. This facilitates sharing of
code between different execution modes. The scall mechanism is designed so that a minimal
execution cycle overhead is experienced when performing supervisor routine calls from time-
critical event handlers.
The scall instruction behaves differently depending on which mode it is called from. The behav-
iour is detailed in the instruction set reference. In order to allow the scall routine to return to the
correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC
CPU, scall and rets uses the system stack to store the return address and the status register.
Debug Requests
The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by
the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the
status register. Upon entry into Debug mode, hardware sets the SR.D bit and jumps to the
Debug Exception handler. By default, Debug mode executes in the exception context, but with
dedicated Return Address Register and Return Status Register. These dedicated registers
remove the need for storing this data to the system stack, thereby improving debuggability. The
Mode bits in the Status Register can freely be manipulated in Debug mode, to observe registers
in all contexts, while retaining full privileges.
Debug mode is exited by executing the retd instruction. This returns to the previous context.
Entry Points for Events
Several different event handler entry points exist. In AVR32UC, the reset address is
0x80000000. This places the reset address in the boot flash memory area.
TLB miss exceptions and scall have a dedicated space relative to EVBA where their event han-
dler can be placed. This speeds up execution by removing the need for a jump instruction placed
at the program address jumped to by the event hardware. All other exceptions have a dedicated
event routine entry point located relative to EVBA. The handler routine address identifies the
exception source directly.
AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation.
ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of
the entries in the MPU. TLB multiple hit exception indicates that an access address did map to
multiple TLB entries, signalling an error.
All interrupt requests have entry points located at an offset relative to EVBA. This autovector off-
set is specified by an interrupt controller. The programmer must make sure that none of the
autovector offsets interfere with the placement of other code. The autovector offset has 14
address bits, giving an offset of maximum 16384 bytes.
Special considerations should be made when loading EVBA with a pointer. Due to security con-
siderations, the event handlers should be located in non-writeable flash memory, or optionally in
a privileged memory protection region if an MPU is present.
If several events occur on the same instruction, they are handled in a prioritized way. The priority
ordering is presented in Table 4-4 on page 31. If events occur on several instructions at different
locations in the pipeline, the events on the oldest instruction are always handled before any
events on any younger instruction, even if the younger instruction has events of higher priority
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than the oldest instruction. An instruction B is younger than an instruction A if it was sent down
the pipeline later than A.
The addresses and priority of simultaneous events are shown in Table 4-4 on page 31. Some of
the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating-
point unit.
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Table 4-4. Priority and Handler Addresses for Events
Priority Handler Address Name Event source Stored Return Address
External input Undefined
1 0x80000000 Reset OCD system First non-completed instruction
Internal PC of offending instruction
2 Provided by OCD system OCD Stop CPU MPU PC of offending instruction
Data bus First non-completed instruction
3 EVBA+0x00 Unrecoverable exception Data bus First non-completed instruction
External input First non-completed instruction
4 EVBA+0x04 TLB multiple hit External input First non-completed instruction
External input First non-completed instruction
5 EVBA+0x08 Bus error data fetch External input First non-completed instruction
External input First non-completed instruction
6 EVBA+0x0C Bus error instruction fetch CPU PC of offending instruction
MPU PC of offending instruction
7 EVBA+0x10 NMI MPU PC of offending instruction
OCD system First non-completed instruction
8 Autovectored Interrupt 3 request Instruction PC of offending instruction
Instruction PC of offending instruction
9 Autovectored Interrupt 2 request Instruction PC of offending instruction
UNUSED
10 Autovectored Interrupt 1 request Instruction PC of offending instruction
Instruction PC(Supervisor Call) +2
11 Autovectored Interrupt 0 request CPU PC of offending instruction
CPU PC of offending instruction
12 EVBA+0x14 Instruction Address MPU PC of offending instruction
MPU PC of offending instruction
13 EVBA+0x50 ITLB Miss MPU PC of offending instruction
MPU PC of offending instruction
14 EVBA+0x18 ITLB Protection UNUSED
15 EVBA+0x1C Breakpoint
16 EVBA+0x20 Illegal Opcode
17 EVBA+0x24 Unimplemented instruction
18 EVBA+0x28 Privilege violation
19 EVBA+0x2C Floating-point
20 EVBA+0x30 Coprocessor absent
21 EVBA+0x100 Supervisor call
22 EVBA+0x34 Data Address (Read)
23 EVBA+0x38 Data Address (Write)
24 EVBA+0x60 DTLB Miss (Read)
25 EVBA+0x70 DTLB Miss (Write)
26 EVBA+0x3C DTLB Protection (Read)
27 EVBA+0x40 DTLB Protection (Write)
28 EVBA+0x44 DTLB Modified
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5. Memories
5.1 Embedded Memories
Internal high-speed flash
256Kbytes (AT32UC3L0256)
128Kbytes (AT32UC3L0128)
0 wait state access at up to 25MHz in worst case conditions
1 wait state access at up to 50MHz in worst case conditions
Pipelined flash architecture, allowing burst reads from sequential flash locations, hiding
penalty of 1 wait state access
Pipelined flash architecture typically reduces the cycle penalty of 1 wait state operation
to only 8% compared to 0 wait state operation
100 000 write cycles, 15-year data retention capability
Sector lock capabilities, bootloader protection, security bit
32 fuses, erased during chip erase
User page for data to be preserved during chip erase
Internal high-speed SRAM, single-cycle access at full speed
32Kbytes
5.2 Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even during boot. Note that AVR32 UC CPU uses unseg-
mented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address
space is mapped as follows:
Table 5-1. AT32UC3L0128/256 Physical Memory Map
Device Start Address Size
AT32UC3L0256 AT32UC3L0128
Embedded SRAM 0x00000000 32 Kbytes 32 Kbytes
128 Kbytes
Embedded Flash 0x80000000 256 Kbytes 256 bytes
64 Kbytes
SAU Channels 0x90000000 256 bytes 64 Kbytes
HSB-PB Bridge B 0xFFFE0000 64 Kbytes
HSB-PB Bridge A 0xFFFF0000 64 Kbytes
Table 5-2. Flash Memory Parameters
Part Number Flash Size (FLASH_PW) Number of pages Page size
AT32UC3L0256 256 Kbytes (FLASH_P) (FLASH_W)
AT32UC3L0128 128 Kbytes
512 512 bytes
256 512 bytes
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5.3 Peripheral Address Map AT32UC3L0128/256
Table 5-3. Peripheral Address Mapping Peripheral Name
Flash Controller - FLASHCDW
Address HSB Matrix - HMATRIX
Secure Access Unit - SAU
0xFFFE0000 Peripheral DMA Controller - PDCA
Interrupt controller - INTC
FLASHCDW Power Manager - PM
System Control Interface - SCIF
0xFFFE0400 Asynchronous Timer - AST
Watchdog Timer - WDT
HMATRIX External Interrupt Controller - EIC
Frequency Meter - FREQM
0xFFFE0800 General-Purpose Input/Output Controller - GPIO
Universal Synchronous Asynchronous Receiver
SAU Transmitter - USART0
Universal Synchronous Asynchronous Receiver
0xFFFF0000 Transmitter - USART1
Universal Synchronous Asynchronous Receiver
PDCA Transmitter - USART2
Universal Synchronous Asynchronous Receiver
0xFFFF1000 Transmitter - USART3
Serial Peripheral Interface - SPI
INTC Two-wire Master Interface - TWIM0
0xFFFF1400
PM
0xFFFF1800
SCIF
0xFFFF1C00
AST
0xFFFF2000 WDT
0xFFFF2400 EIC
0xFFFF2800 FREQM
0xFFFF2C00 GPIO
0xFFFF3000 USART0
0xFFFF3400 USART1
0xFFFF3800 USART2
0xFFFF3C00 USART3
0xFFFF4000 SPI
0xFFFF4400 TWIM0
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Table 5-3. Peripheral Address Mapping
0xFFFF4800
TWIM1 Two-wire Master Interface - TWIM1
Two-wire Slave Interface - TWIS0
0xFFFF4C00 Two-wire Slave Interface - TWIS1
Pulse Width Modulation Controller - PWMA
TWIS0 Timer/Counter - TC0
Timer/Counter - TC1
0xFFFF5000 ADC Interface - ADCIFB
Analog Comparator Interface - ACIFB
TWIS1 Capacitive Touch Module - CAT
Glue Logic Controller - GLOC
0xFFFF5400 aWire - AW
PWMA
0xFFFF5800
TC0
0xFFFF5C00
TC1
0xFFFF6000
ADCIFB
0xFFFF6400
ACIFB
0xFFFF6800
CAT
0xFFFF6C00
GLOC
0xFFFF7000
AW
5.4 CPU Local Bus Mapping
Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to
being mapped on the Peripheral Bus. These registers can therefore be reached both by
accesses on the Peripheral Bus, and by accesses on the local bus.
Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since
the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at
CPU speed, one write or read operation can be performed per clock cycle to the local bus-
mapped GPIO registers.
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The following GPIO registers are mapped on the local bus:
Table 5-4. Local Bus Mapped GPIO Registers
Port Register Mode Local Bus Access
WRITE Address Write-only
0 Output Driver Enable Register (ODER) SET 0x40000040 Write-only
CLEAR 0x40000044 Write-only
Output Value Register (OVR) TOGGLE 0x40000048 Write-only
WRITE 0x4000004C Write-only
Pin Value Register (PVR) SET 0x40000050 Write-only
CLEAR 0x40000054 Write-only
1 Output Driver Enable Register (ODER) TOGGLE 0x40000058 Write-only
- 0x4000005C Read-only
Output Value Register (OVR) WRITE 0x40000060 Write-only
SET 0x40000140 Write-only
Pin Value Register (PVR) CLEAR 0x40000144 Write-only
TOGGLE 0x40000148 Write-only
WRITE 0x4000014C Write-only
SET 0x40000150 Write-only
CLEAR 0x40000154 Write-only
TOGGLE 0x40000158 Write-only
- 0x4000015C Read-only
0x40000160
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6. Supply and Startup Considerations
6.1 Supply Considerations
6.1.1 Power Supplies
The AT32UC3L0128/256 has several types of power supply pins:
VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal.
VDDIN: Powers I/O lines and the internal regulator. Voltage is 1.8 to 3.3V nominal.
VDDANA: Powers the ADC. Voltage is 1.8V nominal.
VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal.
The ground pins GND are common to VDDCORE, VDDIO, and VDDIN. The ground pin for
VDDANA is GNDANA.
When VDDCORE is not connected to VDDIN, the VDDIN voltage must be higher than 1.98V.
Refer to Section 7. on page 41 for power consumption on the various supply pins.
For decoupling recommendations for the different power supplies, please refer to the schematic
checklist.
Refer to Section 3.2 on page 8 for power supply connections for I/O pins.
6.1.2 Voltage Regulator
The AT32UC3L0128/256 embeds a voltage regulator that converts from 3.3V nominal to 1.8V
with a load of up to 60mA. The regulator supplies the output voltage on VDDCORE. The regula-
tor may only be used to drive internal circuitry in the device. VDDCORE should be externally
connected to the 1.8V domains. See Section 6.1.3 for regulator connection figures.
Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid
oscillations. The best way to achieve this is to use two capacitors in parallel between VDDCORE
and GND as close to the device as possible. Please refer to Section 7.8.1 on page 55 for decou-
pling capacitors values and regulator characteristics.
Figure 6-1. Supply Decoupling
3.3V VDDIN
1.8V
C IN3 CIN2 CIN1 1.8V
Regulator
VDDCORE
COUT2 COUT1
The voltage regulator can be turned off in the shutdown mode to power down the core logic and
keep a small part of the system powered in order to reduce power consumption. To enter this
mode the 3.3V supply mode, with 1.8V regulated I/O lines power supply configuration must be
used.
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6.1.3 Regulator Connection
The AT32UC3L0128/256 supports three power supply configurations:
3.3V single supply mode
Shutdown mode is not available
1.8V single supply mode
Shutdown mode is not available
3.3V supply mode, with 1.8V regulated I/O lines
Shutdown mode is available
6.1.3.1 3.3V Single Supply Mode
In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin)
and its output feeds VDDCORE. Figure 6-2 shows the power schematics to be used for 3.3V
single supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO).
Figure 6-2. 3.3V Single Supply Mode
+ VDDIN VDDIO GND
1.98-3.6V
-
I/O Pins I/O Pins
OSC32K_2, OSC32K,
AST, Wake, RC32K,
POR33,
Regulator SM33
control
VDDCORE Linear CPU,
VDDANA regulator Peripherals,
Memories,
ADC SCIF, BOD,
RCSYS,
DFLL, PLL
GNDANA
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6.1.3.2 1.8 V Single Supply Mode
In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are
powered by a single 1.8 V supply as shown in Figure 6-3. All I/O lines will be powered by the
same power (VDDIN = VDDIO = VDDCORE).
Figure 6-3. 1.8V Single Supply Mode.
+ VDDIN VDDIO GND
1.62-1.98V
-
I/O Pins I/O Pins
OSC32K_2, OSC32K,
AST, Wake, RC32K,
Regulator POR33,
SM33
control
VDDCORE ADC CPU,
VDDANA Peripherals,
Memories,
SCIF, BOD,
RCSYS,
DFLL, PLL
GNDANA
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6.1.3.3 3.3V Supply Mode with 1.8V Regulated I/O Lines
In this mode, the internal regulator is connected to the 3.3V source and its output is connected
to both VDDCORE and VDDIO as shown in Figure 6-4. This configuration is required in order to
use Shutdown mode.
Figure 6-4. 3.3V Supply Mode with 1.8V Regulated I/O Lines
+ VDDIN VDDIO GND
1.98-3.6V
-
I/O Pins I/O Pins
OSC32K_2, OSC32K,
AST, Wake, RC32K,
POR33,
Regulator SM33
control
VDDCORE Linear CPU,
VDDANA regulator Peripherals,
Memories,
ADC SCIF, BOD,
RCSYS,
DFLL, PLL
GNDANA
In this mode, some I/O lines are powered by VDDIN while other I/O lines are powered by VDDIO.
Refer to Section 3.2.1 on page 8 for description of power supply for each I/O line.
Refer to the Power Manager chapter for a description of what parts of the system are powered in
Shutdown mode.
Important note: As the regulator has a maximum output current of 60 mA, this mode can only be
used in applications where the maximum I/O current is known and compatible with the core and
peripheral power consumption. Typically, great care must be used to ensure that only a few I/O
lines are toggling at the same time and drive very small loads.
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6.1.4 Power-up Sequence
6.1.4.1 Maximum Rise Rate
To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values
described in Table 7-3 on page 42.
Recommended order for power supplies is also described in this chapter.
6.1.4.2 Minimum Rise Rate
The integrated Power-on Reset (POR33) circuitry monitoring the VDDIN powering supply
requires a minimum rise rate for the VDDIN power supply.
See Table 7-3 on page 42 for the minimum rise rate value.
If the application can not ensure that the minimum rise rate condition for the VDDIN power sup-
ply is met, one of the following configurations can be used:
A logic "0" value is applied during power-up on pin PA11 (WAKE_N) until VDDIN rises above
1.2 V.
A logic "0" value is applied during power-up on pin RESET_N until VDDIN rises above 1.2V.
6.2 Startup Considerations
This chapter summarizes the boot sequence of the AT32UC3L0128/256. The behavior after
power-up is controlled by the Power Manager. For specific details, refer to the Power Manager
chapter.
6.2.1 Starting of Clocks
After power-up, the device will be held in a reset state by the Power-on Reset (POR18 and
POR33) circuitry for a short time to allow the power to stabilize throughout the device. After
reset, the device will use the System RC Oscillator (RCSYS) as clock source. Please refer to
Table 7-17 on page 54 for the frequency for this oscillator.
On system start-up, all high-speed clocks are disabled. All clocks to all modules are running. No
clocks have a divided frequency; all parts of the system receive a clock with the same frequency
as the System RC Oscillator.
When powering up the device, there may be a delay before the voltage has stabilized, depend-
ing on the rise time of the supply used. The CPU can start executing code as soon as the supply
is above the POR18 and POR33 thresholds, and before the supply is stable. Before switching to
a high-speed clock source, the user should use the BOD to make sure the VDDCORE is above
the minimum level (1.62V).
6.2.2 Fetching of Initial Instructions
After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset
address, which is 0x80000000. This address points to the first address in the internal Flash.
The code read from the internal flash is free to configure the clock system and clock sources.
Please refer to the PM and SCIF chapters for more details.
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7. Electrical Characteristics
7.1 Absolute Maximum Ratings*
Table 7-1. Absolute Maximum Ratings *NOTICE: Stresses beyond those listed under
"Absolute Maximum Ratings" may cause
Operating temperature..................................... -40C to +85C permanent damage to the device. This is
Storage temperature...................................... -60C to +150C a stress rating only and functional opera-
Voltage on input pins (except for 5V pins) with respect to ground tion of the device at these or other condi-
.................................................................-0.3V to VVDD(2)+0.3V tions beyond those indicated in the
Voltage on 5V tolerant(1) pins with respect to ground ............... operational sections of this specification is
.............................................................................-0.3V to 5.5V not implied. Exposure to absolute maxi-
mum rating conditions for extended peri-
Total DC output current on all I/O pins - VDDIO ........... 120mA ods may affect device reliability.
Total DC output current on all I/O pins - VDDIN ............. 36mA
Maximum operating voltage VDDCORE......................... 1.98V
Maximum operating voltage VDDIO, VDDIN .................... 3.6V
Notes: 1. 5V tolerant pins, see Section 3.2 "Peripheral Multiplexing on I/O Lines" on page 8
2. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3.2 on page 8 for details.
7.2 Supply Characteristics
The following characteristics are applicable to the operating temperature range: TA=-40C to
85C, unless otherwise specified and are valid for a junction temperature up to TJ=100C.
Please refer to Section 6. "Supply and Startup Considerations" on page 36
Table 7-2. Supply Characteristics
Voltage
Symbol Parameter Min Max Unit
VVDDIO DC supply peripheral I/Os 1.62 3.6 V
DC supply peripheral I/Os, 1.8V 1.62 1.98 V
single supply mode
VVDDIN DC supply peripheral I/Os and
internal regulator, 3.3V supply 1.98 3.6 V
mode
VVDDCORE DC supply core 1.62 1.98 V
VVDDANA Analog supply voltage
1.62 1.98 V
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Table 7-3. Supply Rise Rates and Order(1)
Rise Rate
Symbol Parameter Min Max Unit Comment
VVDDIO DC supply peripheral I/Os 0 2.5
2.5 V/s
VVDDIN DC supply peripheral I/Os 0.002
and internal regulator 2.5 V/s Slower rise time requires
2.5 external power-on reset
circuit.
VVDDCORE DC supply core 0 V/s Rise before or at the same
time as VDDIO
VVDDANA Analog supply voltage 0 V/s Rise together with
VDDCORE
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers
manufactured in the same process technology. These values are not covered by test limits in
production.
7.3 Maximum Clock Frequencies
These parameters are given in the following conditions:
VVDDCORE = 1.62V to 1.98V
Temperature = -40C to 85C
Table 7-4. Clock Frequencies
Symbol Parameter Description Min Max Units
50
fCPU CPU clock frequency DFLLIF main reference, GCLK0 pin 50
fPBA PBA clock frequency 50
fPBB PBB clock frequency DFLLIF dithering and SSG reference, 50
fGCLK0 GCLK0 clock frequency GCLK1 pin
50
fGCLK1 GCLK1 clock frequency
20
fGCLK2 GCLK2 clock frequency AST, GCLK2 pin 140 MHz
fGCLK3 GCLK3 clock frequency PWMA, GCLK3 pin 50
fGCLK4 GCLK4 clock frequency CAT, ACIFB, GCLK4 pin 80
fGCLK5 GCLK5 clock frequency GLOC 50
fGCLK6 GCLK6 clock frequency 50
fGCLK7 GCLK7 clock frequency PLL source clock 50
fGCLK8 GCLK8 clock frequency FREQM, GCLK0-8 150
fGCLK9 GCLK9 clock frequency
7.4 Power Consumption
The values in Table 7-5 are measured values of power consumption under the following condi-
tions, except where noted:
Operating conditions, internal core supply (Figure 7-1) - this is the default configuration
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VVDDIN = 3.0V
VVDDCORE = 1.62V, supplied by the internal regulator
Corresponds to the 3.3V supply mode with 1.8V regulated I/O lines, please refer to
the Supply and Startup Considerations section for more details
Equivalent to the 3.3V single supply mode
Consumption in 1.8V single supply mode can be estimated by subtracting the regula-
tor static current
Operating conditions, external core supply (Figure 7-2) - used only when noted
VVDDIN = VVDDCORE = 1.8V
Corresponds to the 1.8V single supply mode, please refer to the Supply and Startup
Considerations section for more details
TA = 25C
Oscillators
OSC0 (crystal oscillator) stopped
OSC32K (32KHz crystal oscillator) running with external 32KHz crystal
DFLL running at 50MHz with OSC32K as reference
Clocks
DFLL used as main clock source
CPU, HSB, and PBB clocks undivided
PBA clock divided by 4
The following peripheral clocks running
PM, SCIF, AST, FLASHCDW, PBA bridge
All other peripheral clocks stopped
I/Os are inactive with internal pull-up
Flash enabled in high speed mode
POR18 enabled
POR33 disabled
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Table 7-5. Power Consumption for Different Operating Modes
Mode
Active(1) Conditions Measured on Consumption Typ Unit
Idle(1) 300 A/MHz
Frozen(1) CPU running a recursive Fibonacci algorithm 174
Standby(1) 96 A
Stop CPU running a division algorithm 57 nA
DeepStop 46
-OSC32K and AST stopped Amp0 38
Static -Internal core supply 25
14
Shutdown -OSC32K running
-AST running at 1KHz 7.3
-External core supply (Figure 7-2)
6.7
-OSC32K and AST stopped
-External core supply (Figure 7-2) 800
220
-OSC32K running
-AST running at 1KHz
AST and OSC32K stopped
Note: 1. These numbers are valid for the measured condition only and must not be extrapolated to other frequencies.
Figure 7-1. Measurement Schematic, Internal Core Supply
Amp0 VDDIN
VDDIO
VDDCORE
VDDANA
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Figure 7-2. Measurement Schematic, External Core Supply
Amp0 VDDIN
VDDIO
VDDCORE
VDDANA
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7.5 I/O Pin Characteristics
Table 7-6. Normal I/O Pin Characteristics(1)
Symbol Parameter Condition Min Typ Max Units
145 kOhm
RPULLUP Pull-up resistance 75 100 0.3*VVDD
VIL Input low-level voltage 0.3*VVDD V
VIH VVDD = 3.0V -0.3 VVDD + 0.3 V
VOL Input high-level voltage VVDD = 1.62V VVDD + 0.3 V
VOH VVDD = 3.6V -0.3 0.4 V
fMAX Output low-level voltage VVDD = 1.98V 0.4 MHz
tRISE VVDD = 3.0V, IOL = 3mA 0.7*VVDD
tFALL Output high-level voltage VVDD = 1.62V, IOL = 2mA 0.7*VVDD 45 ns
ILEAK VVDD = 3.0V, IOH = 3mA 23 A
CIN Output frequency(2) VVDD = 1.62V, IOH = 2mA VVDD - 0.4 4.7
VVDD = 3.0V, load = 10pF VVDD - 0.4 11.5 pF
Rise time(2) VVDD = 3.0V, load = 30pF 4.8
VVDD = 3.0V, load = 10pF 12
Fall time(2) VVDD = 3.0V, load = 30pF 1
Input leakage current VVDD = 3.0V, load = 10pF
Input capacitance, all VVDD = 3.0V, load = 30pF 1.4
normal I/O pins except Pull-up resistors disabled 1.1
PA05, PA07, PA17, PA20, TQFP48 package 1.1
PA21, PB04, PB05 QFN48 package 2.7
TLLGA48 package 2.4
2.4
TQFP48 package 3.8
3.5
CIN Input capacitance, PA20 QFN48 package 3.5
TLLGA48 package
TQFP48 package
Input capacitance, PA05,
CIN PA07, PA17, PA21, PB04, QFN48 package
PB05 TLLGA48 package
Notes: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3.2.1 on page 8 for
details.
2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Table 7-7. High-drive I/O Pin Characteristics(1)
Symbol Parameter Condition Min Typ Max Units
110 kOhm
PA06 30 50 145
45
RPULLUP Pull-up resistance PA02, PB01, RESET 75 100
PA08, PA09
10 20
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Table 7-7. High-drive I/O Pin Characteristics(1)
Symbol Parameter Condition Min Typ Max Units
VIL Input low-level voltage VVDD = 3.0V -0.3 0.3*VVDD V
VIH VVDD = 1.62V -0.3 0.3*VVDD V
VOL Input high-level voltage VVDD = 3.6V 0.7*VVDD VVDD + 0.3 V
VOH VVDD = 1.98V 0.7*VVDD VVDD + 0.3 V
fMAX Output low-level voltage VVDD = 3.0V, IOL = 6mA MHz
tRISE VVDD = 1.62V, IOL = 4mA 0.4 ns
tFALL Output high-level voltage VVDD = 3.0V, IOH = 6mA MHz
fMAX VVDD = 1.62V, IOH = 4mA 0.4 ns
tRISE Output frequency, all High-drive I/O VVDD = 3.0V, load = 10pF A
tFALL pins, except PA08 and PA09(2) VVDD = 3.0V, load = 30pF VVDD-0.4
ILEAK Rise time, all High-drive I/O pins, VVDD = 3.0V, load = 10pF VVDD-0.4 pF
CIN except PA08 and PA09(2) VVDD = 3.0V, load = 30pF
Fall time, all High-drive I/O pins, VVDD = 3.0V, load = 10pF 45
except PA08 and PA09(2) VVDD = 3.0V, load = 30pF
Output frequency, PA08 and VVDD = 3.0V, load = 10pF 23
PA09(2) VVDD = 3.0V, load = 30pF
VVDD = 3.0V, load = 10pF 4.7
Rise time, PA08 and PA09(2) VVDD = 3.0V, load = 30pF
VVDD = 3.0V, load = 10pF 11.5
Fall time, PA08 and PA09(2) VVDD = 3.0V, load = 30pF
Input leakage current Pull-up resistors disabled 4.8
TQFP48 package
Input capacitance, all High-drive I/O QFN48 package 12
pins, except PA08 and PA09 TLLGA48 package
TQFP48 package 54
40
2.8
4.9
2.4
4.6
1
2.2
2.0
2.0
7.0
CIN Input capacitance, PA08 and PA09 QFN48 package 6.7
Notes:
TLLGA48 package 6.7
1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3.2.1 on page 8 for
details.
2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Table 7-8. High-drive I/O, 5V Tolerant, Pin Characteristics(1)
Symbol Parameter Condition Min Typ Max Units
RPULLUP Pull-up resistance 30 50 110 kOhm
VIL Input low-level voltage
VVDD = 3.0V -0.3 0.3*VVDD
VVDD = 1.62V
V
-0.3 0.3*VVDD
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Table 7-8. High-drive I/O, 5V Tolerant, Pin Characteristics(1)
Symbol Parameter Condition Min Typ Max Units
VIH Input high-level voltage VVDD = 3.6V 0.7*VVDD 5.5
VOL Output low-level voltage VVDD = 1.98V 0.7*VVDD V
VOH Output high-level voltage VVDD = 3.0V, IOL = 6mA VVDD-0.4
fMAX Output frequency(2) VVDD = 1.62V, IOL = 4mA VVDD-0.4 5.5
tRISE Rise time(2) VVDD = 3.0V, IOH = 6mA
tFALL Fall time(2) VVDD = 1.62V, IOH = 4mA 4.5 0.4
ILEAK Input leakage current VVDD = 3.0V, load = 10pF V
VVDD = 3.0V, load = 30pF
VVDD = 3.0V, load = 10pF 0.4
VVDD = 3.0V, load = 30pF
VVDD = 3.0V, load = 10pF V
VVDD = 3.0V, load = 30pF
5.5V, pull-up resistors disabled 87
TQFP48 package MHz
58
2.3
4.3
ns
1.9
3.7
10 A
CIN Input capacitance QFN48 package 4.2 pF
Notes:
TLLGA48 package 4.2
1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3.2.1 on page 8 for
details.
2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Table 7-9. TWI Pin Characteristics(1) Condition Min Typ Max Units
Symbol Parameter
RPULLUP Pull-up resistance VVDD = 3.0V 25 35 60 kOhm
VVDD = 1.62V
VIL Input low-level voltage VVDD = 3.6V -0.3 0.3*VVDD V
VVDD = 1.98V -0.3
VVDD = 3.6V 0.7*VVDD 0.3*VVDD
VVDD = 1.98V 0.7*VVDD
Input high-level voltage IOL = 3mA 0.7*VVDD VVDD + 0.3 V
Pull-up resistors disabled 0.7*VVDD
VIH Input high-level voltage, 5V tolerant VVDD + 0.3
SMBUS compliant pins TQFP48 package
VOL Output low-level voltage QFN48 package 5.5
ILEAK Input leakage current TLLGA48 package V
IIL Input low leakage
IIH Input high leakage 5.5
0.4 V
1
1 A
1
3.8
CIN Input capacitance 3.5 pF
3.5
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Table 7-9. TWI Pin Characteristics(1)
Symbol Parameter Condition Min Typ Max Units
Cbus = 400pF, VVDD > 2.0V 250
tFALL Fall time ns
fMAX Cbus = 400pF, VVDD > 1.62V 470
Note:
Max frequency Cbus = 400pF, VVDD > 2.0V 400 kHz
1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pin. Refer to Section 3.2.1 on page 8 for
details.
7.6 Oscillator Characteristics
7.6.1 Oscillator 0 (OSC0) Characteristics
7.6.1.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied
on XIN.
Table 7-10. Digital Clock Characteristics Conditions Min Typ Max Units
Symbol Parameter 50 MHz
fCPXIN XIN clock frequency 40 0 60 %
tCPXIN XIN clock duty cycle(1) 7.0 cycles
tSTARTUP Startup time 6.7
6.7 pF
CIN XIN input capacitance TQFP48 package
QFN48 package
TLLGA48 package
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
7.6.1.2 Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected
between XIN and XOUT as shown in Figure 7-3. The user must choose a crystal oscillator
where the crystal load capacitance CL is within the range given in the table. The exact value of CL
can be found in the crystal datasheet. The capacitance of the external capacitors (CLEXT) can
then be computed as follows:
CLEXT = 2(CL Ci) CPCB
where CPCB is the capacitance of the PCB and Ci is the internal equivalent load capacitance.
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Table 7-11. Crystal Oscillator Characteristics Conditions Min Typ Max Unit
Symbol Parameter 0.45 10 16 MHz
fOUT Crystal oscillator frequency(3) SCIF.OSCCTRL.GAIN = 2(1) 18 pF
CL Crystal load capacitance(3) Active mode, f = 0.45MHz, 6 2 cycles
Ci Internal equivalent load capacitance SCIF.OSCCTRL.GAIN = 0 30 000(2)
tSTARTUP Startup time Active mode, f = 10MHz, A
SCIF.OSCCTRL.GAIN = 2 30
IOSC Current consumption
220
Notes: 1. Please refer to the SCIF chapter for details.
2. Nominal crystal cycles.
3. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Figure 7-3. Oscillator Connection
CLEXT
XOUT
UC3L
Ci
CL
XIN
CLEXT
7.6.2 32KHz Crystal Oscillator (OSC32K) Characteristics
Figure 7-3 and the equation above also applies to the 32KHz oscillator connection. The user
must choose a crystal oscillator where the crystal load capacitance CL is within the range given
in the table. The exact value of CL can then be found in the crystal datasheet.
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Table 7-12. 32 KHz Crystal Oscillator Characteristics
Symbol
fOUT Parameter Conditions Min Typ Max Unit
tSTARTUP Hz
CL Crystal oscillator frequency 32 768 cycles
30 000(1)
Ci Startup time RS = 60kOhm, CL = 9pF pF
Crystal load capacitance(2)
IOSC32 6 12.5 A
RS kOhm
Internal equivalent load 2
capacitance
Current consumption 0.6
Equivalent series resistance(2)
32 768Hz 35 85
Notes: 1. Nominal crystal cycles.
2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
7.6.3 Phase Locked Loop (PLL) Characteristics
Table 7-13. Phase Locked Loop Characteristics
Symbol
fOUT Parameter Conditions Min Typ Max Unit
fIN Output frequency(1)
IPLL Input frequency(1) 40 240
tSTARTUP MHz
4 16
Current consumption 8 A/MHz
Startup time, from enabling fIN= 4MHz 200
the PLL until the PLL is fIN= 16MHz
locked s
155
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
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7.6.4 Digital Frequency Locked Loop (DFLL) Characteristics
Table 7-14. Digital Frequency Locked Loop Characteristics
Symbol Parameter Conditions Min Typ Max Unit
fOUT Output frequency(2) FINE > 100, all COARSE values (3)
fREF Reference frequency(2) 20 150 MHz
FINE resolution step
8 150 kHz
0.38 %
Frequency drift over voltage Open loop mode See
and temperature Figure 7-4
FINE lock, fREF = 32kHz, SSG disabled 0.1 0.5
ACCURATE lock, fREF = 32kHz, dither clk 0.06 0.5
RCSYS/2, SSG disabled
Accuracy(2) %
FINE lock, fREF = 8-150kHz, SSG
disabled 0.2 1
ACCURATE lock, fREF = 8-150kHz, 0.1 1
dither clk RCSYS/2, SSG disabled
IDFLL Power consumption 25 A/MHz
tSTARTUP Startup time(2)
Within 90% of final values 100 s
tLOCK Lock time
fREF = 32kHz, FINE lock, SSG disabled 8
fREF = 32kHz, ACCURATE lock, dithering ms
clock = RCSYS/2, SSG disabled 28
Notes: 1. Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the DFLL0SSG register.
2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
3. The FINE and COARSE values are selected by wrirting to the DFLL0VAL.FINE and DFLL0VAL.COARSE field respectively.
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Figure 7-4. DFLL Open Loop Frequency Variation(1)(2)
DFLL Open Loop Frequency variation
160
150
140
Frequencies (MHz) 130
120 1,98V
1,8V
1.62V
110
100
90
80
-40 -20 0 20 40 60 80
Tem pera ture
Notes: 1. The plot shows a typical open loop mode behavior with COARSE= 99 and FINE= 255
7.6.5 2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
120MHz RC Oscillator (RC120M) Characteristics
Table 7-15. Internal 120MHz RC Oscillator Characteristics
Symbol
fOUT Parameter Conditions Min Typ Max Unit
IRC120M Output frequency(1)
tSTARTUP 88 120 152 MHz
Current consumption 1.2 mA
Startup time(1)
VVDDCORE = 1.8V 3 s
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
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7.6.6 32kHz RC Oscillator (RC32K) Characteristics
Table 7-16. 32kHz RC Oscillator Characteristics
Symbol
fOUT Parameter Conditions Min Typ Max Unit
IRC32K Output frequency(1)
tSTARTUP 20 32 44 kHz
Current consumption 0.7 A
Startup time(1)
100 s
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
7.6.7 System RC Oscillator (RCSYS) Characteristics
Table 7-17. System RC Oscillator Characteristics
Symbol
fOUT Parameter Conditions Min Typ Max Unit
111.6
Output frequency Calibrated at 85C 115 118.4 kHz
7.7 Flash Characteristics
Table 7-18 gives the device maximum operating frequency depending on the number of flash
wait states and the flash read mode. The FSW bit in the FLASHCDW FSR register controls the
number of wait states used when accessing the flash memory.
Table 7-18. Maximum Operating Frequency
Flash Wait States Read Mode Maximum Operating Frequency
50 MHz
1 25 MHz
High speed read mode 30 MHz
15 MHz
0
1
Normal read mode
0
Table 7-19. Flash Characteristics
Symbol Parameter Conditions Min Typ Max Unit
tFPP Page programming time 5
tFPE Page erase time 5
1
tFFP Fuse programming time fCLK_HSB = 50MHz ms
tFEA Full chip erase time (EA) 6
tFCE JTAG chip erase time (CHIP_ERASE) fCLK_HSB = 115kHz 310
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Table 7-20. Flash Endurance and Data Retention Conditions Min Typ Max Unit
Symbol Parameter
NFARRAY Array endurance (write/page) 100 k cycles
NFFUSE General Purpose fuses endurance (write/bit) 10 k
tRET Data retention
15 years
7.8 Analog Characteristics
7.8.1 Voltage Regulator Characteristics
Table 7-21. VREG Electrical Characteristics
Symbol Parameter Condition Min Typ Max Units
VVDDIN Input voltage range
VVDDCORE Output voltage, calibrated value VVDDIN >= 1.98V 1.98 3.3 3.6
IOUT = 0.1mA to 60mA,
VVDDIN > 1.98V V
IOUT = 0.1mA to 60mA,
VVDDIN < 1.98V 1.8
Normal mode
Output voltage accuracy(1) Low power mode 2
Normal mode %
Low power mode
4
IOUT DC output current(1) 60
IVREG Static current of internal regulator mA
1
13
A
4
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Table 7-22. Decoupling Requirements
Symbol Parameter Condition Typ Techno. Units
CIN1 Input regulator capacitor 1 33
CIN2 Input regulator capacitor 2 nF
CIN3 Input regulator capacitor 3
COUT1 Output regulator capacitor 1 100
10 F
100 nF
COUT2 Output regulator capacitor 2 2.2 Tantalum F
0.5
Note: 1. Refer to Section 6.1.2 on page 36.
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7.8.2 Power-on Reset 18 Characteristics
Table 7-23. POR18 Characteristics
Symbol
VPOT+ Parameter Condition Min Typ Max Units
VPOT- 1.2 1.45 1.58 V
Voltage threshold on VVDDCORE rising 1.32
tDET Voltage threshold on VVDDCORE falling
Time with VDDCORE < VPOT- 460 s
IPOR18 Detection time(1) necessary to generate a reset
tSTARTUP
signal
Current consumption 4 A
Startup time(1)
6 s
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Figure 7-5. POR18 Operating Principle
VVDDCORE
VPOT+
VPOT-
Time
Reset
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7.8.3 Power-on Reset 33 Characteristics
Table 7-24. POR33 Characteristics Condition Min Typ Max Units
Symbol Parameter 1.49 1.58 V
VPOT+ Voltage threshold on VVDDIN rising 1.45
VPOT- Voltage threshold on VVDDIN falling 1.3
tDET Detection time(1) Time with VDDIN < VPOT- 460 s
necessary to generate a reset
signal
IPOR33 Current consumption 20 A
tSTARTUP Startup time(1)
400 s
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Figure 7-6. POR33 Operating Principle
VVDDIN
VPOT+
VPOT-
Time
Reset
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7.8.4 Brown Out Detector Characteristics
The values in Table 7-25 describe the values of the BODLEVEL in the flash General Purpose
Fuse register.
Table 7-25. BODLEVEL Values
BODLEVEL Value Min Typ Max Units
V
011111 binary (31) 0x1F 1.60
100111 binary (39) 0x27 1.69
Table 7-26. BOD Characteristics Condition Min Typ Max Units
Symbol Parameter
VHYST BOD hysteresis T = 25C 10 mV
tDET Detection time Time with VDDCORE < 1 s
BODLEVEL necessary to
generate a reset signal
IBOD Current consumption 7 A
tSTARTUP Startup time
5 s
7.8.5 Supply Monitor 33 Characteristics
Table 7-27. SM33 Characteristics Condition Min Typ Max Units
Symbol Calibrated(1), T = 25C 1.675 1.75
VTH Parameter 1.825 V
VHYST Voltage threshold 11
mV
Step size, between adjacent values
in SCIF.SM33.CALIB(2) 30
Hysteresis(2)
Time with VDDIN < VTH
tDET Detection time necessary to generate a reset 280 s
signal
ISM33 Current consumption Normal mode 17 A
tSTARTUP Startup time
Normal mode 140 s
Notes: 1. Calibration value can be read from the SM33.CALIB field. This field is updated by the flash fuses after a reset. Refer to SCIF
chapter for details.
2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
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7.8.6 Analog to Digital Converter Characteristics
Table 7-28. ADC Characteristics
Symbol Parameter Conditions Min Typ Max Units
12-bit resolution mode
fADC ADC clock frequency 10-bit resolution mode 6 MHz
8-bit resolution mode
fADC ADC clock frequency Return from Idle Mode 6
fADC = 6MHz MHz
VVDD > 3.0V, fADC = 6MHz,
12-bit resolution mode, 6
low impedance source
tSTARTUP Startup time VVDD > 3.0V, fADC = 6MHz, 15 s
tCONV Conversion time (latency) 10-bit resolution mode,
low impedance source 11 26 cycles
VVDD > 3.0V, fADC = 6MHz,
Throughput rate 8-bit resolution mode, 28 kSPS
low impedance source
Throughput rate VADVREFP = VVDDANA 460
ADC Clock = 6MHz kSPS
fADC = 6MHz 460
VADVREFP Reference voltage range 1.62 1.98 V
IADC
Current consumption on VVDDANA 350
IADVREFP Current consumption on ADVREFP A
pin
150
Note: These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process
technology. These values are not covered by test limits in production.
7.8.6.1 Inputs and Sample and Hold Acquisition Times
Table 7-29. Analog Inputs Conditions Min Typ Max Units
Symbol Parameter
12-bit mode
VADn Input Voltage Range 10-bit mode 0 VADVREFP V
8-bit mode
CONCHIP Internal Capacitance(1) 22.5 pF
RONCHIP Internal Resistance(1) VVDDIO = 3.0V to 3.6V, 3.15
VVDDCORE = 1.8V kOhm
VVDDIO = VVDDCORE = 1.62V to 1.98V
55.9
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the
ADC in order to achieve maximum accuracy. Seen externally the ADC input consists of a resis-
tor ( RONCHIP ) and a capacitor ( CONCHIP ). In addition, the resistance ( RSOURCE ) and capacitance
( CSOURCE ) of the PCB and source must be taken into account when calculating the required
sample and hold time. Figure 7-7 shows the ADC input channel equivalent circuit.
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Figure 7-7. ADC Input Positive Input RONCHIP
RSOURCE
VIN CSOURCE CONCHIP
ADCVREFP/2
The minimum sample and hold time (in ns) can be found using this formula:
tSAMPLEHOLD (RONCHIP + RSOURCE) (CONCHIP + CSOURCE) ln (2n + 1)
Where n is the number of bits in the conversion. tSAMPLEHOLD is defined by the SHTIM field in the
ADCIFB ACR register. Please refer to the ADCIFB chapter for more information.
7.8.6.2 Applicable Conditions and Derating Data
Table 7-30. Transfer Characteristics 12-bit Resolution Mode(1)
Parameter Conditions Min Typ Max Units
Resolution 12 Bit
ADC clock frequency = 6MHz,
+/-4
Input Voltage Range = 0 - VADVREFP
Integral non-linearity ADC clock frequency = 6MHz,
Differential non-linearity
Input Voltage Range = (10% VADVREFP) - +/-2
(90% VADVREFP) LSB
-1.5 1.5
Offset error ADC clock frequency = 6MHz +/-3
Gain error +/-5
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Table 7-31. Transfer Characteristics, 10-bit Resolution Mode(1)
Parameter Conditions Min Typ Max Units
Resolution 10 Bit
Integral non-linearity +/-1
Differential non-linearity ADC clock frequency = 6MHz -1 1 LSB
Offset error
+/-1
Gain error +/-2
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Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Table 7-32. Transfer Characteristics, 8-bit Resolution Mode(1)
Parameter Conditions Min Typ Max Units
Resolution ADC clock frequency = 6MHz
Integral non-linearity 8 Bit
Differential non-linearity
Offset error +/-0.5
-0.3 0.3 LSB
+/-1
Gain error +/-1
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
7.8.7 cess technology. These values are not covered by test limits in production.
Temperature Sensor Characteristics
Table 7-33. Temperature Sensor Characteristics(1)
Symbol
Parameter Condition Min Typ Max Units
ITS
tSTARTUP Gradient 1 mV/C
Current consumption 1 A
Startup time 0 s
Note: 1. The Temperature Sensor is not calibrated. The accuracy of the Temperature Sensor is governed by the ADC accuracy.
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7.8.8 Analog Comparator Characteristics
Table 7-34. Analog Comparator Characteristics
Symbol Parameter Condition Min Typ Max Units
Positive input -0.2 VVDDIO + 0.3
voltage range(3) V
Negative input -0.2 VVDDIO - 0.6
voltage range(3)
Statistical offset(3) VACREFN = 1.0V, 20 mV
fAC = 12MHz,
filter length = 2,
hysteresis = 0(1)
fAC Clock frequency for 12 MHz
GCLK4(3)
Throughput rate(3) fAC = 12MHz 12 000 000 Comparisons
per second
Propagation delay Delay from input t--C----L---K---A----C---I1--F---B---------f--A---C-- + 3 tCLKACIFB ns
change to
Interrupt Status
IAC Current Register Changes 420 A
consumption(3)
All channels,
VDDIO = 3.3V,
fA = 3MHz
tSTARTUP Startup time 3 cycles
Input current per 0.2 A/MHz(2)
pin(3)
Notes: 1. AC.CONFn.FLEN and AC.CONFn.HYS fields, refer to the Analog Comparator Interface chapter.
2. Referring to fAC.
3. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
7.8.9 Capacitive Touch Characteristics
7.8.9.1 Discharge Current Source
Table 7-35. DICS Characteristics
Symbol Parameter Min Typ Max Unit
kOhm
RREF Internal resistor 170
k Trim step size(1) %
0.7
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
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7.8.9.2 Strong Pull-up Pull-down
Table 7-36. Strong Pull-up Pull-down Min Typ Max Unit
Parameter
Pull-down resistor 1
Pull-up resistor kOhm
1
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7.9 Timing Characteristics
7.9.1 Startup, Reset, and Wake-up Timing
The startup, reset, and wake-up timings are calculated using the following formula:
t = tCONST + NCPU tCPU
Where tCONST and NCPU are found in Table 7-37. tCPU is the period of the CPU clock. If a
clock source other than RCSYS is selected as the CPU clock, the oscillator startup time,
tOSCSTART , must be added to the wake-up time from the stop, deepstop, and static sleep
modes. Please refer to the source for the CPU clock in the "Oscillator Characteristics" on page
49 for more details about oscillator startup times.
Table 7-37. Maximum Reset and Wake-up Timing(1)
Parameter Measuring Max tCONST (in s) Max NCPU
Startup time from power-up, using Time from VDDIN crossing the VPOT+ threshold of 2210 0
regulator POR33 to the first instruction entering the decode
stage of CPU. VDDCORE is supplied by the internal
regulator.
Startup time from power-up, no Time from VDDIN crossing the VPOT+ threshold of 1810 0
regulator POR33 to the first instruction entering the decode
stage of CPU. VDDCORE is connected to VDDIN.
Time from releasing a reset source (except POR18,
Startup time from reset release POR33, and SM33) to the first instruction entering 170 0
the decode stage of CPU.
Idle 0 19
Frozen 0 110
Standby From wake-up event to the first instruction of an 0 110
Stop
Wake-up interrupt routine entering the decode stage of the
CPU. 27 + tOSCSTART 116
Deepstop 27 + tOSCSTART 116
Static
97 + tOSCSTART 116
Wake-up from shutdown From wake-up event to the first instruction entering 1180 0
the decode stage of the CPU.
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
7.9.2 RESET_N Timing
Table 7-38. RESET_N Waveform Parameters(1) Conditions Min Max Units
Symbol Parameter ns
tRESET RESET_N minimum pulse length 10
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
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7.9.3 USART in SPI Mode Timing
7.9.3.1 Master mode
Figure 7-8. USART in SPI Master Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
SPCK
MISO
USPI0 USPI1
MOSI
USPI2
Figure 7-9. USART in SPI Master Mode with (CPOL= 0 and CPHA= 1) or (CPOL= 1 and
CPHA= 0)
SPCK
MISO
USPI3 USPI4
MOSI
USPI5
Table 7-39. USART in SPI Mode Timing, Master Mode(1) Conditions Min Max Units
Symbol Parameter 28.7 + tSAMPLE(2)
USPI0 MISO setup time before SPCK rises VVDDIO from 16.5
USPI1 MISO hold time after SPCK rises 3.0V to 3.6V, 0 ns
USPI2 SPCK rising to MOSI delay
USPI3 MISO setup time before SPCK falls maximum 25.8 + tSAMPLE(2) 21.19
USPI4 MISO hold time after SPCK falls external 0
USPI5 SPCK falling to MOSI delay capacitor =
40 pF
Notes: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
2. Where: tSAMPLE = tSPCK -2---------t--tC--S-L-P--K--C--U-K---S--A----R---T- 12-- tCLKUSART
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Maximum SPI Frequency, Master Output
The maximum SPI master output frequency is given by the following formula:
fSPCKMAX = MIN(fPINMAX,S----P-1---I--n--, -f-C----L---K----S-9-P----I--------2-)
Where SPIn is the MOSI delay, USPI2 or USPI5 depending on CPOL and NCPHA. fPINMAX is
the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for
the maximum frequency of the pins. fCLKSPI is the maximum frequency of the CLK_SPI. Refer
to the SPI chapter for a description of this clock.
7.9.3.2 Maximum SPI Frequency, Master Input
The maximum SPI master input frequency is given by the following formula:
fSPCKMAX = MIN(S----P----I--n-----+--1---t-V----A---L---I--D--,f--C----L---K----S9--P----I--------2-)
Where SPIn is the MISO setup and hold time, USPI0 + USPI1 or USPI3 + USPI4 depending on
CPOL and NCPHA. TVALID is the SPI slave response time. Please refer to the SPI slave
datasheet for TVALID . fCLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI chap-
ter for a description of this clock.
Slave mode
Figure 7-10. USART in SPI Slave Mode with (CPOL= 0 and CPHA= 1) or (CPOL= 1 and
CPHA= 0)
SPCK
MISO
USPI6
MOSI
USPI7 USPI8
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Figure 7-11. USART in SPI Slave Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1)
SPCK
MISO
USPI9
MOSI
USPI10 USPI11
Figure 7-12. USART in SPI Slave Mode, NPCS Timing
SPCK, CPOL=0 USPI12 USPI13
SPCK, CPOL=1 USPI14 USPI15
NSS
Table 7-40. USART in SPI mode Timing, Slave Mode(1) Conditions Min Max Units
Symbol Parameter
USPI6 SPCK falling to MISO delay VVDDIO from 2.6 + tSAMPLE(2) + 37.3
3.0V to 3.6V, tCLK_USART
USPI7 MOSI setup time before SPCK rises 0
maximum
USPI8 MOSI hold time after SPCK rises external 2.6 + tSAMPLE(2) + 37.0
USPI9 SPCK rising to MISO delay capacitor = tCLK_USART ns
0
USPI10 MOSI setup time before SPCK falls 40 pF 27.2
0
USPI11 MOSI hold time after SPCK falls 27.2
USPI12 NSS setup time before SPCK rises 0
USPI13 NSS hold time after SPCK falls
USPI14 NSS setup time before SPCK falls
USPI15 NSS hold time after SPCK rises
Notes: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
2. Where: tSAMPLE = tS PCK -2---------t--tC--S--LP--K--C--U-K---S--A----R---T- + 12-- tCLKUSART
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Maximum SPI Frequency, Slave Input Mode
The maximum SPI slave input frequency is given by the following formula:
fSPCKMAX = MIN(f--C----L---K----S-9-P----I--------2-,S----P-1---I--n--)
Where SPIn is the MOSI setup and hold time, USPI7 + USPI8 or USPI10 + USPI11 depending
on CPOL and NCPHA. fCLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI
chapter for a description of this clock.
Maximum SPI Frequency, Slave Output Mode
The maximum SPI slave output frequency is given by the following formula:
fSPCKMAX = MIN(f--C----L---K----S9--P----I--------2-, fPINMAX,-S---P----I--n-----+--1---t--S--E----T---U----P-)
Where SPIn is the MISO delay, USPI6 or USPI9 depending on CPOL and NCPHA. TSETUP is
the SPI master setup time. Please refer to the SPI master datasheet for TSETUP . fCLKSPI is the
maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this
clock.fPINMAX is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteris-
tics section for the maximum frequency of the pins.
7.9.4 SPI Timing
7.9.4.1 Master mode
Figure 7-13. SPI Master Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
SPCK
MISO
SPI0 SPI1
MOSI
SPI2
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Figure 7-14. SPI Master Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
SPCK
MISO
SPI3 SPI4
MOSI
SPI5
Table 7-41. SPI Timing, Master Mode(1) Conditions Min Max Units
Symbol Parameter 33.4 + (tCLK_SPI)/2 7.1 ns
SPI0 MISO setup time before SPCK rises VVDDIO from 8.63
SPI1 MISO hold time after SPCK rises 3.0V to 3.6V, 0
SPI2 SPCK rising to MOSI delay
SPI3 MISO setup time before SPCK falls maximum 29.2 + (tCLK_SPI)/2
SPI4 MISO hold time after SPCK falls external 0
SPI5 SPCK falling to MOSI delay capacitor =
40 pF
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Maximum SPI Frequency, Master Output
The maximum SPI master output frequency is given by the following formula:
fSPCKMAX = MIN(fPINMAX,S----P-1---I--n--)
Where SPIn is the MOSI delay, SPI2 or SPI5 depending on CPOL and NCPHA. fPINMAX is the
maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the
maximum frequency of the pins.
Maximum SPI Frequency, Master Input
The maximum SPI master input frequency is given by the following formula:
fSPCKMAX = -----------------1------------------
SPIn + tVALID
Where SPIn is the MISO setup and hold time, SPI0 + SPI1 or SPI3 + SPI4 depending on
CPOL and NCPHA. tVALID is the SPI slave response time. Please refer to the SPI slave
datasheet for tVALID .
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7.9.4.2 Slave mode
Figure 7-15. SPI Slave Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
SPCK
MISO
SPI6
MOSI
SPI7 SPI8
Figure 7-16. SPI Slave Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
SPCK
MISO
SPI9
MOSI
SPI10 SPI11
Figure 7-17. SPI Slave Mode, NPCS Timing
SPCK, CPOL=0 SPI12 SPI13
SPCK, CPOL=1 SPI14 SPI15
NPCS
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Table 7-42. SPI Timing, Slave Mode(1) Conditions Min Max Units
Symbol Parameter
SPI6 SPCK falling to MISO delay 29.4
SPI7 MOSI setup time before SPCK rises
SPI8 MOSI hold time after SPCK rises 0
SPI9 SPCK rising to MISO delay
SPI10 MOSI setup time before SPCK falls 6.0
SPI11 MOSI hold time after SPCK falls
SPI12 NPCS setup time before SPCK rises VVDDIO from 29.0
SPI13 NPCS hold time after SPCK falls ns
SPI14 NPCS setup time before SPCK falls 3.0V to 3.6V, 0
SPI15 NPCS hold time after SPCK rises
maximum
external 5.5
capacitor =
40 pF 3.4
1.1
3.3
0.7
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
Maximum SPI Frequency, Slave Input Mode
The maximum SPI slave input frequency is given by the following formula:
fSPCKMAX = MIN(fCLKSPI,S----P-1---I--n--)
Where SPIn is the MOSI setup and hold time, SPI7 + SPI8 or SPI10 + SPI11 depending on
CPOL and NCPHA. fCLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI chap-
ter for a description of this clock.
7.9.5 Maximum SPI Frequency, Slave Output Mode
The maximum SPI slave output frequency is given by the following formula:
fSPCKMAX = MIN(fPINMAX,-S---P----I--n-----+--1---t-S---E----T---U---P--)
Where SPIn is the MISO delay, SPI6 or SPI9 depending on CPOL and NCPHA. tSETUP is the
SPI master setup time. Please refer to the SPI master datasheet for tSETUP . fPINMAX is the max-
imum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the
maximum frequency of the pins.
TWIM/TWIS Timing
Figure 7-43 shows the TWI-bus timing requirements and the compliance of the device with
them. Some of these requirements (tr and tf) are met by the device without requiring user inter-
vention. Compliance with the other requirements (tHD-STA, tSU-STA, tSU-STO, tHD-DAT, tSU-DAT-TWI, tLOW-
TWI, tHIGH, and fTWCK) requires user intervention through appropriate programming of the relevant
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TWIM and TWIS user interface registers. Please refer to the TWIM and TWIS sections for more
information.
Table 7-43. TWI-Bus Timing Requirements
Minimum Maximum
Symbol Parameter Mode Requirement Device Requirement Device Unit
Standard(1) - 1000
ns
tr TWCK and TWD rise time Fast(1)
300
20 + 0.1Cb
Standard - 300
ns
tf TWCK and TWD fall time
300
Fast 20 + 0.1Cb
tHD-STA Standard 4 - s
(Repeated) START hold time tclkpb
Fast 0.6
tSU-STA Standard 4.7 - s
(Repeated) START set-up time tclkpb
Fast 0.6
tSU-STO STOP set-up time Standard 4.0 - s
Fast 4tclkpb
0.6
tHD-DAT Data hold time Standard 0.3(2) 2tclkpb 3.45() 15tprescaled + tclkpb s
Fast 0.9()
250 2tclkpb
tSU-DAT-TWI Data set-up time Standard 100 tclkpb 100 - ns
Fast 4tclkpb 400
- tclkpb
tSU-DAT - 4.7 8tclkpb - -
tLOW-TWI TWCK LOW period Standard 1.3
Fast - s
-
tLOW - 4.0 - -
tHIGH Standard 0.6
TWCK HIGH period Fast - s
fTWCK TWCK frequency Standard - -----------1------------ kHz
Fast 12tclkpb
Notes: 1. Standard mode: fTWCK 100 kHz ; fast mode: fTWCK > 100 kHz .
2. A device must internally provide a hold time of at least 300 ns for TWD with reference to the falling edge of TWCK.
Notations:
Cb = total capacitance of one bus line in pF
tclkpb = period of TWI peripheral bus clock
tprescaled = period of TWI internal prescaled clock (see chapters on TWIM and TWIS)
The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW-TWI)
of TWCK.
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7.9.6 JTAG Timing
Figure 7-18. JTAG Interface Signals
JTAG2
TCK
JTAG0 JTAG1
TMS/TDI
JTAG3 JTAG4
TDO JTAG5
JTAG6
Boundary
Scan Inputs JTAG7 JTAG8
Boundary
Scan Outputs
JTAG9
JTAG10
Table 7-44. JTAG Timings(1) Conditions Min Max Units
Symbol Parameter ns
JTAG0 TCK Low Half-period 21.8 21.8
JTAG1 TCK High Half-period 32.2
JTAG2 TCK Period 8.6
JTAG3 TDI, TMS Setup before TCK High
JTAG4 TDI, TMS Hold after TCK High 30.3
JTAG5 TDO Hold Time
JTAG6 TCK Low to TDO Valid VVDDIO from 2.0
JTAG7 Boundary Scan Inputs Setup Time
JTAG8 Boundary Scan Inputs Hold Time 3.0V to 3.6V, 2.3
JTAG9 Boundary Scan Outputs Hold Time
JTAG10 TCK to Boundary Scan Outputs Valid maximum 9.5
external
capacitor =
40 pF
0.6
6.9
9.3
Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro-
cess technology. These values are not covered by test limits in production.
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8. Mechanical Characteristics
8.1 Thermal Considerations
8.1.1 Thermal Data
Table 8-1 summarizes the thermal resistance data depending on the package.
Table 8-1. Thermal Resistance Data
Symbol Parameter Condition Package Typ Unit
C/W
JA Junction-to-ambient thermal resistance Still Air TQFP48 54.4 C/W
C/W
JC Junction-to-case thermal resistance TQFP48 15.7
JA Junction-to-ambient thermal resistance Still Air QFN48 26.0
JC Junction-to-case thermal resistance QFN48 1.6
JA Junction-to-ambient thermal resistance Still Air TLLGA48 25.4
JC Junction-to-case thermal resistance TLLGA48 12.7
8.1.2 Junction Temperature
The average chip-junction temperature, TJ, in C can be obtained from the following:
1. TJ = TA + (PD JA)
2. TJ = TA + (P D ( HEATSINK + JC ) )
where:
JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 8-1.
JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in
Table 8-1.
HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet.
PD = device power consumption (W) estimated from data provided in Section 7.4 on page 42.
TA = ambient temperature (C).
From the first equation, the user can derive the estimated lifetime of the chip and decide if a
cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second
equation should be used to compute the resulting average chip-junction temperature TJ in C.
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8.2 Package Drawings
Figure 8-1. TQFP-48 Package Drawing
Table 8-2. Device and Package Maximum Weight
140
mg
Table 8-3. Package Characteristics
Moisture Sensitivity Level MSL3
Table 8-4. Package Reference MS-026
JEDEC Drawing Reference E3
JESD97 Classification
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Figure 8-2. QFN-48 Package Drawing
Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability.
Table 8-5. Device and Package Maximum Weight
140
mg
Table 8-6. Package Characteristics
Moisture Sensitivity Level MSL3
Table 8-7. Package Reference M0-220
JEDEC Drawing Reference E3
JESD97 Classification
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Figure 8-3. TLLGA-48 Package Drawing
Table 8-8. Device and Package Maximum Weight
39.3
mg
Table 8-9. Package Characteristics
Moisture Sensitivity Level MSL3
Table 8-10. Package Reference N/A
JEDEC Drawing Reference E4
JESD97 Classification
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8.3 Soldering Profile
Table 8-11 gives the recommended soldering profile from J-STD-20.
Table 8-11. Soldering Profile Green Package
Profile Feature 3C/s max
Average Ramp-up Rate (217C to Peak) 150-200C
Preheat Temperature 175C 25C 60-150 s
Time Maintained Above 217C 30 s
Time within 5C of Actual Peak Temperature 260C
Peak Temperature Range 6C/s max
Ramp-down Rate 8 minutes max
Time 25C to Peak Temperature
A maximum of three reflow passes is allowed per component.
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9. Ordering Information
Table 9-1. Ordering Information
Device Ordering Code Carrier Type Package Package Type Temperature Operating
AT32UC3L0256 AT32UC3L0256-AUTES ES TQFP 48 Range
AT32UC3L0128 AT32UC3L0256-AUT Tray
AT32UC3L0256-AUR QFN 48 JESD97 Classification E3
AT32UC3L0256-ZAUTES Tape & Reel
AT32UC3L0256-ZAUT ES TLLGA 48 JESD97 Classification E4 Industrial (-40C to 85C)
AT32UC3L0256-ZAUR Tray TQFP 48 JESD97 Classification E3
AT32UC3L0256-D3HES QFN 48 JESD97 Classification E4
AT32UC3L0256-D3HT Tape & Reel TLLGA 48
AT32UC3L0256-D3HR ES
AT32UC3L0128-AUT Tray
AT32UC3L0128-AUR
AT32UC3L0128-ZAUT Tape & Reel
AT32UC3L0128-ZAUR Tray
AT32UC3L0128-D3HT
AT32UC3L0128-D3HR Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
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10. Errata AT32UC3L0128/256
10.1 Rev. C 1. The RC32K output on PA20 is not always permanently disabled
The RC32K output on PA20 may sometimes re-appear.
10.1.1 SCIF Fix/Workaround
Before using RC32K for other purposes, the following procedure has to be followed in order
10.1.2 SPI to properly disable it:
- Run the CPU on RCSYS
32145BS01/2012 - Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT
- Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as
one
- Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as
zero.
2. PLLCOUNT value larger than zero can cause PLLEN glitch
Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-
nal during asynchronous wake up.
Fix/Workaround
The lock-masking mechanism for the PLL should not be used.
The PLLCOUNT field of the PLL Control Register should always be written to zero.
3. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature
The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca-
tion in the SCIF memory range.
Fix/Workaround
None.
1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
2. Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the
SPI and PDCA.
3. SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
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10.1.4 TC 4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
10.1.5 CAT NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
32145BS01/2012 (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
5. SPI mode fault detection enable causes incorrect behavior
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate
properly.
Fix/Workaround
Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.
6. SPI RDR.PCS is not correct
The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not
correctly indicate the value on the NPCS pins at the end of a transfer.
Fix/Workaround
Do not use the PCS field of the SPI RDR.
1. SMBALERT bit may be set after reset
The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after
system reset.
Fix/Workaround
After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.
2. Clearing the NAK bit before the BTF bit is set locks up the TWI bus
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to
attempt to continue transmitting data, thus locking up the bus.
Fix/Workaround
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been
set.
1. Channel chaining skips first pulse for upper channel
When chaining two channels using the Block Mode Register, the first pulse of the clock
between the channels is skipped.
Fix/Workaround
Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle
for the upper channel. After the dummy cycle has been generated, indicated by the
SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real
values.
1. CAT QMatrix sense capacitors discharged prematurely
At the end of a QMatrix burst charging sequence that uses different burst count values for
different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph-
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10.2 Rev. B eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency.
This results in premature loss of charge from the sense capacitors and thus increased vari-
10.2.1 SCIF ability of the acquired count values.
Fix/Workaround
32145BS01/2012 Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11,
13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register.
2. Autonomous CAT acquisition must be longer than AST source clock period
When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the
CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST
source clock is larger than one CAT acquisition. One AST clock period after the AST trigger,
the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely,
ruining the result.
Fix/Workaround
Always ensure that the ATCFG1.max field is set so that the duration of the autonomous
touch acquisition is greater than one clock period of the AST source clock.
1. aWire MEMORY_SPEED_REQUEST command does not return correct CV
The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to
the formula in the aWire Debug Interface chapter.
Fix/Workaround
Issue a dummy read to address 0x100000000 before issuing the
MEMORY_SPEED_REQUEST command and use this formula instead:
fsab = -C---7-V--f--a---w---3-
1. The RC32K output on PA20 is not always permanently disabled
The RC32K output on PA20 may sometimes re-appear.
Fix/Workaround
Before using RC32K for other purposes, the following procedure has to be followed in order
to properly disable it:
- Run the CPU on RCSYS
- Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT
- Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as
one
- Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as
zero.
2. PLLCOUNT value larger than zero can cause PLLEN glitch
Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-
nal during asynchronous wake up.
Fix/Workaround
The lock-masking mechanism for the PLL should not be used.
The PLLCOUNT field of the PLL Control Register should always be written to zero.
3. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature
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10.2.3 SPI
The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca-
32145BS01/2012 tion in the SCIF memory range.
Fix/Workaround
None.
1. WDT Control Register does not have synchronization feedback
When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN),
Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchro-
nizer is started to propagate the values to the WDT clcok domain. This synchronization
takes a finite amount of time, but only the status of the synchronization of the EN bit is
reflected back to the user. Writing to the synchronized fields during synchronization can lead
to undefined behavior.
Fix/Workaround
-When writing to the affected fields, the user must ensure a wait corresponding to 2 clock
cycles of both the WDT peripheral bus clock and the selected WDT clock source.
-When doing writes that changes the EN bit, the EN bit can be read back until it reflects the
written value.
1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
2. Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the
SPI and PDCA.
3. SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
5. SPI mode fault detection enable causes incorrect behavior
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate
83
10.2.4 TWI AT32UC3L0128/256
10.2.5 PWMA properly.
10.2.6 TC Fix/Workaround
Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.
6. SPI RDR.PCS is not correct
The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not
correctly indicate the value on the NPCS pins at the end of a transfer.
Fix/Workaround
Do not use the PCS field of the SPI RDR.
1. TWIS may not wake the device from sleep mode
If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condi-
tion, the CPU may not wake upon a TWIS address match. The request is NACKed.
Fix/Workaround
When using the TWI address match to wake the device from sleep, do not switch to sleep
modes deeper than Frozen. Another solution is to enable asynchronous EIC wake on the
TWIS clock (TWCK) or TWIS data (TWD) pins, in order to wake the system up on bus
events.
2. SMBALERT bit may be set after reset
The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after
system reset.
Fix/Workaround
After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.
3. Clearing the NAK bit before the BTF bit is set locks up the TWI bus
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to
attempt to continue transmitting data, thus locking up the bus.
Fix/Workaround
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been
set.
1. The SR.READY bit cannot be cleared by writing to SCR.READY
The Ready bit in the Status Register will not be cleared when writing a one to the corre-
sponding bit in the Status Clear register. The Ready bit will be cleared when the Busy bit is
set.
Fix/Workaround
Disable the Ready interrupt in the interrupt handler when receiving the interrupt. When an
operation that triggers the Busy/Ready bit is started, wait until the ready bit is low in the Sta-
tus Register before enabling the interrupt.
1. Channel chaining skips first pulse for upper channel
When chaining two channels using the Block Mode Register, the first pulse of the clock
between the channels is skipped.
Fix/Workaround
84
32145BS01/2012
10.2.7 CAT AT32UC3L0128/256
10.2.8 aWire
Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle
for the upper channel. After the dummy cycle has been generated, indicated by the
SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real
values.
1. CAT QMatrix sense capacitors discharged prematurely
At the end of a QMatrix burst charging sequence that uses different burst count values for
different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph-
eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency.
This results in premature loss of charge from the sense capacitors and thus increased vari-
ability of the acquired count values.
Fix/Workaround
Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11,
13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register.
2. Autonomous CAT acquisition must be longer than AST source clock period
When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the
CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST
source clock is larger than one CAT acquisition. One AST clock period after the AST trigger,
the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely,
ruining the result.
Fix/Workaround
Always ensure that the ATCFG1.max field is set so that the duration of the autonomous
touch acquisition is greater than one clock period of the AST source clock.
3. CAT consumes unnecessary power when disabled or when autonomous touch not
used
A CAT prescaler controlled by the ATCFG0.DIV field will be active even when the CAT mod-
ule is disabled or when the autonomous touch feature is not used, thereby causing
unnecessary power consumption.
Fix/Workaround
If the CAT module is not used, disable the CLK_CAT clock in the PM module. If the CAT
module is used but the autonomous touch feature is not used, the power consumption of the
CAT module may be reduced by writing 0xFFFF to the ATCFG0.DIV field.
1. aWire MEMORY_SPEED_REQUEST command does not return correct CV
The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to
the formula in the aWire Debug Interface chapter.
Fix/Workaround
Issue a dummy read to address 0x100000000 before issuing the
MEMORY_SPEED_REQUEST command and use this formula instead:
fsab = -C---7-V--f--a---w---3-
85
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AT32UC3L0128/256
10.3 Rev. A
10.3.1 Device
1. JTAGID is wrong
The JTAGID is 0x021DF03F.
Fix/Workaround
None.
10.3.2 FLASHCDW
1. General-purpose fuse programming does not work
The general-purpose fuses cannot be programmed and are stuck at 1. Please refer to the
Fuse Settings chapter in the FLASHCDW for more information about what functions are
affected.
Fix/Workaround
None.
2. Set Security Bit command does not work
The Set Security Bit (SSB) command of the FLASHCDW does not work. The device cannot
be locked from external JTAG, aWire, or other debug accesses.
Fix/Workaround
None.
3. Flash programming time is longer than specified
The flash programming time is now:
Table 10-1. Flash Characteristics
Symbol Parameter Conditions Min Typ Max Unit
TFPP Page programming time 7.5
TFPE Page erase time
TFFP Fuse programming time 7.5
TFEA Full chip erase time (EA)
JTAG chip erase time fCLK_HSB= 50MHz 1
TFCE (CHIP_ERASE)
ms
9
fCLK_HSB= 115kHz 250
Fix/Workaround
None.
10.3.3 Power Manager
1. Clock Failure Detector (CFD) can be issued while turning off the CFD
While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will
change the main clock source to RCSYS.
Fix/Workaround
Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch
back to original main clock source.
Solution 2: Only turn off the CFD while running the main clock on RCSYS.
2. Sleepwalking in idle and frozen sleep mode will mask all other PB clocks
86
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10.3.4 SCIF AT32UC3L0128/256
32145BS01/2012 If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walk-
ing, all PB clocks will be masked except the PB clock to the sleepwalking module.
Fix/Workaround
Mask all clock requests in the PM.PPCR register before going into idle or frozen mode.
2. Unused PB clocks are running
Three unused PBA clocks are enabled by default and will cause increased active power
consumption.
Fix/Workaround
Disable the clocks by writing zeroes to bits [27:25] in the PBA clock mask register.
1. The RC32K output on PA20 is not always permanently disabled
The RC32K output on PA20 may sometimes re-appear.
Fix/Workaround
Before using RC32K for other purposes, the following procedure has to be followed in order
to properly disable it:
- Run the CPU on RCSYS
- Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT
- Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as
one
- Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as
zero.
2. PLL lock might not clear after disable
Under certain circumstances, the lock signal from the Phase Locked Loop (PLL) oscillator
may not go back to zero after the PLL oscillator has been disabled. This can cause the prop-
agation of clock signals with the wrong frequency to parts of the system that use the PLL
clock.
Fix/Workaround
PLL must be turned off before entering STOP, DEEPSTOP or STATIC sleep modes. If PLL
has been turned off, a delay of 30us must be observed after the PLL has been enabled
again before the SCIF.PLL0LOCK bit can be used as a valid indication that the PLL is
locked.
3. PLLCOUNT value larger than zero can cause PLLEN glitch
Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-
nal during asynchronous wake up.
Fix/Workaround
The lock-masking mechanism for the PLL should not be used.
The PLLCOUNT field of the PLL Control Register should always be written to zero.
4. RCSYS is not calibrated
The RCSYS is not calibrated and will run faster than 115.2kHz. Frequencies around 150kHz
can be expected.
Fix/Workaround
If a known clock source is available the RCSYS can be runtime calibrated by using the fre-
quency meter (FREQM) and tuning the RCSYS by writing to the RCCR register in SCIF.
5. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature
The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca-
tion in the SCIF memory range.
Fix/Workaround
87
10.3.5 WDT AT32UC3L0128/256
10.3.6 GPIO None.
10.3.7 SPI
1. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will
32145BS01/2012 issue a Watchdog reset
If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-
ately issue a Watchdog reset.
Fix/Workaround
Use twice as long timeout period as needed and clear the WDT counter within the first half
of the timeout period. If the WDT counter is cleared after the first half of the timeout period,
you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time
before the reset will be twice as long as needed.
2. WDT Control Register does not have synchronization feedback
When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN),
Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchro-
nizer is started to propagate the values to the WDT clcok domain. This synchronization
takes a finite amount of time, but only the status of the synchronization of the EN bit is
reflected back to the user. Writing to the synchronized fields during synchronization can lead
to undefined behavior.
Fix/Workaround
-When writing to the affected fields, the user must ensure a wait corresponding to 2 clock
cycles of both the WDT peripheral bus clock and the selected WDT clock source.
-When doing writes that changes the EN bit, the EN bit can be read back until it reflects the
written value.
1. Clearing Interrupt flags can mask other interrupts
When clearing interrupt flags in a GPIO port, interrupts on other pins of that port, happening
in the same clock cycle will not be registered.
Fix/Workaround
Read the PVR register of the port before and after clearing the interrupt to see if any pin
change has happened while clearing the interrupt. If any change occurred in the PVR
between the reads, they must be treated as an interrupt.
1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
2. Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the
SPI and PDCA.
88
10.3.8 TWI AT32UC3L0128/256
32145BS01/2012 3. SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
5. SPI mode fault detection enable causes incorrect behavior
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate
properly.
Fix/Workaround
Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.
6. SPI RDR.PCS is not correct
The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not
correctly indicate the value on the NPCS pins at the end of a transfer.
Fix/Workaround
Do not use the PCS field of the SPI RDR.
1. TWIS may not wake the device from sleep mode
If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condi-
tion, the CPU may not wake upon a TWIS address match. The request is NACKed.
Fix/Workaround
When using the TWI address match to wake the device from sleep, do not switch to sleep
modes deeper than Frozen. Another solution is to enable asynchronous EIC wake on the
TWIS clock (TWCK) or TWIS data (TWD) pins, in order to wake the system up on bus
events.
2. SMBALERT bit may be set after reset
The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after
system reset.
Fix/Workaround
After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.
3. Clearing the NAK bit before the BTF bit is set locks up the TWI bus
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to
attempt to continue transmitting data, thus locking up the bus.
Fix/Workaround
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been
set.
4. TWIS stretch on Address match error
89
AT32UC3L0128/256
10.3.9 PWMA When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for
10.3.10 TC the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD
10.3.11 ADCIFB at the same time. This can cause a TWI timing violation.
10.3.12 CAT Fix/Workaround
None.
5. TWIM TWALM polarity is wrong
The TWALM signal in the TWIM is active high instead of active low.
Fix/Workaround
Use an external inverter to invert the signal going into the TWIM. When using both TWIM
and TWIS on the same pins, the TWALM cannot be used.
1. The SR.READY bit cannot be cleared by writing to SCR.READY
The Ready bit in the Status Register will not be cleared when writing a one to the corre-
sponding bit in the Status Clear register. The Ready bit will be cleared when the Busy bit is
set.
Fix/Workaround
Disable the Ready interrupt in the interrupt handler when receiving the interrupt. When an
operation that triggers the Busy/Ready bit is started, wait until the ready bit is low in the Sta-
tus Register before enabling the interrupt.
1. Channel chaining skips first pulse for upper channel
When chaining two channels using the Block Mode Register, the first pulse of the clock
between the channels is skipped.
Fix/Workaround
Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle
for the upper channel. After the dummy cycle has been generated, indicated by the
SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real
values.
1. ADCIFB DMA transfer does not work with divided PBA clock
DMA requests from the ADCIFB will not be performed when the PBA clock is slower than
the HSB clock.
Fix/Workaround
Do not use divided PBA clock when the PDCA transfers from the ADCIFB.
1. CAT QMatrix sense capacitors discharged prematurely
At the end of a QMatrix burst charging sequence that uses different burst count values for
different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph-
eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency.
This results in premature loss of charge from the sense capacitors and thus increased vari-
ability of the acquired count values.
Fix/Workaround
Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11,
13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register.
90
32145BS01/2012
AT32UC3L0128/256
10.3.13 aWire 2. Autonomous CAT acquisition must be longer than AST source clock period
When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the
CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST
source clock is larger than one CAT acquisition. One AST clock period after the AST trigger,
the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely,
ruining the result.
Fix/Workaround
Always ensure that the ATCFG1.max field is set so that the duration of the autonomous
touch acquisition is greater than one clock period of the AST source clock.
3. CAT consumes unnecessary power when disabled or when autonomous touch not
used
A CAT prescaler controlled by the ATCFG0.DIV field will be active even when the CAT mod-
ule is disabled or when the autonomous touch feature is not used, thereby causing
unnecessary power consumption.
Fix/Workaround
If the CAT module is not used, disable the CLK_CAT clock in the PM module. If the CAT
module is used but the autonomous touch feature is not used, the power consumption of the
CAT module may be reduced by writing 0xFFFF to the ATCFG0.DIV field.
4. CAT module does not terminate QTouch burst on detect
The CAT module does not terminate a QTouch burst when the detection voltage is
reached on the sense capacitor. This can cause the sense capacitor to be charged more
than necessary. Depending on the dielectric absorption characteristics of the capacitor, this
can lead to unstable measurements.
Fix/Workaround
Use the minimum possible value for the MAX field in the ATCFG1, TG0CFG1, and
TG1CFG1 registers.
1. aWire MEMORY_SPEED_REQUEST command does not return correct CV
The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to
the formula in the aWire Debug Interface chapter.
Fix/Workaround
Issue a dummy read to address 0x100000000 before issuing the
MEMORY_SPEED_REQUEST command and use this formula instead:
fsab = -C---7-V--f--a---w---3-
10.3.14 I/O Pins
1. PA05 is not 3.3V tolerant.
PA05 should be grounded on the PCB and left unused if VDDIO is above 1.8V.
Fix/Workaround
None.
2. No pull-up on pins that are not bonded
PB13 to PB27 are not bonded on UC3L0256/128, but has no pull-up and can cause current
consumption on VDDIO/VDDIN if left undriven.
Fix/Workaround
91
32145BS01/2012
AT32UC3L0128/256
Enable pull-ups on PB13 to PB27 by writing 0x0FFFE000 to the PUERS1 register in the
GPIO.
3. PA17 has low ESD tolerance
PA17 only tolerates 500V ESD pulses (Human Body Model).
Fix/Workaround
Care must be taken during manufacturing and PCB design.
92
32145BS01/2012
AT32UC3L0128/256
11. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
11.1 Rev. B 01/2012
1. Description: DFLL frequency is 20 to 150MHz, not 40 to 150MHz.
2.
3. Description: "One touch sensor can be configured to operate autonomously..." replaced by "All
4. touch sensors can be configured to operate autonomously...".
5.
Block Diagram: GCLK_IN is input, not output, and is 2 bits wide (GCLK_IN[1..0]). CAT SMP
6. corrected from I/O to output. SPI NPCS corrected from output to I/O.
7.
Package and Pinout: PRND signal removed from Signal Descriptions List table and GPIO
8. Controller Function Multiplexing table.
9.
10. Supply and Startup Considerations: In 1.8V single supply mode figure, the input voltage is
11. 1.62-1.98V, not 1.98-3.6V. "On system start-up, the DFLL is disabled" is replaced by "On
system start-up, all high-speed clocks are disabled".
11.2 Rev. A 12/2011
ADCIFB: PRND signal removed from block diagram.
Electrical Characteristics: Added PLL source clock in the Clock Frequencies table in the
Maximum Clock Frequencies section. Removed 64-pin package information from I/O Pin
Characteristics tables and Digital Clock Characteristics table.
Electrical Characteristics: Removed USB Transceiver Characteristics, as the device contains
no USB.
Mechanical Characteristics: Added notes to package drawings.
Summary: Removed Programming and Debugging chapter, added Processor and Architecture
chapter.
Datasheet Revision History: Corrected release date for datasheet rev. A; the correct date is
12/2011.
1. Initial revision.
93
32145BS01/2012
AT32UC3L0128/256
Table of Contents
Features ..................................................................................................... 1
1 Description ............................................................................................... 3
2 Overview ................................................................................................... 5
2.1 Block Diagram ...................................................................................................5
2.2 Configuration Summary .....................................................................................6
3 Package and Pinout ................................................................................. 7
3.1 Package .............................................................................................................7
3.2 Peripheral Multiplexing on I/O Lines ..................................................................8
3.3 Signal Descriptions ..........................................................................................13
3.4 I/O Line Considerations ...................................................................................16
4 Processor and Architecture .................................................................. 18
4.1 Features ..........................................................................................................18
4.2 AVR32 Architecture .........................................................................................18
4.3 The AVR32UC CPU ........................................................................................19
4.4 Programming Model ........................................................................................23
4.5 Exceptions and Interrupts ................................................................................27
5 Memories ................................................................................................ 32
5.1 Embedded Memories ......................................................................................32
5.2 Physical Memory Map .....................................................................................32
5.3 Peripheral Address Map ..................................................................................33
5.4 CPU Local Bus Mapping .................................................................................34
6 Supply and Startup Considerations ..................................................... 36
6.1 Supply Considerations .....................................................................................36
6.2 Startup Considerations ....................................................................................40
7 Electrical Characteristics ...................................................................... 41
7.1 Absolute Maximum Ratings* ...........................................................................41
7.2 Supply Characteristics .....................................................................................41
7.3 Maximum Clock Frequencies ..........................................................................42
7.4 Power Consumption ........................................................................................42
7.5 I/O Pin Characteristics .....................................................................................46
7.6 Oscillator Characteristics .................................................................................49
7.7 Flash Characteristics .......................................................................................54
i
32145BS01/2012
AT32UC3L0128/256
7.8 Analog Characteristics .....................................................................................55
7.9 Timing Characteristics .....................................................................................64
8 Mechanical Characteristics ................................................................... 74
8.1 Thermal Considerations ..................................................................................74
8.2 Package Drawings ...........................................................................................75
8.3 Soldering Profile ..............................................................................................78
9 Ordering Information ............................................................................. 79
10 Errata ....................................................................................................... 80
10.1 Rev. C ..............................................................................................................80
10.2 Rev. B ..............................................................................................................82
10.3 Rev. A ..............................................................................................................86
11 Datasheet Revision History .................................................................. 93
11.1 Rev. B 01/2012 .............................................................................................93
11.2 Rev. A 12/2011 .............................................................................................93
Table of Contents....................................................................................... i
ii
32145BS01/2012
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32145BS01/2012
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