ASX340AT: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Features
1/4-Inch Color CMOS NTSC/PAL Digital Image
SOC with Overlay Processor
ASX340AT Datasheet, Rev. H
For the latest datasheet, please visit www.onsemi.com
Features Table 1: Key Parameters
Low-power CMOS image sensor with integrated Parameter Typical Value
image flow processor (IFP) and video encoder Pixel size
and type 5.6 m x 5.6 m active pinned-
1/4-inch optical format, VGA resolution (640H x photodiode with high-sensitivity
480V ) Sensor clear pixels mode for low-light conditions
728H x 560V (includes VGA active
2x upscaling zoom and pan control NTSC output pixels, demosaic and lens alignment
40 additional columns and 36 additional rows to PAL output pixels)
Optical area 720H x 487V
compensate for lens alignment tolerances (clear pixels) 720H x 576V
Option to use single 2.8 V power supply with off-chip Optical format
Frame rate 4.077 mm x 3.136 mm
bypass transistor Sensor scan mode
Overlay generator for dynamic bitmap overlay Color filter array -inch
Integrated video encoder for NTSC/PAL with overlay Chief ray angle (CRA) 50/60 fields/sec
Shutter type Progressive scan
capability and 10-bit I-DAC RGB standard Bayer
Integrated microcontroller for flexibility Automatic Functions 0
On-chip image flow processor performs Electronic rolling shutter (ERS)
Programmable Exposure, white balance, black level
sophisticated processing, such as color recovery and Controls offset correction, flicker detection and
correction, sharpening, gamma, lens shading avoidance, color saturation control,
correction, on-the-fly defect correction, auto white on the-fly defect correction, aperture
balancing, and auto exposure correction
Auto black-level calibration Exposure, white balance, horizontal
10-bit, on-chip analog-to-digital converter (ADC) and vertical blanking, color,
Internal master clock generated by on-chip phase- sharpness, gamma correction, lens
locked loop (PLL) shading correction, horizontal and
Two-wire serial programming interface vertical image flip, zoom, windowing,
Interface to low-cost EEPROM and Flash through SPI sampling rates, GPIO control
bus
High-level host command interface Key parameters are continued on next page.
Stand-alone operation support See "New Features" on page 3.
Comprehensive tool support for overlay generation See "Ordering Information" on page 3
and lens correction setup
Development system with DevWare
Applications
Automotive rear view camera and side mirror
Blind spot and surround view
ASX340AT/D Rev. H, 8/15 EN 1 Semiconductor Components Industries, LLC 2015,
ASX340AT: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Applications
Table 2: Key Parameters (continued)
Parameter Typical Value
Overlay Support Utilizes SPI interface to load overlay data from external flash/EEPROM memory with the
following features:
Windowing Available in Analog output and BT656 Digital output
Analog gain range Overlay Size 360 x 480 pixel rendered into 720 x 480 (NTSC) or 720 x 576 (PAL)
ADC Up to four (4) overlays may be blended simultaneously
Output interface Selectable readout: Rotating order user-selected
Output data formats1 Dynamic scenes by loading pre-rendered frames from external memory
Palette of 32 colors out of 64,000
Data rate 8 colors per bitmap
Blend factor dynamically-programmable for smooth transitions
Control interface Fast update rate of up to 30 fps
Input clock for PLL Every bitmap object has independent x/y position
SPI Clock Frequencies Statistic Engine to calibrate optical alignment
Number Generator
Supply voltage Programmable to any size
0.516x
Power Analog output only 10-bit, on-chip
Analog composite video out, single-ended or differential; 8-, 10-bit parallel digital output
consumption Digital output only Digital: Raw Bayer 8-,10-bit, CCIR656, 565RGB, 555RGB, 444RGB
Parallel: 27 MHz Pixel clock
Package NTSC: 60 fields/sec
PAL: 50 fields/sec
Ambient temperature Two-wire I/F for register interface plus high-level command exchange. SPI port to interface to
external memory to load overlay data, register settings, or firmware extensions.
Dark Current 27 MHz
1.6875 18 MHz, programmable
Fixed pattern Column Analog: 2.8V 5%
Core: 1.8 V 5% (2.8V 5% power supply with off-chip bypass transistor generates a
noise Row 1.70 - 1.95 V core voltage supply, which is acceptable for performance.)
IO: 2.8 V 5%
Responsivity Full resolution at 60 fps: 291 mW
Full resolution at 60 fps: 192 mW
Signal to noise ratio (S/N) 63-BGA, 7.5 mm x 7.5 mm, 0.65mm pin pitch
Operating: -40 C to 105 C
Pixel dynamic range Functional: -40 C to + 85 C
Storage: -50C to + 150C
< 200 e/s at 60 C with a gain of 1
<2%
<2%
16.5 V/lux-s at 550 nm
46 dB
87 dB
ASX340AT/D Rev. H, 8/15 EN 2 Semiconductor Components Industries, LLC,2015.
ASX340AT: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
New Features
New Features
Temperature sensor for dynamic feedback and sensor control
Automatic 50Hz/60Hz flicker detection
2x upscaling zoom and pan/tilt control
Independent control of colorburst parameters in the NTSC/PAL encoder
Horizontal field of view adjustment between 700 and 720 pixels on the analog output
Option to use single 2.8V power supply with off-chip bypass transistor
SPI EEPROM support for lower cost system design.
Ordering Information
Table 3: Available Part Numbers
Part Number Product Description Orderable Product Attribute Description
ASX340AT2C00XPED0-DPBR Rev2, Color, 0deg CRA, iBGA Package Drypack, Protective Film, Anti-Reflective Glass
ASX340AT2C00XPED0-DRBR Rev2, Color, 0deg CRA, iBGA Package Drypack, Anti-Reflective Glass
ASX340AT2C00XPED0-TPBR Rev2, Color, 0deg CRA, iBGA Package Tape & Reel, Protective Film, Anti-Reflective Glass
ASX340AT2C00XPED0-TRBR Rev2, Color, 0deg CRA, iBGA Package Tape & Reel, Anti-Reflective Glass
ASX340AT2C00XPEDD3-GEVK Rev2, Color, Demo Kit
ASX340AT2C00XPEDH3-GEVB Rev2, Color, Head Board Drypack, Protective Film, Anti-Reflective Glass
ASX340AT3C00XPED0-DPBR Rev3, Color, 0deg CRA, iBGA Package Drypack, Anti-Reflective Glass
ASX340AT3C00XPED0-DRBR Rev3, Color, 0deg CRA, iBGA Package Tape & Reel, Protective Film, Anti-Reflective Glass
ASX340AT3C00XPED0-TPBR Rev3, Color, 0deg CRA, iBGA Package Tape & Reel, Anti-Reflective Glass
ASX340AT3C00XPED0-TRBR Rev3, Color, 0deg CRA, iBGA Package
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full
description of the naming convention used for image sensors. For reference documenta-
tion, including information on evaluation kits, please visit our web site at
www.onsemi.com.
ASX340AT/D Rev. H, 8/15 EN 3 Semiconductor Components Industries, LLC,2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
New Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pin Descriptions and Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
SOC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Sensor Pixel Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
System Configuration and Usage Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Multicamera Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
External Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Slave Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Overlay Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
NVM Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Overlay Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Overlay Character Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Modes and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
ASX340AT/D Rev. H, 8/15 EN 4 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
List of Figures
List of Figures
Figure 1: Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 2: System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 3: Using a Crystal Instead of an External Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 4: Sensor Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 5: Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 6: Image Capture Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 7: Pixel Color Pattern Detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 8: Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 9: Color Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 10: Color Bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 11: Gamma Correction Curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 12: Multicamera System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 13: External Signal Processing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 14: Power-Up Sequence Configuration Options Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 15: Interface Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 16: Host Command Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Figure 17: Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 18: Single Read from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 19: Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 20: Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 21: Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 22: Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 23: Overlay Data Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 24: Memory Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 25: Overlay Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 26: Internal Block Diagram Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 27: Example of Character Descriptor 0 Stored in ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 28: Full Character Set for Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 29: CCIR656 8-Bit Parallel Interface Format for 525/60 (625/50) Video Systems . . . . . . . . . . . . . . . . . . . .49
Figure 30: Typical CCIR656 Vertical Blanking Intervals for 525/60 Video System. . . . . . . . . . . . . . . . . . . . . . . . . .50
Figure 31: Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System. . . . . . . . . . . . . . . . . . . . . . . . . .51
Figure 32: Primary Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 33: Typical I/O Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 34: NTSC Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 35: Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 36: Digital Output I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 37: Slew Rate Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 38: Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 39: Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 40: Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Figure 41: FRAME_SYNC to FRAME_VALID/LINE_VALID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Figure 42: Reset to SPI Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Figure 43: Reset to Serial Access Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Figure 44: Reset to AE/AWB Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Figure 45: SPI Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Figure 46: Video Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 47: Equalizing Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 48: V Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 49: Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Figure 50: Quantum Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Figure 51: 63-Ball iBGA Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
ASX340AT/D Rev. H, 8/15 EN 5 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
List of Tables
List of Tables
Table 1: Key Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 2: Key Parameters (continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Table 3: Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Table 4: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 5: Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 6: Reset/Default State of Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 7: EIA Color Bars (NTSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 8: EBU Color Bars (PAL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 9: NTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 10: PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 11: YCbCr Output Data Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 12: RGB Ordering in Default Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 13: 2-Byte Bayer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 14: System Manager Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 15: Overlay Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 16: GPIO Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 17: Flash Manager Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 18: Sequencer Host Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 19: Patch Loader Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 20: Miscellaneous Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 21: Calibration Stats Host Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 22: Two-Wire Interface ID Address Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 23: Transfer Time Estimate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 24: Character Generator Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 25: Field, Vertical Blanking, EAV, and SAV States 525/60 Video System . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 26: Field, Vertical Blanking, EAV, and SAV States for 625/50 Video System . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 27: Output Data Ordering in DOUT RGB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 28: Output Data Ordering in Sensor Stand-Alone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 29: Parallel Digital Output I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 30: Slew Rate for PIXCLK and DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 31: Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 32: Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Table 33: Power Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 34: FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Table 35: RESET_BAR Delay Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 36: SPI Data Setup and Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 37: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Table 38: Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 39: Video DAC Electrical CharacteristicsSingle-Ended Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Table 40: Video DAC Electrical CharacteristicsDifferential Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 41: Digital I/O Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Table 42: Power Consumption Condition 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 43: Power Consumption Condition 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Table 44: NTSC Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 45: Video Timing: Specification from Rec. ITU-R BT.470. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Table 46: Equalizing Pulse: Specification from Rec. ITU-R BT.470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Table 47: V Pulse: Specification from Rec. ITU-R BT.470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 48: Two-Wire Serial Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
ASX340AT/D Rev. H, 8/15 EN 6 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
General Description
General Description
The ON Semiconductor ASX340AT is a VGA-format, single-chip CMOS active-pixel
digital image sensor for automotive applications. It captures high-quality color images
at VGA resolution and outputs NTSC or PAL interlaced composite video.
The VGA CMOS image sensor features ON Semiconductor's breakthrough low-noise
imaging technology that achieves superior image quality (based on signal-to-noise ratio
and low-light sensitivity) while maintaining the inherent size, cost, low power, and inte-
gration advantages of ON Semiconductor's advanced active pixel CMOS process tech-
nology.
The ASX340AT is a complete camera-on-a-chip. It incorporates sophisticated camera
functions on-chip and is programmable through a simple two-wire serial interface or by
an attached SPI EEPROM or Flash memory that contains setup information that may be
loaded automatically at startup.
The ASX340AT performs sophisticated processing functions including color recovery,
color correction, sharpening, programmable gamma correction, auto black reference
clamping, auto exposure, 50Hz/60Hz flicker detection and avoidance, lens shading
correction, auto white balance (AWB), and on-the-fly defect identification and correc-
tion.
The ASX340AT outputs interlaced-scan images at 60 or 50 fields per second, supporting
both NTSC and PAL video formats. The image data can be output on one or two output
ports:
Composite analog video (single-ended and differential output support)
Parallel 8-, 10-bit digital
Architecture
Internal Block Diagram
Figure 1: Internal Block Diagram
SPI Two-Wire I/F 2. 8V 1 .8 V
4 2 Camera Control
SPI & 2W I/F AWB
Interface AE
640 x 480 Active Array Image Flow Processor Overlay
Graphics
" VGA ROI 10 8
@ 60 frames per sec.
Color & Gamma Correction Generation BT -656
Color Space Conversion
Edge Enhancement
VideoEncoder NTSC /
DAC PAL
ASX340AT/D Rev. H, 8/15 EN 7 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Architecture
System Block Diagram
The system block diagram will depend on the application. The system block diagram in
Figure 2 shows all components; optional peripheral components are highlighted.
Control information will be received by a microcontroller through the automotive bus to
communicate with the ASX340AT through its two-wire serial bus. Optional components
will vary by application.
Figure 2: System Block Diagram
18 pF - NPO EXTCLK
27.000 MHz
XTAL
18 pF - NPO RESET_BAR
FRAME _SYNC
System Bus C 2WIRE I/F SPI Serial Data
2.8V EEPROM/Flash
2.35k DAC _POS Composite
DAC _REF DAC _NEG 1KB - 16MB Video
LP Filter PAL /NTSC
VDD_DAC (2.8V) 37.5
VDD_PLL (2.8.V)
VDD_IO (2..8V) Optional
VAA _PIX (2.8V)
VAA (2.8V) CCIR 656/
VDD (1.8V ) GPO
VREG_BASE
DOUT[7:0]
DOUT_LSB0, 1
PIXCLK
FRAME_VALID
LINE_VALID
ASX340AT/D Rev. H, 8/15 EN 8 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Architecture
Crystal Usage
As an alternative to using an external oscillator, a fundamental 27 MHz crystal may be
connected between EXTCLK and XTAL. Two small loading capacitors of 1022 pF of NPO
dielectric should be added as shown in Figure 3.
ON Semiconductor does not recommend using the crystal option for applications above
85C. A crystal oscillator with temperature compensation is recommended.
Figure 3: Using a Crystal Instead of an External Oscillator
18 pF - NPO Sensor
27.000 MHz EXTCLK
XTAL
18pF - NPO
Note: Value of load capacitor is crystal dependent. Crystal with small load capacitor is recommended.
ASX340AT/D Rev. H, 8/15 EN 9 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Pin Descriptions and Assignments
Table 4: Pin Descriptions
Pin Number Pin Name Type Description
EXTCLK
A2 Input Clock and Reset
XTAL Output
B1 RESET_BAR Input Master input clock (27MHz): This can either be a square-wave generated from an
D2 Input oscillator (in which case the XTAL input must be left unconnected) or connected
FRAME_SYNC directly to a crystal.
E1
SCLK If EXTCLK is connected to one pin of a crystal, this signal is connected to the other
F1 SDATA pin; otherwise this signal must be left unconnected.
F2 SADDR
E2 Asynchronous active-low reset: When asserted, the device will return all interfaces
SPI_SCLK to their reset state. When released, the device will initiate the boot sequence. This
D4 SPI_SDI signal has an internal pull-up resistor.
E4 SPI_SDO
H3 SPI_CS_N This input can be used to set the output timing of the ASX340AT to a fixed point in
H2 FRAME_VALID the frame.
LINE_VALID The input buffer associated with this input is permanently enabled. This signal
F7 PIXCLK must be connected to GND if not used.
G7 DOUT[7:0]
E6 Register Interface
F8, D6, D7, DOUT_LSB1
C6, C7, B6, DOUT_LSB0 Input These two signals implement the serial communications protocol for access to the
B7, A6
B3 Input/Output internal registers and variables.
C2
Input This signal controls the device ID that will respond to serial communication
commands.
Two-wire serial interface device ID selection:
0: 0x90
1: 0xBA
Output SPI Interface
Input Clock output for interfacing to an external SPI memory such as Flash/EEPROM.
Output Tri-state when RESET_BAR is asserted.
Output Data in from SPI device. This signal has an internal pull-up resistor.
Data out to SPI device. Tri-state when RESET_BAR is asserted.
Chip selects to SPI device. Tri-state when RESET_BAR is asserted.
(Parallel) Pixel Data Output
Input/Output Pixel data from the ASX340AT can be routed out on this interface and processed
Input/Output externally.
Output To save power, these signals are driven to a constant logic level unless the parallel
Output pixel data output or alternate (GPIO) function is enabled for these pins.
This interface is disabled by default.
The slew rate of these outputs is programmable.
These signals can also be used as general purpose input/outputs.
Input/Output When the sensor core is running in bypass mode, it will generate 10 bits of output
Input/Output data per pixel. These two pins make the two LSB of pixel data available externally.
Leave DOUT_LSB1and DOUT_LSB0 unconnected if not used. To save power, these
signals are driven to a constant logic level unless the sensor core is running in
bypass mode or the alternate function is enabled for these pins. The slew rate of
these outputs is programmable.
ASX340AT/D Rev. H, 8/15 EN 10 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Table 4: Pin Descriptions (continued)
Pin Number Pin Name Type Description
F5 DAC_POS Output Composite Video Output
G5 DAC_NEG Output Positive video DAC output in differential mode.
A4 DAC_REF Output Video DAC output in single-ended mode. This interface is enabled by default using
NTSC/PAL signaling. For applications where composite video output is not
D3 TDI required, the video DAC can be placed in a power-down state under software
G2 TDO control.
F3 TMS
C3 TCK Negative video DAC output in differential mode.
C4 TRST_N
G6 ATEST1 External reference resistor for the video DAC.
F6 ATEST2
Input Manufacturing Test Interface
C1 GPIO12 Output JTAG Test pin (Reserved for Test Mode)
A3 GPIO13 Input JTAG Test pin (Reserved for Test Mode)
Input JTAG Test pin (Reserved for Test Mode)
G4 VREG_BASE Input JTAG Test pin (Reserved for Test Mode)
A5, A7, D8, VDD Input Connect to GND.
E7, G1, G3 Input Analog test input. Connect to GND in normal operation.
B2, B8, C8, VDD_IO Analog test input. Connect to GND in normal operation.
E3, E8, G8,
VDD_DAC GPIO
H8 VDD_PLL Input/Output Dedicated general-purpose input/output pin.
H5 Input/Output Dedicated general-purpose input/output pin.
A8 VAA
B4, H6 VAA_PIX Supply Power
H7 Reserved Supply Voltage regulator control. Leave floating if not used.
H4 Supply for VDD core: 1.8V nominal. Can be connected to the output of the
B5, C5, D1, DGND Supply transistor of the off-chip bypass transistor or an external 1.8V power supply.
D5, H1 AGND
E5, F4 Supply for digital IOs: 2.8V nominal.
Supply Supply for video DAC: 2.8V nominal.
Supply Supply for PLL: 2.8V nominal.
Supply Analog power: 2.8V nominal.
Supply Analog pixel array power: 2.8V nominal. Must be at same voltage potential as VAA.
Leave floating for normal operation.
Supply
Digital ground.
Supply
Analog ground.
ASX340AT/D Rev. H, 8/15 EN 11 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Pin Assignments
Pin 1 is not populated with a ball. That allows the device to be identified by an additional
marking.
Table 5: Pin Assignments
1 2 3 4 5 6 7 8
EXTCLK GPIO13 DAC_REF VDD DOUT0 VDD VDD_PLL
A VDD_IO DOUT_LSB1 VAA GND DOUT2 DOUT1 VDD_IO
DOUT_LSB0 TCK TRST_N GND DOUT4 DOUT3 VDD_IO
B XTAL RESET_BAR TDI SPI_SCLK GND DOUT6 DOUT5 VDD
SADDR VDD_IO SPI_SDI AGND PIXCLK VDD VDD_IO
C GPIO12 SDATA TMS AGND DAC_POS ATEST2 FRAME_VALID DOUT7
VDD VREG_BASE DAC_NEG ATEST1 LINE_VALID VDD_IO
D GND TDO SPI_SDO Reserved VDD_DAC VAA VAA_PIX VDD_IO
SPI_CS_N
E FRAME_SYNC
F SCLK
G VDD
H GND
Table 6: Reset/Default State of Interfaces
Name Reset State Default State Notes
EXTCLK Clock running or stopped Clock running
Input
XTAL N/A N/A
RESET_BAR Asserted De-asserted Input
SCLK N/A N/A Input
SDATA High impedance High impedance Input. Must always be driven to high via
a pull-up resistor in the range of 1.5 to 4.7 k.
SADDR N/A N/A
Input/Output. Must always be driven to high
SPI_SCLK High impedance. Driven, logic 0 via
SPI_SDI Internal pull-up enabled. Internal pull-up enabled a pull-up resistor in the range of 1.5 to 4.7 k.
SPI_SDO High impedance Driven, logic 0 Input. Must be permanently tied to VDD_IO or
SPI_CS_N High impedance Driven, logic 1 GND.
FRAME_VALID High impedance High impedance
LINE_VALID Output. Output enable is R0x0032[13].
Input. Internal pull-up is permanently
enabled.
Output enable is R0x0032[13].
Output enable is R0x0032[13].
Input/Output. This interface is disabled by
default. Input buffers (used for GPIO function)
powered down by default, so these pins can
be left unconnected (floating). After reset,
these pins are powered up, sampled, then
powered down again as part of the auto-
configuration mechanism. See Note 2.
ASX340AT/D Rev. H, 8/15 EN 12 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Pin Descriptions and Assignments
Table 6: Reset/Default State of Interfaces (continued)
Name Reset State Default State Notes
PIXCLK High impedance Driven, logic 0
DOUT7 Output. This interface disabled by default.
DOUT6 See Note 1.
DOUT5
DOUT4 High impedance High impedance Input/Output. This interface disabled by
DOUT3 High impedance High impedance default. Input buffers (used for GPIO function)
DOUT2 powered down by default, so these pins can
DOUT1 High impedance Driven be left unconnected (floating). After reset,
DOUT0 these pins are powered-up, sampled, then
DOUT_LSB1 powered down again as part of the auto-
DOUT_LSB0 configuration mechanism.
DAC_POS Output. Interface disabled by hardware reset
DAC_NEG and enabled by default when the device starts
DAC_REF streaming.
TDI Internal pull-up enabled Internal pull-up enabled Input. Internal pull-up means that this pin can
High impedance High impedance be left unconnected (floating).
TDO
Internal pull-up enabled Internal pull-up enabled Output. Driven only during appropriate parts
TMS Internal pull-up enabled Internal pull-up enabled of the JTAG shifter sequence.
TCK N/A N/A Input. Internal pull-up means that this pin can
be left unconnected (floating).
TRST_N N/A N/A
High impedance High impedance Input. Internal pull-up means that this pin can
FRAME_SYNC be left unconnected (floating).
High impedance High impedance
GPIO12 Input. Must always be driven to a valid logic
N/A N/A level. Must be driven to GND for normal
GPIO13 N/A N/A operation.
ATEST1 Input. Must always be driven to a valid logic
ATEST2 level. Must be driven to GND if not used.
Input/Output. This interface disabled by
default. Input buffers (used for GPIO function)
powered down by default, so these pins can
be left unconnected (floating)
Input/Output. This interface disabled by
default. Input buffers (used for GPIO function)
powered down by default, so these pins can
be left unconnected (floating).
Must be driven to GND for normal operation.
Must be driven to GND for normal operation.
Notes: 1. The reason for defining the default state as logic 0 rather than high impedance is this: when wired
in a system (for example, on ON Semiconductor's demo boards), these outputs will be connected,
and the inputs to which they are connected will want to see a valid logic level. No current drain
should result from driving these to a valid logic level (unless there is a pull-up at the system level).
2. These pads have their input circuitry powered down, but they are not output-enabled. Therefore,
they can be left floating but they will not drive a valid logic level to an attached device.
ASX340AT/D Rev. H, 8/15 EN 13 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
SOC Description
SOC Description
Detailed Architecture Overview
Sensor Core
The sensor consists of a pixel array, an analog readout chain, a 10-bit ADC with programmable
gain and black offset, and timing and control as illustrated in Figure 4.
Figure 4: Sensor Core Block Diagram
Active Pixel Control Register Communication
Sensor (APS) Timing and Control Bus
Array to IFP
Clock
Sync
Signals
Analog Processing ADC 10-Bit Data
to IFP
Pixel Array Structure
The sensor core pixel array is configured as 728 columns by 560 rows, as shown in
Figure 5.
Figure 5: Pixel Array Description
(40, 36) (0, 0)
lens alignment rows Pixel logical address = (0, 0)
demosaic rows
lens alignment columns
demosaic columns
demosaic columns
lens alignment columns
Active pixel array
640 x 480
Pixel logical address = (727, 559) demosaic rows
lens alignment rows
(687, 523)
(not to scale)
Black rows used internally for automatic black level adjustment are not addressed by
default, but can be read out in raw output mode via a register setting.
There are 728 columns by 560 rows of optically-active pixels (that is, clear pixels) that
include a pixel boundary around the VGA (640 x 480) image to avoid boundary effects
during color interpolation and correction. Among the 728 columns by 560 rows of clear
ASX340AT/D Rev. H, 8/15 EN 14 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
SOC Description
Figure 6: pixels, there are 36 lens alignment rows on the top and bottom, and 40 lens alignment
columns on the left and right; and there are 4 demosaic rows and 4 demosaic columns
on each side.
Figure 6 illustrates the process of capturing the image. The original scene is flipped and
mirrored by the sensor optics. Sensor readout starts at the lower right corner. The image
is presented in true orientation by the output display.
Image Capture Example
SCENE
(Front view)
OPTICS Process of Image Gathering and Image Display
IMAGE SENSOR IMAGE CAPTURE
(Rear view) Row by Row
Start Rasterization Start Readout
IMAGE RENDERING
DISPLAY
(Front view)
ASX340AT/D Rev. H, 8/15 EN 15 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Sensor Pixel Array
The active pixel array is 640 x 480 pixels. In addition, there are 72 rows and 80 columns
for lens alignment and 8 rows and 8 columns for demosaic.
Figure 7: Pixel Color Pattern Detail (top right corner)
Column Readout Direction
... Black Pixels
First Lens Alignment
Pixel
(64, 0)
GRGRGRG
Row BGBGBGB
Readout
Direction ... G R G R G R G
BGBGBGB
GRGRGRG
BGBGBGB
Output Data Format
The sensor core image data are read out in progressive scan order. Valid image data are
surrounded by horizontal and vertical blanking, shown in Figure 8.
For NTSC output, the horizontal size is stretched from 640 to 720 pixels. The vertical size
is 243 pixels per field; 240 image pixels and 3 dark pixels that are located at the bottom of
the image field.
For PAL output, the horizontal size is also stretched from 640 to 720 pixels. The vertical
size is 288 pixels per field.
ASX340AT/D Rev. H, 8/15 EN 16 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Figure 8: Spatial Illustration of Image Readout
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n 00 00 00 .................. 00 00 00
P2,0 P2,1 P2,2.....................................P2,n-1 P2,n 00 00 00 .................. 00 00 00
Valid Image Odd Field Horizontal
Blanking
Pm-2,0 Pm-2,1.....................................Pm-2,n-1 Pm-2,n 00 00 00 .................. 00 00 00
Pm,0 Pm,1.....................................Pm,n-1 Pm,n 00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
Vertical Even Blanking Vertical/Horizontal
Blanking
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
P1,0 P1,1 P1,2.....................................P1,n-1 P1,n 00 00 00 .................. 00 00 00
P3,0 P3,1 P3,2.....................................P3,n-1 P3,n 00 00 00 .................. 00 00 00
Valid Image Even Field Horizontal
Blanking
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00
Pm+1,0 Pm+1,1..................................Pm+1,n-1 Pm+1,n 00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
Vertical Odd Blanking Vertical/Horizontal
Blanking
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
00 00 00 ..................................... 00 00 00 00 00 00 .................. 00 00 00
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Image Flow Processor
Image and color processing in the ASX340AT are implemented as an image flow
processor (IFP) coded in hardware logic. During normal operation, the embedded
microcontroller will automatically adjust the operation parameters. The IFP is broken
down into different sections, as outlined in Figure 9.
Figure 9: Color Pipeline
RAW 10
Pixel Array
ADC
IFP Raw Data
MUX
Test Pattern
Generator
Digital Gain Control Black
Lens Shading Level
Correction Subtraction
Defect Correction,
Noise Reduction,
Color Interpolation
Statistics 8-bit
Engine RGB
10/12-Bit RGB to YUV
RGB
8-bit
Color Correction YUV
Aperture Color Kill
Correction
Output
Gamma Formatting
Correction YUV to RGB
(12-to-8 Lookup)
Overlay Control
Output Analog Output Mux Parallel Output Mux
Interface
NTSC/PAL Parallel
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Test Patterns
During normal operation of the ASX340AT, a stream of raw image data from the sensor
core is continuously fed into the color pipeline. For test purposes, this stream can be
replaced with a fixed image generated by a special test module in the pipeline. The
module provides a selection of test patterns sufficient for basic testing of the pipeline.
NTSC/PAL Test Pattern Generation
There is a built-in standard EIA (NTSC) and EBU (PAL) color bars to support hue and
color saturation characterization. Each pattern consists of seven color bars (white,
yellow, cyan, green, magenta, red, and blue). The Y, Cb and Cr values for each bar are
detailed in Tables 7 and 8.
Figure 10: Color Bars
Table 7: EIA Color Bars (NTSC)
Nominal Range White Yellow Cyan Green Magenta Red Blue
Y 16 to 235 180 162 131 112 84 65 35
Cb 16 to 240 128 44 156 72 184 100 212
Cr 16 to 240 128 142 44 58 198 212 114
Table 8: EBU Color Bars (PAL)
Nominal Range White Yellow Cyan Green Magenta Red Blue
Y 16 to 235 235 162 131 112 84 65 35
Cb 16 to 240 128 44 156 72 184 100 212
Cr 16 to 240 128 142 44 58 198 212 114
CCIR-656 Format
The color bar data is encoded in 656 data streams. The duration of the blanking and
active video periods of the generated 656 data are summarized in Tables 9 and 10.
Table 9: NTSC
Line Numbers Field Description
1-3 2 Blanking
4-19 1 Blanking
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Sensor Pixel Array
Table 9: NTSC (continued)
Line Numbers Field Description
20-263 1 Active video
264-265 1 Blanking
266-282 2 Blanking
283-525 2 Active Video
Table 10: PAL
Line Numbers Field Description
1-22 1 Blanking
1 Active video
23-310 1 Blanking
311-312 2 Blanking
313-335 2 Active video
336-623 2 Blanking
624-625
Black Level Subtraction and Digital Gain
Image stream processing starts with black level subtraction and multiplication of all
pixel values by a programmable digital gain. Both operations can be independently set
to separate values for each color channel (R, Gr., Gb, B). Independent color channel
digital gain can be adjusted with registers. Independent color channel black level adjust-
ments can also be made. If the black level subtraction produces a negative result for a
particular pixel, the value of this pixel is set to 0.
Positional Gain Adjustments (PGA)
Lenses tend to produce images whose brightness is significantly attenuated near the
edges. There are also other factors causing fixed pattern signal gradients in images
captured by image sensors. The cumulative result of all these factors is known as image
shading. The ASX340AT has an embedded shading correction module that can be
programmed to counter the shading effects on each individual R, Gb, Gr., and B color
signal.
The Correction Function
The correction functions can then be applied to each pixel value to equalize the
response across the image as follows:
Pcorrected(row,col)=Psensor(row,col)*f(row,col) (EQ 1)
where P is the pixel values and f is the color dependent correction functions for each
color channel.
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Sensor Pixel Array
Color Interpolation
In the raw data stream fed by the sensor core to the IFP, each pixel is represented by a
10-bit integer number, which can be considered proportional to the pixel's response to a
one-color light stimulus, red, green, or blue, depending on the pixel's position under the
color filter array. Initial data processing steps, up to and including the defect correction,
preserve the one-color-per-pixel nature of the data stream, but after the defect correc-
tion it must be converted to a three-colors-per-pixel stream appropriate for standard
color processing. The conversion is done by an edge-sensitive color interpolation
module. The module pads the incomplete color information available for each pixel
with information extracted from an appropriate set of neighboring pixels. The algorithm
used to select this set and extract the information seeks the best compromise between
preserving edges and filtering out high frequency noise in flat field areas. The edge
threshold can be set through register settings.
Color Correction and Aperture Correction
To achieve good color fidelity of the IFP output, interpolated RGB values of all pixels are
subjected to color correction. The IFP multiplies each vector of three pixel colors by a
3 x 3 color correction matrix. The three components of the resulting color vector are all
sums of three 10-bit numbers. Since such sums can have up to 12 significant bits, the bit
width of the image data stream is widened to 12 bits per color (36 bits per pixel). The
color correction matrix can be either programmed by the user or automatically selected
by the auto white balance (AWB) algorithm implemented in the IFP. Color correction
should ideally produce output colors that are corrected for the spectral sensitivity and
color crosstalk characteristics of the image sensor. The optimal values of the color
correction matrix elements depend on those sensor characteristics and on the spectrum
of light incident on the sensor. The color correction parameters can be adjusted through
register settings.
To increase image sharpness, a programmable 2D aperture correction (sharpening filter)
is applied to color-corrected image data. The gain and threshold for 2D correction can
be defined through register settings.
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Sensor Pixel Array
Gamma Correction
The ASX340AT includes a block for gamma correction that can adjust its shape based on
brightness to enhance the performance under certain lighting conditions. Two custom
gamma correction tables may be uploaded corresponding to a brighter lighting condi-
tion and a darker lighting condition. At power-up, the IFP loads the two tables with
default values. The final gamma correction table used depends on the brightness of the
scene and takes the form of an interpolated version of the two tables.
The gamma correction curve (as shown in Figure 11) is implemented as a piecewise
linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit
output. The abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280,
1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. The 8-bit ordinates
are programmable through registers.
Figure 11: Gamma Correction Curve
RGB to YUV Conversion
For further processing, the data is converted from RGB color space to YUV color space.
Color Kill
To remove high-or low-light color artifacts, a color kill circuit is included. It affects only
pixels whose luminance exceeds a certain preprogrammed threshold. The U and V
values of those pixels are attenuated proportionally to the difference between their lumi-
nance and the threshold.
YUV Color Filter
As an optional processing step, noise suppression by one-dimensional low-pass filtering
of Y and/or UV signals is possible. A 3- or 5-tap filter can be selected for each signal.
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Sensor Pixel Array
YUV-to-RGB/YUV Conversion and Output Formatting
The YUV data stream emerging from the colorpipe can either exit the color pipeline as-is
or be converted before exit to an alternative YUV or RGB data format.
Output Format and Timing
YUV/RGB Data Ordering
The ASX340AT supports swapping YCbCr mode, as illustrated in Table 11.
Table 11: YCbCr Output Data Ordering
Mode Data Sequence
Default (no swap) Cbi Yi Cri Yi+1
Swapped CbCr
Swapped YC Cri Yi Cbi Yi+1
Swapped CbCr, YC Yi Cbi Yi+1 Cri
Yi Cri Yi+1 Cbi
The RGB output data ordering in default mode is shown in Table 12. The odd and even
bytes are swapped when luma/chroma swap is enabled. R and B channels are bit-wise
swapped when chroma swap is enabled.
Table 12: RGB Ordering in Default Mode
Mode (Swap Disabled) Byte D7D6D5D4D3D2D1D0
565RGB
555RGB Odd R7R6R5R4R3G7G6G5
444xRGB Even G4G3G2B7B6B5B4B3
x444RGB Odd 0 R7R6R5R4R3G7G6
Even G5G4G3B7B6B5B4B3
Odd R7R6R5R4G7G6G5G4
Even
Odd B7B6B5B4 0 0 0 0
Even 0 0 0 0 R7R6R5R4
G7G6G5G4B7B6B5B4
Uncompressed 10-Bit Bypass Output
Raw 10-bit Bayer data from the sensor core can be output in bypass mode in two ways:
Using 8 data output signals (DOUT[7:0]) and GPIO[1:0]. The GPIO signals are the least
significant 2 bits of data.
Using only 8 signals (DOUT[7:0]) and a special 8 + 2 data format, shown in Table 13.
Table 13: 2-Byte Bayer Format
Byte Bits Used Bit Sequence
Odd bytes 8 data bits
Even bytes 2 data bits + 6 unused bits D9D8D7D6D5D4D3D2
0 0 0 0 0 0 D1D0
Readout Formats
Progressive format is used for raw Bayer output.
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Sensor Pixel Array
Output Formats
ITU-R BT.656 and RGB Output
TheASX340AT can output processed video as a standard ITU-R BT.656 (CCIR656) stream,
an RGB stream, or as unprocessed Bayer data. The ITU-R BT.656 stream contains YCbCr
4:2:2 data with embedded synchronization codes. This output is typically suitable for
subsequent display by standard video equipment or JPEG/MPEG compression.
Colorpipe data (pre-lens correction and overlay) can also be output in YCbCr 4:2:2 and a
variety of RGB formats in 640 by 480 progressive format in conjunction with
LINE_VALID and FRAME_VALID.
The ASX340AT can be configured to output 16-bit RGB (565RGB), 15-bit RGB (555RGB),
and two types of 12-bit RGB (444RGB). Refer to Table 24 and Table 25 on page 50 for
details.
Bayer Output
Unprocessed Bayer data are generated when bypassing the IFP completely--that is, by
simply outputting the sensor Bayer stream as usual, using FRAME_VALID, LINE_VALID,
and PIXCLK to time the data. This mode is called sensor bypass mode.
Output Ports
Composite Video Output
The composite video output DAC is external-resistor-programmable and supports both
single-ended and differential output. The DAC is driven by the on-chip video encoder
output.
Parallel Output
Parallel output uses either 8-bit or 10-bit output. Eight-bit output is used for ITU-R
BT.656 and RGB output. Ten-bit output is used for raw Bayer output.
Zoom Support
The ASX340AT supports zoom x1 and x2 modes, in interlaced and progressive scan
modes. The progressive support is limited to the VGA at either 60 fps or 50 fps.
In the zoom x2 modes, the sensor is configured for QVGA (320 x 240), and the zoom x2
window can be configured to pan around the VGA window.
FOV Stretch Support
The ASX340AT supports the ability to control the active 'width' of the TV output line,
between 692 and 720 pixels. The hardware supports two margins, each a maximum of 14
pixels width, and has to be an even number of pixels.
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System Configuration and Usage Modes
System Configuration and Usage Modes
How a camera based on the ASX340AT will be configured depends on what features are
used. There are essentially three configuration modes for ASX340AT: Auto-Config Mode,
Flash-Config Mode, and Host-Config Mode. Refer to System Configuration and Usage
Modes in the Developer Guide document for details.
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Multicamera Support
Multicamera Support
Two or more ASX340AT sensors may be synchronized to a frame by asserting the
FRAME_SYNC signal. At that point, the sensor and video encoder will reset without
affecting any register settings. The ASX340AT may be triggered to be synchronized with
another ASX340AT or an external event.
Figure 12: Multicamera System Block Diagram
Decoder/DSP Dual Camera
CVBS ASX340 OSC Camera 1
CVBS
F_SYNC
System Bus
ASX340 Camera 2
F_SYNC
1
C
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External Signal Processing
External Signal Processing
An external signal processor can take data from ITU656 or raw Bayer output format and
post-process or compress the data in various formats.
Figure 13: External Signal Processing Block Diagram
27 MHz
EXTCLK Serial
SPI EEPROM/Flash
1KB to 16MB
VIDEO_P CVBS
VIDEO_N PAL/NTSC
DOUT [7:0] Signal processor
PIXCLK
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External Signal Processing
Device Configuration
After power is applied and the device is out of reset by de-asserting the RESET_BAR pin,
it will enter a boot sequence to configure its operating mode. There are essentially three
three configuration modes: Flash/EEPROM Config, Auto Config, and Host Config. Figure
14: "Power-Up Sequence Configuration Options Flow Chart," on page 29 contains
more details on the configuration options.
The SOC firmware supports a System Configuration phase at start-up. This consists of
five modes of execution:
1. Flash Detection
2. Flash-Config
3. Auto-Config
4. Host-Config
5. Change-Config (commences streaming - completes the System Configuration mode).
The System Configuration phase is entered immediately after the firmware initializes
following SOC power-up or reset. By default, the firmware first enters the Flash Detec-
tion mode.
The Flash Detection mode attempts to detect the presence of an SPI Flash or EEPROM
device:
If no device is detected, the firmware then samples the SPI_SDI pin state to determine
the next mode:
If SPI_SDI == 0 then it enters the Host-Config mode.
If SPI_SDI == 1 then it enters the Auto-Config mode.
If a device is detected, the firmware switches to the Flash-Config mode.
In the Flash-Config phase, the firmware interrogates the device to determine if it
contains valid configuration records:
If no records are detected, then the firmware enters the Auto-Config mode.
If records are detected, the firmware processes them. By default, when all Flash
records are processed the firmware switches to the Host-Config mode. However, the
records encoded into the Flash can optionally be used to instruct the firmware to
proceed to one of the other mode (auto-config/change-config).
The Auto-Config mode uses the FRAME_VALID, LINE_VALID, DOUT_LSB0 and
DOUT_LSB1 pins to configure the operation of the device, such as video format and
pedestal (refer to the Developer Guide for more details). After Auto-Config completes
the firmware switches to the Change-Config mode.
In the Host-Config mode, the firmware performs no configuration, and remains idle
waiting for configuration and commands from the host. The System Configuration
phase is effectively complete and the SOC will take no actions until the host issues
commands.
In the Change-Config mode, the firmware performs a 'Change-Config' operation. This
applies the current configuration settings to the SOC, and commences streaming. This
completes the System Configuration phase.
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External Signal Processing
Power Sequence
In power-up, refer to the power-up sequence in Figure 39: "Power Up Sequence," on
page 59.
In power down, refer to Figure 40: "Power Down Sequence," on page 60 for details.
Figure 14: Power-Up Sequence Configuration Options Flow Chart
Power Up/ RESET
EEPROM/Flash yes
device present?
no EEPROM/Flash
contents valid?
yes no
SPI _SDI = 0?
no Parse (:optional) Auto-Config
EEPROM/Flash Change-Config
Disable Auto-Config
Content
Wait for Host
Command (default)
Auto Configuration: Auto-Config
FRAME_VALID Wait for Host Host Config
LINE_VALID Command
DOUT _LSB 0
DOUT _LSB 1
Change Config Change-Config
Wait for Host
Command
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External Signal Processing
Supported NVM Devices
The ASX340AT supports a variety of SPI non-volatile memory (NVM) devices. Refer to
Flash/EEPROM Programming section in Developer Guide document for details.
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External Signal Processing
Host Command Interface
ON Semiconductor sensors and SOCs contain numerous registers that are accessed
through a two-wire interface with speeds up to 400 kHz.
The ASX340AT in addition to writing or reading straight to/from registers or firmware
variables, has a mechanism to write higher level commands, the Host Command Inter-
face (HCI). Once a command has been written through the HCI, it will be executed by
on-chip firmware and the results are reported back. In general, registers should not be
accessed with the exception of registers that are marked for "User Access."
EEPROM or Flash memory is also available to store commands for later execution.
Under DMA control, a command is written into the SOC and executed.
For a complete description of host commands, refer to the ASX340AT Host Command
Interface Specification.
Figure 15: Interface Structure
bit 15 14 0
command register
Addr 0x40 1 Host Command to FW
0 Response from FW
door bell
bit 15 Parameter 0 0
Addr 0xFC00 Parameter 7 cmd_handler_params_pool_0
Addr 0xFC02 cmd_handler_params_pool_1
Addr 0xFC04 cmd_handler_params_pool_2
Addr 0xFC06 cmd_handler_params_pool_3
Addr 0xFC08 cmd_handler_params_pool_4
Addr 0xFC0A cmd_handler_params_pool_5
Addr 0xFC0C cmd_handler_params_pool_6
Addr 0xFC0E cmd_handler_params_pool_7
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External Signal Processing
Host Command Process Flow
Figure 16: Host Command Process Flow
Issu e Wa it fo r a No
C o mma n d re sp o n se?
H o st co u ld in se rt a n
o p tio n a l d e la y here R e a d C o mma n d Ye s
re g ister
No H o st co u ld in se rt a n R e a d C o mma n d
D o o rb e ll o p tio n a l d e la y here re g iste r
No b it cle a r ?
No
Ye s
At th is p o in t D o o rb e ll b it
C o mma n d h a s C o mma n d R e g iste r cle a r?
p a ra me te rs?
co n ta in s re sp o n se co d e Ye s
Ye s
Write p a ra me te rs C o mma n d
to h a s response No
Pa ra me te r Po o l
parameters ?
Write co mma n d
to Ye s
C o mma n d re g iste r R e a d re sp o n se
p a ra me te rs fro m
Pa ra me te r Po o l
Done
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External Signal Processing
Command Flow
The host issues a command by writing (through a two-wire interface bus) to the
command register. All commands are encoded with bit 15 set, which automatically
generates the host command (doorbell) interrupt to the microprocessor.
Assuming initial conditions, the host first writes the command parameters (if any) to the
parameters pool (in the command handler's logical page), then writes the command to
command register. The firmware interrupt handler then signals the Command Handler
task to process the command.
Note: If the host wishes to determine the outcome of the command, it must poll the command
register waiting for the doorbell bit to be cleared. This indicates that the firmware
completed processing the command. When the doorbell bit is cleared, the contents of
the command register indicate the command's result status. If the command generated
response parameters, the host can now retrieve these from the parameters pool.
The host must not write to the parameters pool, nor issue another command, until
the previous command completes. This is true even if the host does not care about the
result of the previous command. Therefore, the host must always poll the command
register to determine the state of the doorbell bit, and ensure the bit is cleared before
issuing a command.
For a complete command list and further information consult the Host Command Inter-
face Specification.
An example of how (using DevWare) a command may be initiated in the form of a
"Preset" follows.
Issue the SYSMGR_SET_STATE Command
All DevWare presets supplied by ON Semiconductor poll and test the doorbell bit after
issuing the command. Therefore there is no need to check if the doorbell bit is clear
before issuing the next command.
# Set the desired next state in the parameters pool(SYS_STATE_ENTER_CON-
FIG_CHANGE)
REG= 0xFC00, 0x2800 // CMD_HANDLER_PARAMS_POOL_0
# Issue the HC_SYSMGR_SET_STATE command
REG= 0x0040, 0x8100 // COMMAND_REGISTER
# Wait for the FW to complete the command (clear the Doorbell bit)
POLL_FIELD= COMMAND_REGISTER, DOORBELL,!=0, DELAY=10, TIMEOUT=100
# Check the command was successful
ERROR_IF= COMMAND_REGISTER, HOST_COMMAND,!=0, "Set State command
failed",
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External Signal Processing
Summary of Host Commands
Table 14 on page 34 through Table 21 on page 36 show summaries of the host
commands. The commands are divided into the following sections:
System Manager
Overlay
GPIO
Flash Manager
Sequencer
Patch Loader
Miscellaneous
Calibration Stats
Following is a summary of the Host Interface commands. The description gives a quick
orientation. The "Type" column shows if it is an asynchronous or synchronous
command. For a complete list of all commands including parameters, consult the Host
Command Interface Specification document.
Table 14: System Manager Commands
System Manager Value Type Description
Host Command 0x8100 Synchronous Request the system enter a new state
0x8101 Synchronous Get the current state of the system
Set State
Get State
Table 15: Overlay Host Commands
Overlay Host Command Value Type Description
Enable Overlay 0x8200 Synchronous Enable or disable the overlay subsystem
Get Overlay State 0x8201 Synchronous Retrieve the state of the overlay subsystem
Set Calibration 0x8202 Synchronous Set the calibration offset
Set Bitmap Property 0x8203 Synchronous Set a property of a bitmap
Get Bitmap Property 0x8204 Synchronous Get a property of a bitmap
Set String Property 0x8205 Synchronous Set a property of a character string
Load Buffer 0x8206 Asynchronous Load an overlay buffer with a bitmap (from Flash)
Load Status 0x8207 Synchronous Retrieve status of an active load buffer operation
Write Buffer 0x8208 Synchronous Write directly to an overlay buffer
Read Buffer 0x8209 Synchronous Read directly from an overlay buffer
Enable Layer 0x820A Synchronous Enable or disable an overlay layer
Get Layer Status 0x820B Synchronous Retrieve the status of an overlay layer
Set String 0x820C Synchronous Set the character string
Get String 0x820D Synchronous Get the current character string
Load String 0x820E Asynchronous Load a character string (from Flash)
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External Signal Processing
Table 16: GPIO Host Commands
GPIO Host Command Value Type Description
Set GPIO Property 0x8400
Get GPIO Property 0x8401 Synchronous Set a property of one or more GPIO pins
Set GPO State 0x8402
Get GPIO State 0x8403 Synchronous Retrieve a property of a GPIO pin
Set GPI Association 0x8404
Get GPI Association 0x8405 Synchronous Set the state of a GPO pin or pins
Synchronous Get the state of a GPI pin or pins
Synchronous Associate a GPI pin state with a Command Sequence stored in SPI Flash
Synchronous Retrieve an GPIO pin association
Table 17: Flash Manager Host Commands
Flash Manager Value Type Description
Host Command 0x8500
0x8501 Asynchronous Request the Flash Manager access lock
Get Lock 0x8502
Lock Status 0x8503 Synchronous Retrieve the status of the access lock request
Release Lock 0x8504
Config 0x8505 Synchronous Release the Flash Manager access lock
Read 0x8506
Write 0x8507 Synchronous Configure the Flash Manager and underlying SPI Flash subsystem
Erase Block 0x8508
Erase Device 0x8509 Asynchronous Read data from the SPI Flash
Query Device 0x850A
Status Asynchronous Write data to the SPI Flash
Config Device
Asynchronous Erase a block of data from the SPI Flash
Asynchronous Erase the SPI Flash device
Asynchronous Query device-specific information
Synchronous Obtain status of current asynchronous operation
Synchronous Configure the attached SPI NVM device
Table 18: Sequencer Host Commands
Sequencer Host Value Type Description
Command 0x8606 Synchronous Refresh the automatic image processing algorithm configuration
0x8607 Synchronous Retrieve the status of the last Refresh operation
Refresh
Refresh Status
Table 19: Patch Loader Host Commands
Patch Loader Host Value Type Description
Command 0x8700 Asynchronous Load a patch from SPI Flash and automatically apply
0x8701 Synchronous Get status of an active Load Patch or Apply Patch request
Load Patch 0x8702 Asynchronous Apply a patch (already located in Patch RAM)
Status 0x8706 Synchronous Reserve RAM to contain a patch
Apply Patch
Reserve RAM
Table 20: Miscellaneous Host Commands
Miscellaneous Host Command Value Type Description
Invoke Command Seq 0x8900 Synchronous Invoke a sequence of commands stored in NVM
Config Command Seq Processor 0x8901 Synchronous Configures the Command Sequencer processor
Wait For Event 0x8902 Synchronous Wait for a system event to be signalled
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
External Signal Processing
Table 21: Calibration Stats Host Commands
Calibration Stats Host Value Type Description
Command 0x8B00 Asynchronous Start statistics gathering
0x8B01 Synchronous Read the results back
Control
Read
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Slave Two-Wire Serial Interface
The two-wire serial interface bus enables read/write access to control and status regis-
ters within the ASX340AT. This interface is designed to be compatible with the MIPI Alli-
ance Standard for Camera Serial Interface 2 (CSI-2) 1.0, which uses the electrical
characteristics and transfer protocols of the two-wire serial interface specification.
The interface protocol uses a master/slave model in which a master controls one or
more slave devices. The sensor acts as a slave device. The master generates a clock (SCLK)
that is an input to the sensor and used to synchronize transfers.
Data is transferred between the master and the slave on a bidirectional signal (SDATA).
SDATA is pulled up to VDD_IO off-chip by a pull-up resistor in the range of 1.5 to 4.7 k.
Protocol Data transfers on the two-wire serial interface bus are performed by a sequence of low-
level protocol elements, as follows:
Table 22: a start or restart condition
a slave address/data direction byte
a 16-bit register address
an acknowledge or a no-acknowledge bit
data bytes
a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with a
start condition, and the bus is released with a stop condition. Only the master can gener-
ate the start and stop conditions.
The SADDR pin is used to select between two different addresses in case of conflict with
another device. If SADDR is LOW, the slave address is 0x90; if SADDR is HIGH, the slave
address is 0xBA. See Table 22.
Two-Wire Interface ID Address Switching
SADDR Two-Wire Interface Address ID
0 0x90
1 0xBA
Start Condition
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a "repeated start" or "restart" condition.
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of
data is followed by an acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte and for message bytes.
One data bit is transferred during each SCLK clock period. SDATA can change when SCLK
is low and must be stable while SCLK is HIGH.
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Slave Two-Wire Serial Interface
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A "0" in bit [0] indicates a write, and a "1" indicates a read. The default
slave addresses used by the ASX340AT are 0x90 (write address) and 0x91 (read address).
Alternate slave addresses of 0xBA (write address) and 0xBB (read address) can be
selected by asserting the SADDR input signal.
Message Byte
Message bytes are used for sending register addresses and register write data to the slave
device and for retrieving register read data. The protocol used is outside the scope of the
two-wire serial interface specification.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl-
edge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is
LOW and must be stable while SCLK is HIGH.
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver does not drive SDATA low during
the SCLK clock period following a data transfer. A no-acknowledge bit is used to termi-
nate a read sequence.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Typical Operation
A typical READ or WRITE sequence begins by the master generating a start condition on
the bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a READ or a WRITE, where a "0"
indicates a WRITE and a "1" indicates a READ. If the address matches the address of the
slave device, the slave device acknowledges receipt of the address by generating an
acknowledge bit on the bus.
If the request was a WRITE, the master then transfers the 16-bit register address to which
a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave
sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master will then transfer the 16-bit data, as two 8-bit sequences and the
slave sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master stops writing by generating a (re)start or stop condition. If the
request was a READ, the master sends the 8-bit write slave address/data direction byte
and 16-bit register address, just as in the write request. The master then generates a
(re)start condition and the 8-bit read slave address/data direction byte, and clocks out
the register data, 8 bits at a time. The master generates an acknowledge bit after each
8-bit transfer. The data transfer is stopped when the master sends a no-acknowledge bit.
Single READ from Random Location
Figure 17 shows the typical READ cycle of the host to the ASX340AT. The first two bytes
sent by the host are an internal 16-bit register address. The following 2-byte READ cycle
sends the contents of the registers to host.
Figure 17: Single READ from Random Location
Previous RegAddress, N Reg Address, M M+1
S Slave Address 0 A Reg Address[15:8] A Reg Address[7:0] A Sr Slave Address 1A Read Data A Read Data A P
[15:8] [7:0]
S = start condition slave to master
P = stop condition master toslave
Sr = restart condition
A = acknowledge
A = no-acknowledge
Single READ from Current Location
Figure 18 shows the single READ cycle without writing the address. The internal address
will use the previous address value written to the register.
Figure 18: Single Read from Current Location
Previous Reg Address, N Reg Address, N+1 N+2
S Slave Address 1 A Read Data A Read Data P S Slave Address Read Data Read Data
[15:8] [7:0] A 1 A [15:8] A [7:0] A P
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Sequential READ, Start from Random Location
This sequence (Figure 19) starts in the same way as the single READ from random loca-
tion (Figure 17 on page 39). Instead of generating a no-acknowledge bit after the first
byte of data has been transferred, the master generates an acknowledge bit and
continues to perform byte READs until "L" bytes have been read.
Figure 19: Sequential READ, Start from Random Location
Previous Reg Address, N Reg Address, M M+1
A
S Slave Address 0 A Reg Address[15:8] A Reg Address[7:0] A Sr Slave Address 1 A Read Data
M+1 M+2 M+3 M+L-2 M+L-1 M+L
Read Data A Read Data A Read Data A Read Data A Read Data A Read Data A Read Data A Read Data A P
(15:8) (7:0) (15:8) (7:0) (15:8) (7:0) (15:8) (7:0)
Sequential READ, Start from Current Location
This sequence (Figure 20) starts in the same way as the single READ from current loca-
tion (Figure 18). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte reads until "L" bytes have been read.
Figure 20: Sequential READ, Start from Current Location
Previous Reg Address, N N+1 N+2 N+L-1 N+L
S Slave Address 1 A Re(a1d5D:8Ra) teaadADaReta(a7d:D0)ata A Re(a1d5D:8Ra) teaadADaReta(a7d:D0)ata A Re(a1d5D:8Ra)teaadADaReta(a7d:D0)ata A Re(a1d5D:8Ra)teaadADaReta(a7d:D0)ata A P
Single Write to Random Location
Figure 21 shows the typical WRITE cycle from the host to the ASX340AT.The first 2 bytes
indicate a 16-bit address of the internal registers with most-significant byte first. The
following 2 bytes indicate the 16-bit data.
Figure 21: Single WRITE to Random Location
Previous Reg Address, N RegAddress, M M+1
S Slave Address 0 A RegAddress[15:8] A RegAddress[7:0] A Write Data AP
A
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Slave Two-Wire Serial Interface
Sequential WRITE, Start at Random Location
This sequence (Figure 22) starts in the same way as the single WRITE to random location
(Figure 21). Instead of generating a no-acknowledge bit after the first byte of data has
been transferred, the master generates an acknowledge bit and continues to perform
byte writes until "L" bytes have been written. The WRITE is terminated by the master
generating a stop condition.
Figure 22: Sequential WRITE, Start at Random Location
Previous Reg Address, N Reg Address, M M+1
S Slave Address 0 A Reg Address[15:8] A Reg Address[7:0] A Write Data A
M+1 M+2 M+3 M+L-2 M+L-1 M+L
Write Data A Write Data A Wr(i1te5:DW8)atraiteADWatri(at7e:0D)ata AA Wr(i1te5:DW8a)traiteADWatri(at7e:0D)ata A Wr(i1te5:DW8a)traiteADWatri(at7e:0D)ata A P
(15:8) (7:0) A
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Capability
Overlay Capability
Figure 23 highlights the graphical overlay data flow of theASX340AT. The images are
separated to fit into 2 KB blocks of memory after compression.
Up to four overlays may be blended simultaneously
Overlay size 360 x 480 pixels rendered into a display area of 720 x 480 pixels (NTSC) or
720 x 576 (PAL)
Selectable readout: rotating order is user programmable
Dynamic movement through predefined overlay images
Palette of 32 colors out of 64,000 with eight colors per bitmap
Blend factors may be changed dynamically to achieve smooth transitions
The host commands allow a bitmap to be written piecemeal to a memory buffer through
the two-wire serial interface, and also through DMA direct from SPI Flash memory.
Multiple encoding passes may be required to fit an image into a 2KB block of memory;
alternatively, the image can be divided into two or more blocks to make the image fit.
Every graphic image may be positioned in the horizontal and vertical direction and
overlap with other graphic images.
The host may load an image at any time. Under control of DMA assist, data are trans-
ferred to the off-screen buffer in compressed form. This assures that no display data are
corrupted during the replenishment of the four active overlay buffers.
Figure 23: Overlay Data Flow
Flash Overlay buffers: 2KB each Decompress
Bitmaps - compressed Blend and Overlay
Off-screen
buffer
Note: These images are not actually rendered, but show conceptual objects and object blending.
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
NVM Partition
NVM Partition
The contents of the Flash/EEPROM memory partition logically into three blocks (see
Figure 24):
Memory for overlay data and descriptors
Memory for register settings, which may be loaded at boot-up
Firmware extensions or software patches; in addition to the on-chip firmware, exten-
sions reside in this block of memory
These blocks are not necessarily contiguous.
Figure 24: Memory Partitioning
Flash FFiixxedd-sSizize e FFiixxeedd-sSiziez e
PartFiltaisohning OOvveerrllaayyss-RRLLE E OOvverllaayyss- RRLLEE
Partitioning
1122-Bbyyttee HHeeaaddeerr
OOvevrelarylaDyata RRLLEE EEnnccooddeedd
Data 2DD2kaKBatyBtaate
Lens Shading
Correction
Parameter
AlAteltrenrantaeteReg.
Register Setting
SoftSw/aWrePaPtacthch
External Memory Speed Requirement
For a 2 KB block of overlay to be transferred within a frame time to achieve maximum
update rate, the SPI NVM must operate at a certain minimum speed.
Table 23: Transfer Time Estimate
Frame Time SPI Clock Transfer Time for 2 KB
33.3ms 4.5 MHz 1ms
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Adjustment
Overlay Adjustment
To ensure a correct position of the overlay to compensate for assembly deviation, the
overlay can be adjusted with assistance from the overlay statistics engine:
The overlay statistics engine supports a windowed 8-bin luma histogram, either row-
wise (vertical) or column-wise (horizontal).
The calibration statistics can be used to perform an automatic successive-approxima-
tion search of a cross-hair target within the scene.
On the first frame, the firmware performs a coarse horizontal search, followed by a
coarse vertical search in the second frame.
In subsequent frames, the firmware reduces the region-of-interest of the search to the
histogram bins containing the greatest accumulator values, thereby refining the
search.
The resultant row and column location of the cross-hair target can be used to assign a
calibration value to offset selected overlay graphic image positions within the output
image.
The calibration statistics patch also supports a manual mode, which allows the host
to access the raw accumulator values directly.
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Overlay Character Generator
Figure 25: Overlay Calibration
The position of the target will be used to determine the calibration value that shifts the
row and column position of adjustable overlay graphics.
The overlay calibration is intended to be applied on a device by device basis "in system,"
which means after the camera has been installed. ON Semiconductor provides basic
programming scripts that may reside in the SPI Flash memory to assist in this effort.
Overlay Character Generator
In addition to the four overlay layers, a fifth layer exists for a character generator overlay
string.
There are a total of:
16 alphanumeric characters available
22 characters maximum per line
16 x 32 pixels with 1-bit color depth
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Overlay Character Generator
Any update to the character generator string requires the string to be passed in its
entirety with the Host Command. Character strings have their own control properties
aside from the Overlay bitmap properties.
Figure 26: Internal Block Diagram Overlay
BT656
O verla y
Register Bus User Registers Layer3
Tim ing control Layer2
Data Bus Layer1
Layer0
D M A /C P U N um ber
G en e ra to r
ROM
BT656
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Character Generator
Character Generator
The character generator can be seen as the fifth top layer, but instead of getting the
source from RLE data in the memory buffers, it has 16 predefined characters stored in
ROM.
All the characters are 1-bit depth color and are sharing the same YCbCr look up table.
Figure 27: Example of Character Descriptor 0 Stored in ROM
ROM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x02 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x04 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0
0x06 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0
0x08 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
0x0a 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0
0x0c 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0
0x0e 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0
0x10 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0
0x12 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0
0x14 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0
0x16 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0
0x18 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0
0x1a 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0
0x1c 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0
0x1e 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0
0x20 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0
0x22 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0
0x24 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0
0x26 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0
0x28 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0
0x2a 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 0
0x2c 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0
0x2e 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 0
0x30 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0
0x32 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0
0x34 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
0x36 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0
0x38 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0
0x3a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x3c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x3e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
...
It can show a row of up to 22 characters of 16 x 32 pixels resolution (32 x 32 pixels when
blended with the BT 656 data).
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Overlay Character Generator
Character Generator Details
Table 24 shows the characters that can be generated.
Table 24: Character Generator Details
Item Quantity Description
16-bit character 22 Code for one of these characters: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /, (space), :, , (comma), (period)
1 bpp color 1 Depth of the bit map is 1 bpp
Note: It is the responsibility of the user to set up proper values in the character positioning to
fit them in the same row (that is one of the reasons that 22 is the maximum number of
characters).
No error is generated if the character row overruns the horizontal or vertical limits of
the frame.
Full Character Set for Overlay
Figure 28 shows all of the characters that can be generated by the ASX340AT.
Figure 28: Full Character Set for Overlay
0x0 0x4 0x8 0xC
0x1 0x5 0x9 0xD
0x2 0x6 0xA 0xE
0x3 0x7 0xB 0xF
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Modes and Timing
Modes and Timing
This section provides an overview of the typical usage modes and related timing infor-
mation for the ASX340AT.
Composite Video Output
The external pin DOUT_LSB0 can be used to configure the device for default NTSC or PAL
operation (auto-config mode). This and other video configuration settings are available
as register settings accessible through the serial interface.
NTSC
Both differential and single-ended connections of the full NTSC format are supported.
The differential connection that uses two output lines is used for low noise or long
distance applications. The single-ended connection is used for PCB tracks and screened
cable where noise is not a concern. The NTSC format has three black lines at the bottom
of each image for padding (which most LCDs do not display).
PAL
The PAL format is supported with 576 active image rows.
Single-Ended and Differential Composite Output
The composite output can be operated in a single-ended or differential mode by simply
changing the external resistor configuration. Refer to the Developer Guide for configura-
tion options.
Parallel Output (DOUT)
The DOUT[7:0] port supports both progressive and Interlaced mode. Progressive mode
(with FV and LV signal) include raw bayer(8 or 10 bit), YCbCr, RGB. Interlaced mode is
CCIR656 compliant.
Figure 29 shows the data that is output on the parallel port for CCIR656. Both NTSC and
PAL formats are displayed. The blue values in Figure 29 represent NTSC (525/60). The
red values represent PAL (625/50).
Figure 29: CCIR656 8-Bit Parallel Interface Format for 525/60 (625/50) Video Systems
Start of digital line Start of digital active line Next line
EAV CODE BLANKING SAV CODE CO-SITED _ CO-SITED _
F 00X8181 8 1F 0 0 XC Y C Y C Y C Y C Y F Digital
F 00Y0000 0 0F 0 0YB R B R R F video
stream
4 268 4 1440
4 280 4 1440
1716
1728
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Modes and Timing
Figure 30 shows detailed vertical blanking information for NTSC timing. See Table 25 for
data on field, vertical blanking, EAV, and SAV states.
Figure 30: Typical CCIR656 Vertical Blanking Intervals for 525/60 Video System
Line 4 Blanking Line 1 (V = 1)
Field 1 Active Video Line 20 (V = 0)
Field 1 Line 264 (V = 1)
(F = 0) Blanking Line 283 (V = 0)
Odd Field 2 Active Video Line 525 (V = 0)
266
Field 2
(F = 1)
Even
H=1 H=0
EAV SAV
Table 25: Field, Vertical Blanking, EAV, and SAV States 525/60 Video System
H H
Line Number F V (EAV) (SAV)
13 1 1 1 0
49 0 1 1 0
20263 0 0 1 0
264265 0 1 1 0
266282 1 1 1 0
283525 1 0 1 0
Figure 31 on page 51 shows detailed vertical blanking information for PAL timing. See
Table 26 on page 51 for data on field, vertical blanking, EAV, and SAV states.
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ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 31: Typical CCIR656 Vertical Blanking Intervals for 625/50 Video System
Blanking Line 1 (V = 1)
Line 23 (V = 0)
Field 1 Field 1 Active Video
(F = 0)
Odd
Blanking Line 311 (V = 1)
Line 336 (V = 0)
Field 2 Field 2 Active Video
(F = 1)
Even
Blanking Line 624 (V = 1)
Line 625 (V = 1)
H=1 H= 0
EAV SAV
Table 26: Field, Vertical Blanking, EAV, and SAV States for 625/50 Video System
H H
Line Number F V (EAV) (SAV)
122 0 1 1 0
23310
311312 0 0 1 0
313335
336623 0 1 1 0
624625
1 1 1 0
1 0 1 0
1 1 1 0
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Modes and Timing
Reset and Clocks Power-up reset is asserted or de-asserted with the RESET_BAR pin, which is active LOW.
In the reset state, all control registers are set to default values. See "Device Configura-
Reset tion" on page 28 for more details on Auto, Host, and Flash configurations.
Clocks Soft reset is asserted or de-asserted by the two-wire serial interface. In soft-reset mode,
the two-wire serial interface and the register bus are still running. All control registers
are reset using default values.
The ASX340AT has two primary clocks:
A master clock coming from the EXTCLK signal.
In default mode, a pixel clock (PIXCLK) running at 2 * EXTCLK. In raw Bayer bypass
mode, PIXCLK runs at the same frequency as EXTCLK.
When the ASX340AT operates in raw Bayer bypass mode, the image flow pipeline clocks
can be shut off to conserve power.
The sensor core is a master in the system. The sensor core frame rate defines the overall
image flow pipeline frame rate. Horizontal blanking and vertical blanking are influenced
by the sensor configuration, and are also a function of certain image flow pipeline func-
tions. The relationship of the primary clocks is depicted in Figure 32.
The image flow pipeline typically generates up to 16 bits per pixel--for example, YCbCr
or 565RGB--but has only an 8-bit port through which to communicate this pixel data.
To generate NTSC or PAL format images, the sensor core requires a 27 MHz clock.
Figure 32: Primary Clock Relationships
EXTCLK Sensor Sensor Core
Master Clock
10 bits/pixel
Sensor 1 pixel/clock
Pixel Clock
Colorpipe
16 bits/pixel
1 pixel/clock
Output Interface
16 bits/pixel (TYP)
0.5 pixel/clock
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Modes and Timing
Floating Inputs
The following ASX340AT pins cannot be floated:
SDATAThis pin is bidirectional and should not be floated
FRAME_SYNC
TRST_N
SCLK
SADDR
ATEST1
ATEST2
Output Data Ordering
Table 27: Output Data Ordering in DOUT RGB Mode
Mode Byte D7 D6 D5 D4 D3 D2 D1 D0
(Swap Disabled)
565RGB First R7 R6 R5 R4 R3 G7 G6 G5
555RGB Second G4 G3 G2 B7 B6 B5 B4 B3
444xRGB First 0 R7 R6 R5 R4 R3 G7 G6
x444RGB Second G5 G4 G3 B7 B6 B5 B4 B3
First R7 R6 R5 R4 G7 G6 G5 G4
Second B7 B6 B5 B4 0 0 0 0
First 0 0 0 0 R7 R6 R5 R4
Second G7 G6 G5 G4 B7 B6 B5 B4
Note: PIXCLK is 54 MHz when EXTCLK is 27 MHz.
Table 28: Output Data Ordering in Sensor Stand-Alone Mode
Mode D7 D6 D5 D4 D3 D2 D1 D0 DOUT_LSB1 DOUT_LSB0
10-bit Output B1 B0
B9 B8 B7 B6 B5 B4 B3 B2
Note: PIXCLK is 27 MHz when EXTCLK is 27 MHz.
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Modes and Timing
I/O Circuitry
Figure 33 illustrates typical circuitry used for each input, output, or I/O pad.
Figure 33: Typical I/O Equivalent Circuits
VDD_IO
Input Pad Receiver
Pad
GND
VDD_IO
SPI_SDI and RESET_BAR Receiver
Input Pad
Pad
GND
VDD_IO Receiver
I/O Pad
Slew
Pad Rate
Control
GND VDD_IO
Receiver
SCLK and XTAL_IN
Input Pad
Pad
GND Pad XTAL
VDD_IO Output Pad
Note: GND
All I/O circuitry shown above is for reference only. The actual implementation may be different.
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Figure 34: NTSC Block ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
NTSC Block
VDD_DAC
DAC_REF Pad
ESD
Pad DAC_POS
Resistor ESD
2.35k
Pad DAC_NEG
ESD
GND
Note: All I/O circuitry shown above is for reference only. The actual implementation may be different.
Figure 35: Serial Interface
ASX340AT/D Rev. H, 8/15 EN 55 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
I/O Timing
Digital Output
By default, the ASX340AT launches pixel data, FV, and LV synchronously with the falling
edge of PIXCLK. The expectation is that the user captures data, FV, and LV using the
rising edge of PIXCLK. The timing diagram is shown in Figure 36.
As an option, the polarity of the PIXCLK can be inverted from the default by program-
ming R0x0016[14].
Figure 36: Digital Output I/O Timing
t
extclk_period
Input EXTC LK
O utput PIXC LK
t t
pixclkf_dout dout_ho
O utput D OUT [7:0] t
dout_su
t
t fvlv_ho
pixclkf_fvlv
O utput F R AM E_VALID t
LIN E _VALID fvlv_su
Table 29: Parallel Digital Output I/O Timing
Signal fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
EXTCLK VDD_PLL = 2.8V; VDD_DAC = 2.8V; Default slew rate
PIXCLK1
DATA[7:0] Parameter Conditions Min Typ Max Unit
FV/LV fextclk 6 27 54 MHz
textclk_period 37 166.67
18.52 50 55 ns
Duty cycle 45 27 54 %
fpixclk 6 37.04 166.67 MHz
tpixclk_period 50 55 ns
18.52 1.9 %
Duty cycle 45 20 ns
tpixclkf_dout 1.55 20 ns
tdout_su 18 3.05 ns
tdout_ho 18 16 ns
tpixclkf_fvlv 1.6 21 ns
tfvlv_su 15 ns
tfvlv_ho 20
Note: PIXCLK can be inverted from the default by programming R0x0016[14].
ASX340AT/D Rev. H, 8/15 EN 56 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Slew Rate
Table 30: Slew Rate for PIXCLK and DOUT
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; V_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; T = 25C; CLOAD = 40 pF
PIXCLK DOUT[7:0]
R0x1E [10:8] Rise Time Fall Time R0x1E [2:0] Rise Time Fall Time Unit
000 NA NA 000 15.0 13.5 ns
001 NA NA 001 9.0 8.5 ns
010 7.0 6.9 010 6.8 6.0 ns
011 5.2 5.0 011 5.2 4.8 ns
100 4.0 3.8 100 3.8 3.5 ns
101 3.0 2.8 101 3.3 3.3 ns
110 2.4 2.2 110 3.0 3.0 ns
111 1.9 1.7 111 2.8 2.8 ns
Figure 37: Slew Rate Timing
P IXCLK 90%
tr is e 10%
tfa ll
D OUT 90%
10%
tr is e tfa ll
ASX340AT/D Rev. H, 8/15 EN 57 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Configuration Timing
During start-up, the Dout_LSB0, LV and FV are sampled. Setup and hold timing for the
RESET_BAR signal with respect to DOUT_LSB0, LV, and FV are shown in Figure 38 and
Table 31. These signals are sampled once by the on-chip firmware, which yields a long
tHOLD time.
Figure 38: Configuration Timing
RESET_BAR tSETUP tHOLD
DOUT_LSB0 Valid Data
FRAME_VALID
LINE_VALID
Table 31: Configuration Timing
Signal Parameter Min Typ Max Unit
DOUT_LSB0, FRAME_VALID, LINE_VALID
tSETUP 0 s
tHOLD
50 s
Note: Table data is based on EXTCLK = 27 MHz.
ASX340AT/D Rev. H, 8/15 EN 58 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 39: Power Up Sequence
VDD_PLL t0
VDD_DAC (2.8) t1
VAA_PIX t2
VAA (2.8)
VDD_IO (2.8)
VDD (1.8)
EXTCLK
RESET_BAR
t3 t4 t5
Hard Reset
Internal Patch Config
Initialization SPI or Host Streaming
Table 32: Power Up Sequence
Definition Symbol Minimum Typical Maximum Unit
VDD_PLL to VAA/VAA_PIX t0 0 s
VAA/VAA_PIX to VDD_IO t1 0 s
VDD_IO to VDD t2 0 s
Hard Reset t3 2 s
Internal Initialization t4 14 ms
Notes: 1. Delay between VDD and EXTCLK depends on customer devices, i.e. Xtal, Oscillator, and so on. There
is no requirement on this from the sensor.
2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are
required for the sensor itself, assuming all power rails are settled. In a circuit where Hard reset is
performed by the RC circuit, then the RC time must include the all power rail settle time and Xtal.
3. The time for Patch Config SPI or Host, that is, t5, depends on the patches being applied.
ASX340AT/D Rev. H, 8/15 EN 59 Semiconductor Components Industries, LLC, 2015.
Figure 40: Power Down Sequence ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
VDD (1.8)
t0
VDD_IO (2.8) t1
VAA_PIX t2
VAA (2.8)
VDD_PLL t3
VDD_DAC (2.8) Power Down until next Power Up Cycle
EXTCLK
Table 33: Power Down Sequence
Definition Symbol Minimum Typical Maximum Unit
VDD to VDD_IO t0 0 s
VDD_IO to VAA/VAA_PIX t1 0
VAA/VAA_PIX to VDD_PLL/DAC t2 0 s
Power Down until Next Power Up Time t3 1001
s
ms
(1) t3 is required between power down and next power up time, all decoupling caps from
regulators must completely discharge before next power up.
Figure 41: FRAME_SYNC to FRAME_VALID/LINE_VALID
tFRAME_SYNC
FRAME_SYNC tFRMSYNH_FVH
FRAME_VALID
LINE_VALID
Table 34: FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters
Parameter Name Conditions Min Typ Max Unit
FRAME_SYNC to FV/LV tFRMSYNC_FVH Interlaced mode 1.22 ms
tFRAME_SYNC tFRAMESYNC 1 s
ASX340AT/D Rev. H, 8/15 EN 60 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Modes and Timing
Figure 42: Reset to SPI Access Delay
R ESET_BAR
tRSTH_CSL
SPI_CS_N
Figure 43: Reset to Serial Access Delay tRSTH_SDATAL
RESET_BAR
SDATA
Figure 44: Reset to AE/AWB Image
RESET_BAR
VIDEO
First Frame Overlay from
Flash
tRSTH_FVL AE/AWB settled
tRSTH_OVL
tRSTH_AEAWB
Table 35: RESET_BAR Delay Parameters
Parameter Name Condition Min Typ Max Unit
RESET_BAR HIGH to SPI_CS_N LOW tRSTH_CSL 13 ms
RESET_BAR HIGH to SDATA LOW tRSTH_SDATAL 18 ms
RESET_BAR HIGH to FRAME_VALID tRSTH_FVL 14 ms
RESET_BAR HIGH to first Overlay tRSTH_OVL Overlay size dependent ms
RESET_BAR HIGH to AE/AWB settled tRSTH_AEAWB Scene dependent ms
RESET_BAR HIGH to first NTSC frame tRSTH_NTSC 47 ms
RESET_BAR HIGH to first PAL frame tRSTH_PAL 53 ms
ASX340AT/D Rev. H, 8/15 EN 61 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Electrical Specifications tCS_SCLK
Figure 45: SPI Output Timing tsu tSCLK_SDO
SPI_CS_N
SPI_SCLK
SPI_SDI
SPI_SDO
Table 36: SPI Data Setup and Hold Timing
Parameter Description Min Typ Max Units
fSPI_SCLK
tsu SPI_SCLK Frequency 1.6875 4.5 18 MHz
tSCLK_SDO
tCS_SCLK Setup time 110 ns
Hold time 110 ns
Delay from falling edge of SPI_CS_N to rising edge of SPI_SCLK 230 ns
Caution Stresses greater than those listed in Table 37 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other con-
ditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliabil-
ity.
Table 37: Absolute Maximum Ratings
Rating
Symbol Parameter Min Max Unit
VDD Digital power (1.8V)
VDD_IO I/O power (2.8v) -0.3 2.4 V
VAA VAA analog power (2.8V)
VAA_PIX Pixel array power (2.8v) -0.3 4 V
VDD_PLL PLL power (2.8V)
VDD_DAC DAC power (2.8V) -0.3 4 V
VIN DC Input Voltage
VOUT DC Output Voltage -0.3 4 V
TSTG Storage temperature
-0.3 4 V
-0.3 4 V
-0.3 VDD_IO+0.3 V
-0.3 VDD_IO+0.3 V
-50 150 C
Note: "Rating" column gives the maximum and minimum values that the device can tolerate.
ASX340AT/D Rev. H, 8/15 EN 62 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Table 38: Electrical Characteristics and Operating Conditions
Parameter1 Condition Min Typ Max Unit
Core digital voltage (VDD) 1.70 1.8 1.95 V
IO digital voltage (VDD_IO)
Video DAC voltage (VDD_DAC) 2.66 2.8 2.94 V
PLL Voltage (VDD_PLL)
Analog voltage (VAA) 2.66 2.8 2.94 V
Pixel supply voltage (VAA_PIX)
Imager operating temperature2 2.66 2.8 2.94 V
Functional operating temperature3
Storage temperature 2.66 2.8 2.94 V
2.66 2.8 2.94 V
40 +105 C
40 +85 C
50 +150 C
Notes: 1. VAA and VAA_PIX must all be at the same potential to avoid excessive current draw. Care must be
taken to avoid excessive noise injection in the analog supplies if all three supplies are tied together.
2. The imager operates in this temperature range, but image quality may degrade if it operates
beyond the functional operating temperature range.
3. Image quality is not guaranteed at temperatures equal to or greater than this range.
Table 39: Video DAC Electrical CharacteristicsSingle-Ended Mode
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V
Parameter Condition Min Typ Max Unit
Resolution
DNL Output pad (DAC_POS) 10 - bits
INL Unused output (DAC_NEG)
Output local load Single-ended mode, code 000h 0.2 0.4 bits
Single-ended mode, code 3FFh
Output voltage Single-ended mode, code 000h 0.7 3.5 bits
Single-ended mode, code 3FFh
Output current Estimate 37.5 -
Supply current DAC Reference
DAC_REF DAC Reference 37.5 -
R DAC_REF
.021 - V
1.392 - V
0.560 - mA
37.120 - mA
- 25.0 mA
1.200 - V
2.4 - K
Note: DAC_POS, DAC_NEG, and DAC_REF are loaded with resistors to simulate video output driving into
a low pass filter and achieve a full output swing of 1.4V. Their resistor loadings may be different
from the loadings in a real single-ended or differential-ended video output system with an actual
receiving end. Please refer to the Developer Guide for proper resistor loadings.
ASX340AT/D Rev. H, 8/15 EN 63 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Table 40: Video DAC Electrical CharacteristicsDifferential Mode
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V
Parameter Condition Min Typ Max Unit
DNL
INL 0.2 0.4 Bits
Output local load 0.7 3.5 Bits
Output voltage
Differential mode per pad 37.5
Output current (DAC_POS and DAC_NEG)
Supply current Differential mode, code 000h, pad dacp .022 V
DAC_REF
R DAC_REF Differential mode, code 000h, pad dacn 1.421 V
Differential mode, code 3FFh, pad dacp 1.421 V
Differential mode, code 3FFH, pad dacn .022 V
Differential mode, code 000h, pad dacp .587 mA
Differential mode, code 000h, pad dacn 37.893 mA
Differential mode, code 3FFh, pad dacp 37.893 mA
Differential mode, code 3FFH, pad dacn .587 mA
Estimate 50 mA
DAC Reference 1.2 V
DAC Reference 2.4 K
Note: DAC_POS, DAC_NEG, and DAC_REF are loaded with resistors to simulate video output driving into
a low pass filter and achieve a full output swing of 1.4V. Their resistor loadings may be different
from the loadings in a real single-ended or differential-ended video output system with an actual
receiving end. Please refer to the Developer Guide for proper resistor loadings.
Table 41: Digital I/O Parameters
TA = Ambient = 25C; All supplies at 2.8V
Signal Parameter Definitions Condition Min Typ Max Unit
All Load capacitance 5 30 pF
Outputs
VOH Output high voltage 0.7 * VDD_IO V
VOL Output low voltage 0.3* VDD_IO V
IOH Output high current VOH = VDD_IO - 0.4V 20 35 mA
IOL Output low current VOL = 0.4V 29 53 mA
All VIH Input high voltage 0.7 * VDD_IO VDD_IO + 0.5 V
Inputs
VIL Input low voltage 0.3 0.3 * VDD_IO V
IIH Input high leakage 0.02 0.26 A
current
IIL Input low leakage 0.01 0.05 A
current
Signal CAP Input signal 6.5 pF
capacitance
Notes: 1. All inputs are protected and may be active when all supplies (2.8V and 1.8V) are turned off.
ASX340AT/D Rev. H, 8/15 EN 64 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Power Consumption, Operating Mode
Table 42: Power Consumption Condition 1
fEXTCLK = 27 MHz; T = 25C, dark condition (lens with cover)
Power Plane Supply Condition 1 Typ Power Max Power Unit
Parallel off
VDD 1.8 48.2 72 mW
VDD_IO 2.8 Single 75 2.2
2.8 Total 96 10 mW
VAA 2.8 2.2
VAA_PIX 2.8 122.9 140 mW
VDD_DAC 2.8 18.8
VDD_PLL 290.3 5 mW
146 mW
25 mW
398 mW
Analog output uses single-ended mode: DAC_Pos = 75, DAC_Neg = 37.5, DAC_Ref =
2.4k, parallel output is disabled.
Table 43: Power Consumption Condition 2
fEXTCLK = 27 MHz; T = 25C, dark condition (lens with cover), CLOAD = 40pF
Power Plane Supply Condition 2 Typ Power Max Power Unit
Parallel on
VDD 1.8 47.5 72 mW
VDD_IO 2.8 VDAC off 26.6
2.8 Total 95.5 50 mW
VAA 2.8 2.2
VAA_PIX 2.8 1.1 140 mW
VDD_DAC 2.8 18.8
VDD_PLL 191.7 5 mW
5 mW
25 mW
297 mW
Analog output is disabled; parallel output is enabled.
ASX340AT/D Rev. H, 8/15 EN 65 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
NTSC Signal Parameters
Table 44: NTSC Signal Parameters
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V
Parameter Conditions Min Typ Max Units Notes
Line Frequency 15734.25 15734.27 15734.28 Hz
Field Frequency Hz 2, 4
Sync Rise Time 59.94 59.94 59.94 ns 2, 4
Sync Fall Time 111 148 222 ns
Sync Width 111 148 222 s 1, 2, 4
Sync Level 4.6 4.74 4.8 IRE 1, 2, 3, 4
Burst Level 39 40 41 IRE
Sync to Setup 36 40 44 s
(with pedestal off) 9.2 9.5 10.3
Sync to Burst Start s
Front Porch 4.71 5.3 5.71 s
Black Level 1.27 1.7 2.22 IRE
White Level 7.5 10 IRE
5 100 110
90
Notes: 1. Black and white levels are referenced to the blanking level.
2. NTSC convention standardized by the IRE (1 IRE = 7.14mV).
3. Encoder contrast setting R0x3C0A[5:4] = 0.
4. DAC ref = 2.8k, load = 37.5
ASX340AT/D Rev. H, 8/15 EN 66 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Figure 46: Video Timing
A
D E
B C
F G H
H
Table 45: Video Timing: Specification from Rec. ITU-R BT.470
A Signal NTSC PAL Units
B 27 MHz 27 MHz
C H Period s
D Hsync to burst 63.556 64.00 s
E 4.71 to 5.71 5.60 0.10 s
F burst 2.23 to 3.11 2.25 0.23 s
G Hsync to Signal 9.20 to 10.30 10.20 0.30 s
H 52.655 0.20 s
Video Signal 1.27 to 2.22 52 +0, -0.3 s
Front 4.70 0.10 s
1.5 +0.3, -0.0
Hsync Period 0.25 4.70 0.20
Sync rising/falling edge 0.20 0.10
ASX340AT/D Rev. H, 8/15 EN 67 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Figure 47: Equalizing Pulse
L
I
J
K
K
Table 46: Equalizing Pulse: Specification from Rec. ITU-R BT.470
I Signal NTSC PAL Units
J 27 MHz 27 MHz
K H/2 Period s
L Pulse width 31.778 32.00 s
Pulse rising/falling edge 2.30 0.10 2.35 0.10 s
Signal to pulse 0.25 0.05 s
0.25
1.50 -0.10 3.0 2.0
ASX340AT/D Rev. H, 8/15 EN 68 Semiconductor Components Industries, LLC, 2015.
Figure 48: V Pulse ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
P
M
O
N
P
Table 47: V Pulse: Specification from Rec. ITU-R BT.470
M Signal NTSC PAL Units
N 27 MHz 27 MHz
O H/2 Period s
P Pulse width 31.778 32.00 s
V pulse interval 27.10 (nominal) 27.30 0.10 s
Pulse rising/falling edge 4.70 0.10 s
4.70 0.10 0.25 0.05
0.25
ASX340AT/D Rev. H, 8/15 EN 69 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
Two-Wire Serial Bus Timing
Figure 49 and Table 48 describe the timing for the two-wire serial interface.
Figure 49: Two-Wire Serial Bus Timing Parameters
SDATA
tf tLOW tr tSU;DAT tf tHD;STA tr tBUF
SCLK
tHD;STA tHD;DAT tHIGH tSU;STA tSU;STO P S
S Sr
Table 48: Two-Wire Serial Bus Characteristics
fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25C
Standard Mode Fast Mode
Parameter Symbol Min Max Min Max Unit
SCLK Clock Frequency fSCL 0 100 0 400 KHz
Hold time (repeated) START condition.
After this period, the first clock pulse is tHD;STA 4.0 - 0.6 - s
generated
LOW period of the SCLK clock tLOW 4.7 - 1.3 - s
HIGH period of the SCLK clock tHIGH 4.0 - 0.6 - s
Set-up time for a repeated START condition tSU;STA 4.7 - 0.6 - s
Data hold time tHD;DAT 04 3.455 06 0.95 s
Data set-up time tSU;DAT 250 - 1006 - ns
Rise time of both SDATA and SCLK signals tr - 1000 20 + 0.1Cb7 300 ns
Fall time of both SDATA and SCLK signals tf - 300 20 + 300 ns
0.1Cb7
Set-up time for STOP condition tSU;STO 4.0 - 0.6 - s
Bus free time between a STOP and START tBUF 4.7 - 1.3 - s
condition
Capacitive load for each bus line Cb - 400 - 400 pF
Serial interface input pin capacitance
SDATA max load capacitance CIN_SI - 3.3 - 3.3 pF
SDATA pull-up resistor
CLOAD_SD - 30 - 30 pF
RSD 1.5 4.7 1.5 4.7 K
Notes: 1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I2C-compatible.
3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of
the SCLK signal.
6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it
ASX340AT/D Rev. H, 8/15 EN 70 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Electrical Specifications
must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according
to the Standard-mode I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
ASX340AT/D Rev. H, 8/15 EN 71 Semiconductor Components Industries, LLC, 2015.
ASX340AT/D Rev. H, 8/15 EN Spectral Characteristics
Figure 50: Quantum Efficiency
60 Red
GreenR
50 GreenB
Quantum Efficiency (%) Blue
40
30
20 ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Spectral Characteristics
72 10
0
350 450 550 650 750 850 950 1050 1150
Wavelength (nm)
Note: The measurements were done on packaged parts with regular glass coating (that is, without Anti-Reflective Glass (ARC) coating).
Semiconductor Components Industries, LLC, 2015
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Spectral Characteristics
Package and Die Dimensions
Figure 51: 63-Ball iBGA Package Outline Drawing
ASX340AT/D Rev. H, 8/15 EN 73 Semiconductor Components Industries, LLC, 2015
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Revision History
Revision History
Rev. H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8/31/15
Updated "Ordering Information" on page 3
Rev. G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/1/15
Updated "Ordering Information" on page 3
Rev. F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/29/15
Updated "Ordering Information" on page 3
Removed Confidential marking
Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/12/14
Applied ON Semiconductor template
Updated Table 2, "Key Parameters (continued)," on page 2
Updated Figure 2: "System Block Diagram," on page 8
Updated note to Figure 3: "Using a Crystal Instead of an External Oscillator," on
page 9
Updated Table 4, "Pin Descriptions," on page 10
Updated "Pixel Array Structure" on page 15
Updated Figure 5: "Pixel Array Description," on page 14
Updated "Power Sequence" on page 29
Updated "Host Command Interface" on page 31
Updated "Slave Two-Wire Serial Interface" on page 37
Updated "Overlay Capability" on page 42
Changed heading "Serial Memory Partition" to "NVM Partition" on page 43
Updated "External Memory Speed Requirement" on page 43
Updated "Overlay Adjustment" on page 44
Updated Figure 34: "NTSC Block," on page 55
Updated Table 29, "Parallel Digital Output I/O Timing," on page 56
Updated "Reset" on page 52
Updated "Clocks" on page 52
Updated Table 31, "Configuration Timing," on page 58
Updated Table 32, "Power Up Sequence," on page 59
Updated Figure 39: "Power Up Sequence," on page 59
Updated Table 34, "FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters," on
page 60
Updated Table 35, "RESET_BAR Delay Parameters," on page 61
Updated Table 37, "Absolute Maximum Ratings," on page 62
Updated Table 39, "Video DAC Electrical CharacteristicsSingle-Ended Mode," on
page 63
Updated Table 40, "Video DAC Electrical CharacteristicsDifferential Mode," on
page 64
Updated Table 41, "Digital I/O Parameters," on page 64
Updated Table 42, "Power Consumption Condition 1," on page 65
Updated Table 43, "Power Consumption Condition 2," on page 65
Updated Table 44, "NTSC Signal Parameters," on page 66
Updated Figure 46: "Video Timing," on page 67
Updated Figure 50: "Quantum Efficiency," on page 72
ASX340AT/D Rev. H, 8/15 EN 74 Semiconductor Components Industries, LLC, 2015.
ASX340CS: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor
Revision History
Updated Figure 51: "63-Ball iBGA Package Outline Drawing," on page 73
Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9/25/12
Updated Table 38, "Electrical Characteristics and Operating Conditions," on page 63
Updated Table 39, "Video DAC Electrical CharacteristicsSingle-Ended Mode," on
page 63
Updated "Power Consumption, Operating Mode" on page 65
Updated Table 44, "NTSC Signal Parameters," on page 66
Updated Table 45, "Video Timing: Specification from Rec. ITU-R BT.470," on page 67
Updated Table 46, "Equalizing Pulse: Specification from Rec. ITU-R BT.470," on
page 68
Updated Table 47, "V Pulse: Specification from Rec. ITU-R BT.470," on page 69
Updated note for Figure 50: "Quantum Efficiency," on page 72
Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7/18/12
Updated Figure 49: "Two-Wire Serial Bus Timing Parameters," on page 70
Updated Table 41, "Digital I/O Parameters," on page 64
Updated Table 48, "Two-Wire Serial Bus Characteristics," on page 70
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/18/12
Updated to Production
Updated Table 1: "Key Parameters," on page 1
Updated Table 6, "Reset/Default State of Interfaces," on page 12
Updated "Pixel Array Structure" on page 15
Updated "FOV Stretch Support" on page 25
Updated Table 29, "Parallel Digital Output I/O Timing," on page 56
Updated Table 30, "Slew Rate for PIXCLK and DOUT," on page 57
Updated Table 32, "Power Up Sequence," on page 59
Updated Table 33, "Power Down Sequence," on page 60
Updated Table 34, "FRAME_SYNC to FRAME_VALID/LINE_VALID Parameters," on
page 60
Updated Table 38, "Electrical Characteristics and Operating Conditions," on page 63
Updated Figure 51: "63-Ball iBGA Package Outline Drawing," on page 73
Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/10/11
Initial release
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the
rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/
Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey
any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
This literature is subject to all applicable copyright laws and is not for resale in any manner.
ASX340AT/D Rev. H, 8/15 EN 75 Semiconductor Components Industries, LLC, 2015 .
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