- Data Format: MSB 32,24-bit / LSB 24,20,16-bit / I
2
S
- PCM Short / Long Frame Supported
- TDM Format Supported
□
Digital Mixer Circuit
□
PLL Circuit
□
μP Interface: SPI(7MHz max), I
2
C-bus (1MHz, Fast Mode Plus)
□
Power Supply:
- Analog AVDD: 3.0 to 3.6V (typ. 3.3V)
- Digital LVDD: 3.0 to 3.6V (typ. 3.3V) (3.3V → 1.2V regulator integrated)
- I/F
VDD33: 3.0 to 3.6V (typ. 3.3V)
TVDD1: 1.7 to 3.6V (typ. 3.3V)
TVDD2: 1.7 to 3.6V (typ. 3.3V)
□
Operating Temperature Range: -40C to 85C
□
Package: 64-pin LQFP (10mm x 10mm, 0.5mm pitch)
015000122-E-00-PB
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2015/01
[AK7738]
3. Table of Contents
1.
2.
3.
4.
General Description ......................................................................................................................................... 1
Features ........................................................................................................................................................... 1
Table of Contents ............................................................................................................................................ 3
Block Diagram and Functions ......................................................................................................................... 4
Analog Characteristics............................................................................................................................ 15
■
Power Consumption ............................................................................................................................... 20
9.
Digital Filter Characteristics.......................................................................................................................... 21
10. DC Characteristics ......................................................................................................................................... 31
■
DC Characteristics .................................................................................................................................. 31
13. Revision History ............................................................................................................................................ 41
IMPORTANT NOTICE ...................................................................................................................................... 42
015000122-E-00-PB
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2015/01
[AK7738]
4. Block Diagram and Functions
■
Block Diagram
(Synchronous)
(Asynchronous)
Figure 1. Block Diagram
015000122-E-00-PB
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2015/01
[AK7738]
■
DSP1 Block Diagram
Pointer
CP0, CP1
DP0, DP1
Data RAM
6144w x 28Bit max
2048w Unit
DLP0, DLP1
Delay RAM
20480w x 28Bit max
4096w Unit
OFREG
64w x 15Bit
Coefficient RAM
6144w×24Bit max
2048w Unit
CBUS(24Bit)
DBUS(28Bit)
Micon I/F
MPX24
MPX24
Control
Program RAM
X
Y
Multiply
24×24
→
48Bit
DEC
8192w×36Bit max
2048w Unit
PC
Stack: 5 Level (max)
28Bit
TMP 12×28Bit
PTMP(LIFO) 6×28Bit
DBUS
SHIFT
48Bit
A
ALU
52Bit
Overflow Margin: 4Bit
52-Bit
DR0
3
52Bit
Over Flow Data
Generator
28bit x fifo16 DTMP (Connect to DSP2)
28bit x fifo8
CTMP (Connect to Sub DSP)
2 x 32Bit
2 x 32Bit
2 x 32Bit
2 x 32Bit
2 x 32Bit x fifo12
2 x 32Bit x fifo12
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
B
2 x 24Bit
2 x 24Bit
2 x 24Bit
2 x 24Bit
2 x 24Bit x fifo12
2 x 24Bit x fifo12
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
Serial I/F
48Bit
MUL
52Bit
Division 2424→24
Peak Detector
Figure 2. DSP1 Block Diagram (Note
1)
Note 1. Coefficient RAM, Data RAM, Delay RAM, Program RAM areas are shared by DSP1 and DSP2 and