[AK7738]
AK7738
Multi DSP with 5ch ADC + 4ch DAC + 8ch SRC
1. General Description
The AK7738 is a highly integrated digital signal processor, including a 24-bit stereo ADC with MIC gain
amplifiers, a 24-bit stereo ADC with input selector, a monaural ADC, two 32-bit stereo DACs, 4 stereo
sampling rate convertors supporting the sampling frequency up to 192kHz, two DSPs and a Sub DSP for
Audio/HF process. Each two DSPs and a Sub DSP has 2560step/fs (when fs=48kHz) parallel processing
power. The AK7738 is capable of processing sound and voice such as for hands-free function simultaneously
because two DSPs are able to work on different but synchronized sampling frequencies. As the AK7738 is a
RAM based DSP, it is freely programmable for user requirements, such as acoustic effects and proprietary
high performance hands-free function. The AK7738 is available in a 64-pin LQFP package.
2. Features
DSP1/DSP2: (Memory areas are shared by DSP1 and DSP2)
- Word length: 28-bit (Simple floating point supported)
- Instruction cycle: 8.1ns (2560fs at fs=48kHz)
- Multiplier: 24 x 24 48-bit (Double precision arithmetic available)
- Divider: 24 / 24 24-bit (Floating point normalization function)
- ALU: 52-bit arithmetic operation (with 4bits overflow margin)
- Program RAM: 8192 word x 36-bit
- Coefficient RAM: 6144 word x 24-bit
- Data RAM: 6144 word x 28-bit
- Delay RAM: 20480 word x 28-bit
- JX pins (Interrupt)
- Clock Mode Selector for DSP1, DSP2
- Independent Power Management Function for DSP1, DSP2
Sub DSP
- Word length: 28-bit (Simple floating point supported)
- Instruction cycle: 8.1ns (2560fs at fs=48kHz)
- Multiplier: 24 x 24 48-bit (Double precision arithmetic available)
- Divider: 24 / 24 24-bit (Floating point normalization function)
- ALU: 52-bit arithmetic operation (with 4bits overflow margin)
- Program RAM: 1024 word x 36-bit
- Coefficient RAM: 2048 word x 24-bit
- Data RAM: 4096 word x 28-bit
ADC1: 24-bit Stereo ADC with MIC Gain Amplifiers
- Sampling Frequency: fs=8kHz to 192kHz
- Channel Independent Analog Gain Amplifiers
(0 to 18dB(2dB Step), 18 to 36dB(3dB step))
- Differential Input or Single-ended Input
- ADC Characteristics S/N: 102dB (fs=48kHz, Differential Input, MIC Gain=0dB,)
- Channel Independent Digital Volume Control (+24 to -103dB, 0.5dB Step, Mute)
- Analog DRC (Dynamic Range Control)
- Digital HPF for DC Offset Cancelling
- Low Noise MIC Power Output: 2ch
- 4 types of Digital Filter for Sound Color Selection
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ADC2: 24-bit Stereo ADC with Input Selector
- Sampling Frequency: fs=8kHz to 192kHz
- Analog Input Selector: Differential Input x1 or Single-ended Input x2,
Semi-Differential Input x1
- ADC Characteristics S/N: 102dB (fs=48kHz, Differential Input)
- Channel Independent Digital Volume (+24 to -103dB, 0.5dB Step, Mute)
- Digital HPF for DC Offset Cancelling
- 4 types of Digital Filter for Sound Color Selection
ADCM: 24-bit Monaural ADC
- Sampling Frequency: fs=8kHz to 192kHz
- Differential Input or Single-ended Input
- ADC Characteristics S/N: 102dB (fs=48kHz, Differential Input)
- Channel Independent Digital Volume (+24 to -103dB, 0.5dB Step, Mute)
- Digital HPF for DC Offset Cancelling
- 4 types of Digital Filter for Sound Color Selection
DAC: Advanced 32-bit DAC
- 2ch x2
- Sampling Frequency: fs=8kHz to 192kHz
- Single-ended Output
- DAC Characteristics S/N: 108dB (fs=48kHz)
- Channel Independent Digital Volume Control (+12 to -115dB, 0.5dB Step, Mute)
- 4 types of Digital Filter for Sound Color Selection
SRC:
- 2ch x4
- FSI = 8kHz to 192kHz, FSO = 8kHz to 192kHz (FSO/FSI = 0.167 to 6.0)
FSCONV: Monaural Simple SRC
- 1ch x2
- FSI = 44.1kHz to 48kHz, FSO = 8kHz to 16kHz (FSO/FSI = 0.167 to 0.363)
DIT:
- S/PDIF, IEC60958, AES/EBU, EIAJ CP1201 Compatible
- 24-bit Stereo Output
Digital Interface:
- Digital Input Port: max 24ch when TDM mode
- Digital Output Port: max 28ch when TDM mode
- Independent LRCK/BICK Input port x 5 Lines
- Data Format: MSB 32,24-bit / LSB 24,20,16-bit / I2S
- PCM Short / Long Frame Supported
- TDM Format Supported
Digital Mixer Circuit
PLL Circuit
P Interface: SPI(7MHz max), I2C-bus (1MHz, Fast Mode Plus)
Power Supply:
- Analog AVDD: 3.0 to 3.6V (typ. 3.3V)
- Digital LVDD: 3.0 to 3.6V (typ. 3.3V) (3.3V 1.2V regulator integrated)
- I/F VDD33: 3.0 to 3.6V (typ. 3.3V)
TVDD1: 1.7 to 3.6V (typ. 3.3V)
TVDD2: 1.7 to 3.6V (typ. 3.3V)
Operating Temperature Range: -40C to 85C
Package: 64-pin LQFP (10mm x 10mm, 0.5mm pitch)
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3. Table of Contents
1. General Description......................................................................................................................................... 1
2. Features ........................................................................................................................................................... 1
3. Table of Contents ............................................................................................................................................ 3
4. Block Diagram and Functions ......................................................................................................................... 4
Block Diagram..........................................................................................................................................4
DSP1 Block Diagram ...............................................................................................................................5
DSP2 Block Diagram ...............................................................................................................................6
Sub DSP Block Diagram ..........................................................................................................................7
5. Pin Configurations and Functions ................................................................................................................... 8
Ordering Guide.........................................................................................................................................8
Pin Layout ................................................................................................................................................8
Pin Functions ............................................................................................................................................9
Handling of Unused Pins........................................................................................................................12
Internal Pulled-down Pin Status .............................................................................................................12
Power-down Status of Output Pins.........................................................................................................13
Relationship between Power Supplies and Digital Pins .........................................................................13
6. Absolute Maximum Ratings.......................................................................................................................... 14
7. Recommended Operating Conditions............................................................................................................ 14
8. Electrical Characteristics ............................................................................................................................... 15
Analog Characteristics............................................................................................................................15
Power Consumption ...............................................................................................................................20
9. Digital Filter Characteristics.......................................................................................................................... 21
10. DC Characteristics......................................................................................................................................... 31
DC Characteristics..................................................................................................................................31
11. Switching Characteristics .............................................................................................................................. 32
12. Package.......................................................................................................................................................... 40
Outline Dimensions ................................................................................................................................40
Material and Lead Finish........................................................................................................................40
Marking ..................................................................................................................................................41
13. Revision History............................................................................................................................................ 41
IMPORTANT NOTICE ...................................................................................................................................... 42
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Block Diagram 4. Block Diagram and Functions
(Synchronous)
(Asynchronous)
Figure 1. Block Diagram
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[AK7738]
DSP1 Block Diagram
Pointer CP0, CP1 DP0, DP1 DLP0, DLP1 OFREG
64w x 15Bit
Coefficient RAM Data RAM Delay RAM
6144w24Bit max 6144w x 28Bit max
20480w x 28Bit max
2048w Unit 2048w Unit 4096w Unit
CBUS(24Bit)
DBUS(28Bit)
MPX24 MPX24 Micon I/F Serial I/F
Control
X Y DEC Program RAM
8192w36Bit max
Multiply
2424 48Bit 2048w Unit
28Bit PC
Stack: 5 Level (max)
48Bit
TMP 1228Bit
PTMP(LIFO) 628Bit
52Bit MUL DBUS 2 x 24Bit DIN6
SHIFT 2 x 24Bit DIN5
2 x 24Bit DIN4
48Bit 2 x 24Bit DIN3
2 x 24Bit x fifo12 DIN2
A B
2 x 24Bit x fifo12 DIN1
ALU
52Bit 2 x 32Bit DOUT6
2 x 32Bit DOUT5
Overflow Margin: 4Bit 2 x 32Bit DOUT4
2 x 32Bit DOUT3
52-Bit 2 x 32Bit x fifo12 DOUT2
DR0 3 2 x 32Bit x fifo12 DOUT1
52Bit 28bit x fifo16 DTMP (Connect to DSP2)
Over Flow Data 28bit x fifo8 CTMP (Connect to Sub DSP)
Generator
Division 242424 Peak Detector
Figure 2. DSP1 Block Diagram (Note 1)
Note 1. Coefficient RAM, Data RAM, Delay RAM, Program RAM areas are shared by DSP1 and DSP2 and
the sizes are configurable by control registers.
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SDOUT3
[AK7738]
DSP2 Block Diagram
Pointer CP0, CP1 DP0, DP1 DLP0, DLP1 OFREG
64w x 15Bit
Coefficient RAM Data RAM Delay RAM
6144w24Bit max 6144w x 28Bit max
20480w x 28Bit max
2048w Unit 2048w Unit 4096w Unit
CBUS(24Bit)
DBUS(28Bit)
MPX24 MPX24 Micon I/F Serial I/F
Control
X Y DEC Program RAM
8192w36Bit max
Multiply
2048w Unit
2424 48Bit PC
Stack : 5 Level(max)
28Bit
TMP 1228Bit
48Bit
PTMP(LIFO) 628Bit
52Bit MUL DBUS 2 x 24Bit DIN6
SHIFT 2 x 24Bit DIN5
2 x 24Bit DIN4
48Bit 2 x 24Bit DIN3
2 x 24Bit DIN2
A B 2 x 24Bit DIN1
ALU 2 x 32Bit DOUT6
2 x 32Bit DOUT5
52Bit 2 x 32Bit DOUT4
2 x 32Bit DOUT3
Overflow Margin: 4Bit 2 x 32Bit DOUT2
2 x 32Bit DOUT1
52-Bit
28bit x fifo16 DTMP (Connect to DSP1)
DR0 3
52Bit
Over Flow Data
Generator
Division 242424 Peak Detector
Figure 3. DSP2 Block Diagram (Note 1)
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Sub DSP Block Diagram
Pointer CP0, CP1 DP0
Coefficient RAM Data RAM
2048w24Bit 4096w x 28Bit
CBUS(24Bit)
DBUS(28Bit)
MPX24 MPX24 Micon I/F Serial I/F
Control
X Y DEC Program RAM
1024w36Bit
Multiply
2424 48Bit PC
Stack : 5 Level(max)
28Bit
TMP 1228Bit
48Bit PTMP(LIFO) 628Bit
52Bit MUL DBUS
SHIFT
28Bit x fifo8 CTMP (Connect to DSP1)
48Bit
A B
ALU
52Bit
Overflow Margin: 4Bit
52-Bit
DR0 3
52Bit
Over Flow Data
Generator
Division 242424 Peak Detector
Figure 4. Sub DSP Block Diagram
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5. Pin Configurations and Functions
Ordering Guide
AK7738VQ: -40 +85C 64-pin LQFP (0.5mm pitch)
AKD7738:
Evaluation Board for AK7738
Pin Layout
AIN2RP / AIN3R AIN2RN / AIN4R AIN5L GNDIN5 AIN5R AINMP / AINM AINMN DVSS3 LVDD AVDRV PDN SI / I2CFIL SCLK / SCL SO / SDA CSN STO / RDY / SDOUT4
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AIN2LN / AIN4L 49 32 SDOUT3 / GPO1
DVSS2
AIN2LP / AIN3L 50 AVDD LVDD TVDD2 31 TVDD2
BICK4
INN2 51 30 LRCK4
BICK3 / JX3
AIN1R / INP2 52 29 LRCK3 / JX2
SDIN4
INN1 53 28 SDIN3 / JX1
SDIN1
AIN1L / INP1 54 64pin LQFP 27 SDOUT1
( Top View ) BICK1
MPREF 55 26 LRCK1
SDIN2 / JX0
MPWR1 56 25 SDOUT2 / GPO0
BICK2
MPWR2 57 24
AVDD 58 23
AVSS 59 22
VCOM 60 21
VREFH 61 20
VREFL 62 TVDD1 19
AOUT1R 63 VDD33 18
AOUT1L 64 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
AOUT2R AOUT2L TESTI LRCK5 SDOUT5 / GPO2 BICK5 CLKO SDOUT6 / DIT / GPO3 SDIN5 / JX0 SDIN6 XTO XTI VDD33 DVSS1 TVDD1 LRCK2
Input
Output
I/O
Power
*** are internal pulled-down pins. (***: Pin Name)
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Pin Functions
No. Pin Name I/O Function
1 AOUT2R O DAC2 Rch Analog Output Pin
This pin outputs "Hi-Z" during power-down state.
2 AOUT2L
O DAC2 Lch Analog Output Pin
3 TESTI This pin outputs "Hi-Z" during power-down state.
4 LRCK5
I Test Input Pin
SDOUT5 It must be tied "L".
5
I/O LR Channel Select Clock 5 Pin
GPO2
6 BICK5 O Serial Data Output 5 Pin
7 CLKO
O DSP Programmable Output 2 Pin (GPO0 Output of DSP2)
SDOUT6
8 DIT I/O Serial Bit Clock 5 Pin
GPO3 O Master Clock Output Pin
SDIN5
9 O Serial Data Output 6 Pin
JX0
10 SDIN6 O Digital Transmit Channel Output Pin
11 XTO O DSP Programmable Output 3 Pin (GPO1 Output of DSP2)
12 XTI I Serial Data Input 5 Pin
13 VDD33 I External Conditional Jump Input 0 Pin
14 DVSS1
15 TVDD1 I Serial Data Input 6 Pin
16 LRCK2
17 BICK2 Crystal Oscillator Output Pin
O When using a crystal oscillator, connect it between XTI and XTO.
SDOUT2
18 When not using a crystal oscillator, leave this pin open.
GPO0 Crystal Oscillator Input Pin
SDIN2
19 I When using a crystal oscillator, connect it between XTI and XTO.
JX0 When not using a crystal oscillator, connect this pin to an external clock or
20 LRCK1
21 BICK1 DVSS1.
22 SDOUT1
23 SDIN1 - Digital I/F Power Supply Pin 3.0~3.6V (typ.3.3V)
- Digital Ground 1 Pin 0V (Substrate potential)
- Digital I/F Power Supply 1 Pin 1.7~3.6V (typ.3.3V)
I/O LR Channel Select Clock 2 Pin
I/O Serial Bit Clock 2 Pin
O Serial Data Output 2 Pin
O DSP Programmable Output 0 Pin (GPO0 Output of DSP1)
I Serial Data Input 2 Pin
I External Conditional Jump Input 0 Pin
I/O LR Channel Select Clock 1 Pin
I/O Serial Bit Clock 1 Pin
O Serial Data Output 1 Pin
I Serial Data Input 1 Pin
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[AK7738]
No. Pin Name I/O Function
SDIN3
I Serial Data Input 3 Pin
24
JX1 I External Conditional Jump Input 1 Pin
25 SDIN4 I Serial Data Input 4 Pin
LRCK3
I/O LR Channel Select Clock 3 Pin
26
JX2 I External Conditional Jump Input 2 Pin
BICK3
I/O Serial Bit Clock 3 Pin
27
JX3 I External Conditional Jump Input 3 Pin
28 LRCK4 I/O LR Channel Select Clock 4 Pin
29 BICK4
30 TVDD2 I/O Serial Bit Clock 4 Pin
31 DVSS2
- Digital I/F Power Supply 2 Pin 1.7~3.6V (typ.3.3V)
SDOUT3
32 - Digital Ground 2 Pin 0V (Substrate potential)
GPO1 O Serial Data Output 3 Pin
STO
33 RDY O DSP Programmable Output 1 Pin (GPO1 Output of DSP1)
SDOUT4
O Status Output Pin
34 CSN This pin outputs "L" during power-down state.
SO O RDY Signal Output Pin
35
O Serial Data Output 4 Pin
SDA
SCLK SPI Mode
36
SCL I SPI I/F Chip Select N Pin
SI During power-down state or when P I/F are not in use, leave this pin "H"
37
I2CFIL level.
38 PDN I2C Mode
I I2C I/F Chip Address N Pin
39 AVDRV
This pin must be pulled up or pulled down.
40 LVDD
41 DVSS3 O Serial Data Output Pin for SPI I/F
This pin outputs "Hi-Z" during power-down state.
I/O Serial Data In/Output Pin for I2C I/F
This pin outputs "Hi-Z" during power-down state.
I Serial Data Clock Input Pin for SPI I/F
I Serial Data Clock Input Pin for I2C I/F
I Serial Data Input Pin for SPI I/F
I2C I/F Mode Select Input Pin
I I2CFIL = "L": Fast Mode (400kHz)
I2CFIL = "H": Fast Mode Plus (1MHz) (should be fixed to TVDD2)
Power-down N Pin
I Use this pin to power down the AK7738.
The PDN pin should be held "L" when power is supplied.
LDO Output Pin
O Connect a 2.2uF ceramic capacitor between this pin and DVSS3.
Do not connect this pin to an external circuit.
- Digital Core Power Supply Pin 3.0~3.6V (typ.3.3V)
- Digital Ground 3 Pin 0V (Substrate potential)
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[AK7738]
No. Pin I/O Function
Name
42 AINMN I ADCM Inverted Differential Input Pin
AINMP I ADCM Non-inverted Differential Input Pin
43 I ADCM Single-ended Input Pin
AINM
44 AIN5R I ADC2 Rch Pseudo Differential Input 5 Pin
45 GNDIN5 I ADC2 Pseudo Differential Ground Input 5 Pin
46 AIN5L I ADC2 Lch Pseudo Differential Input 5 Pin
AIN2RN I ADC2 Rch Inverted Differential Input 2 Pin
47 I ADC2 Rch Single-ended Input 4 Pin
AIN4R
AIN2RP I ADC2 Rch Non-inverted Differential Input 2 Pin
48 I ADC2 Rch Single-ended Input 3 Pin
AIN3R
AIN2LN I ADC2 Lch Inverted Differential Input 2 Pin
49 I ADC2 Lch Single-ended Input 4 Pin
AIN4L
AIN2LP I ADC2 Lch Non-inverted Differential Input 2 Pin
50 I ADC2 Lch Single-ended Input 3 Pin
AIN3L
51 INN2 I ADC1 Rch Inverted Differential Input 2 Pin
AIN1R I ADC1 Rch Single-ended Input 1 Pin
52 I ADC1 Rch Non-inverted Differential Input 2 Pin
INP2
53 INN1 I ADC1 Lch Inverted Differential Input 1 Pin
AIN1L I ADC1 Lch Single-ended Input 1 Pin
54 I ADC1 Lch Non-inverted Differential Input 1 Pin
INP1
Ripple Filter Pin for Microphone Power Supply
55 MPREF O Connect a 1uF ceramic capacitor between this pin and AVSS.
56 MPWR1
Do not connect this pin to an external circuit.
O Power Supply Output 1 Pin for Microphone
This pin outputs "Hi-Z" during power-down state.
57 MPWR2 O Power Supply Output 2 Pin for Microphone
This pin outputs "Hi-Z" during power-down state.
58 AVDD - Analog Power Supply Pin 3.0~3.6V (typ.3.3V)
59 AVSS - Analog Ground Pin 0V (Substrate potential)
Analog Common Voltage Output Pin
60 VCOM O Connect a 2.2uF ceramic capacitor between this pin and AVSS.
Do not connect this pin to an external circuit.
This pin outputs "L" during power-down state.
61 VREFH I Analog High-level Reference Voltage Input Pin
Connect this pin to AVDD.
62 VREFL I Analog Low-level Reference Voltage Input Pin
Connect this pin to AVSS.
63 AOUT1R O DAC1 Rch Analog Output Pin
This pin outputs "Hi-Z" during power-down state.
64 AOUT1L O DAC1 Lch Analog Output Pin
This pin outputs "Hi-Z" during power-down state.
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Handling of Unused Pins
Unused I/O pins must be connected appropriately.
Classification Pin Name Setting
Analog MPREF, MPWR1, MPWR2, AIN1L/INP1, INN1, AIN1R/INP2, INN2, Open
AIN2LP/AIN3L, AIN2LN/AIN4L, AIN2RP/AIN3R, AIN2RN/AIN4R,
AIN5L, GNDIN5, AIN5R, AINMP/AINM, AINMN, AOUT1L,
AOUT1R, AOUT2L, AOUT2R
CLKO, XTO, SDOUT1, SDOUT2/GPO0, SDOUT3/GPO1, Open
STO/RDY/SDOUT4, SDOUT5/GPO2, SDOUT6/DIT/GPO3
Digital XTI , SDIN6, SDIN5/JX0, SDIN4, SDIN3/JX1, SDIN2/JX0, SDIN1, Connect to
LRCK1, BICK1, LRCK2, BICK2, LRCK3/JX2, BICK3/JX3, LRCK4, DVSS1 ~ 3
BICK4, LRCK5, BICK5, TESTI
Table 1. Handling of Unused Pins
Note 2. Although it is recommended that the LRCK1, BICK1, LRCK2, BICK2, LRCK3/JX2, BICK3/JX3,
LRCK4, BICK4, LRCK5 and BICK5 pins are connected to DVSS1-3 when not using, they can be
open since they are pulled down internally.
Internal Pulled-down Pin Status
Internal pulled-down I/O pins have different statuses in power-down and power-down release statuses.
Power Down Status Power Down Release Power Down Release
PDN pin = "L"
No Pin Name I/O PDN pin = "H" PDN pin = "H"
(when I/O pin = Input) (when I/O pin = Output)
3 TESTI I Pulled-down (25k) Pulled-down (25k) Pulled-down (25k)
4 LRCK5 I/O Pulled-down (50k) Pulled-down (46k) Output
5 SDOUT5/GPO2 O Pulled-down (50k) Output Output
6 BICK5 I/O Pulled-down (50k) Pulled-down (46k) Output
7 CLKO O Pulled-down (50k) Output Output
8 SDOUT6/DIT/GPO3 O Pulled-down (50k) Output Output
16 LRCK2 I/O Pulled-down (50k) Pulled-down (46k) Output
17 BICK2 I/O Pulled-down (50k) Pulled-down (46k) Output
18 SDOUT2/GPO0 O Pulled-down (50k) Output Output
20 LRCK1 I/O Pulled-down (50k) Pulled-down (46k) Output
21 BICK1 I/O Pulled-down (50k) Pulled-down (46k) Output
22 SDOUT1 O Pulled-down (50k) Output Output
26 LRCK3/JX2 I/O Pulled-down (50k) Pulled-down (46k) Output
27 BICK3/JX3 I/O Pulled-down (50k) Pulled-down (46k) Output
28 LRCK4 I/O Pulled-down (50k) Pulled-down (46k) Output
29 BICK4 I/O Pulled-down (50k) Pulled-down (46k) Output
32 SDOUT3/GPO1 O Pulled-down (50k) Output Output
33 STO/RDY/SDOUT4 O Pulled-down (50k) Output Output
39 AVDRV O Pulled-down (70) Output Output
Table 2. Internal Pulled-down Pin Status
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Power-down Status of Output Pins
No Pin Name I/O Power-down Status No Pin Name I/O Power-down Status
60 VCOM O "L" Output 35 SO/SDA I/O "Hi-Z" Output
55 MPREF O "L" Output
56 MPWR1 O "Hi-Z" Output 22 SDOUT1 O "L" Output
57 MPWR2 O "Hi-Z" Output 18 SDOUT2/GPO0 O "L" Output
64 AOUT1L O "Hi-Z" Output 32 SDOUT3/GPO1 O "L" Output
63 AOUT1R O "Hi-Z" Output 33 STO/RDY/SDOUT4 O "L" Output
2 AOUT2L O "Hi-Z" Output 5 SDOUT5/GPO2 O "L" Output
1 AOUT2R O "Hi-Z" Output 8 SDOUT6/DIT/GPO3 O "L" Output
20 LRCK1 I/O Input 7 CLKO O "L" Output
21 BICK1 I/O Input 11 XTO O "H" Output
16 LRCK2 I/O Input 39 AVDRV O "L" Output
17 BICK2 I/O Input
26 LRCK3/JX2 I/O Input
27 BICK3/JX3 I/O Input
28 LRCK4 I/O Input
29 BICK4 I/O Input
4 LRCK5 I/O Input
6 BICK5 I/O Input
Table 3. Power-down Status of Output Pins
Relationship between Power Supplies and Digital Pins
Power Digital Pins
Supply
TVDD1 SDIN1, SDIN2/JX0, SDOUT1, SDOUT2/GPO0, LRCK1, BICK1, LRCK2, BICK2
SDIN3/JX1, SDIN4, SDOUT3/GPO1, STO/RDY/SDOUT4, LRCK3/JX2, BICK3/JX3,
TVDD2 LRCK4, BICK4, PDN, SCLK/SCL, SO/SDA, CSN, SI/I2CFIL
SDIN5/JX0, SDIN6, SDOUT5/GPO2, SDOUT6/DIT/GPO3, LRCK5, BICK5, CLKO,
VDD33 TESTI, XTO, XTI
Table 4. Relationship between Power Supplies and Digital Pins
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6. Absolute Maximum Ratings
(AVSS=DVSS1=DVSS2=DVSS3=0V; Note 3)
Parameter Symbol min max Unit
Power Supplies
Analog AVDD -0.3 4.3 V
Digital1(Core) LVDD -0.3 4.3 V
Digital2(I/F) TVDD1 -0.3 4.3 V
Digital3(I/F) TVDD2 -0.3 4.3 V
Digital4(I/F) VDD33 -0.3 4.3 V
DVSS-AVSS (Note 3) GND -0.3 0.3 V
Input Current (except power supply pins) IIN 10 mA
Analog Input Voltage (Note 4) VINA -0.3 (AVDD+0.3)4.3 V
Digital Input Voltage (Note 5) VIND1 -0.3 (TVDD1+0.3)4.3 V
Digital Input Voltage (Note 6) VIND2 -0.3 (TVDD2+0.3)4.3 V
Digital Input Voltage (Note 7) VIND3 -0.3 (VDD33+0.3)4.3 V
Ambient Temperature (Power applied) Ta -40 85 C
Storage Temperature Tstg -65 150 C
Note 3. All voltages are with respect to ground. AVSS and DVSS1-3 must be connected to the same ground.
Note 4. The maximum analog input voltage is smaller value between (AVDD+0.3)V and 4.3V.
Note 5. The maximum digital input voltage of SDIN1, SDIN2/JX0, LRCK1, BICK1, LRCK2 and BICK2
pins is smaller value between (TVDD1+0.3)V and 4.3V.
Note 6. The maximum digital input voltage of SDIN3/JX1, SDIN4, LRCK3/JX2, BICK3/JX3, LRCK4,
BICK4, PDN, SCLK/SCL, SO/SDA, CSN and SI/I2CFIL pins is smaller value between
(TVDD2+0.3)V and 4.3V.
Note 7. The maximum digital input voltage of SDIN5/JX0, SDIN6, LRCK5, BICK5, TESTI and XTI pins is
smaller value between (VDD33+0.3)V and 4.3V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal
operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(AVSS=DVSS1=DVSS2=DVSS3=0V; Note 3)
Parameter Symbol min typ max Unit
Power Supplies
Analog AVDD 3.0 3.3 3.6 V
Digital1(Core) LVDD 3.0 3.3 3.6 V
Digital2(I/F) TVDD1 1.7 3.3 3.6 V
Digital3(I/F) TVDD2 1.7 3.3 3.6 V
Digital4(I/F) VDD33 3.0 3.3 3.6 V
Note 8. The power-up sequence with AVDD, DVDD, TVDD1, TVDD2 and VDD33 is not critical. The
PDN pin should be held "L" when power is supplied. The PDN pin is allowed to be "H" after all
power supplies are applied and settled.
Note 9. Do not turn off the power supply of the AK7738 with the power supply of the peripheral device
turned on. When using the I2C interface, pull-up resistors of SDA and SCL pins should be
connected to TVDD2 or less voltage.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet.
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8. Electrical Characteristics
Analog Characteristics
1. MIC AMP Gain
(Ta=25C; AVDD=LVDD=TVDD1=TVDD2=VDD33=3.3V; AVSS=DVSS1=DVSS2=DVSS3=0V)
Parameter min typ max Unit
Input Impedance 14 20 26 k
MGNL[3:0]bits=0h, MGNR[3:0]bits=0h -1 0 1
MGNL[3:0]bits=1h, MGNR[3:0]bits=1h 1 2 3
MGNL[3:0]bits=2h, MGNR[3:0]bits=2h 3 4 5
MGNL[3:0]bits=3h, MGNR[3:0]bits=3h 5 6 7
MGNL[3:0]bits=4h, MGNR[3:0]bits=4h 7 8 9
MGNL[3:0]bits=5h, MGNR[3:0]bits=5h 9 10 11
MIC MGNL[3:0]bits=6h, MGNR[3:0]bits=6h 11 12 13
AMP MGNL[3:0]bits=7h, MGNR[3:0]bits=7h 13 14 15 dB
Gain MGNL[3:0]bits=8h, MGNR[3:0]bits=8h 15 16 17
MGNL[3:0]bits=9h, MGNR[3:0]bits=9h 17 18 19
MGNL[3:0]bits=Ah, MGNR[3:0]bits=Ah 20 21 22
MGNL[3:0]bits=Bh, MGNR[3:0]bits=Bh 23 24 25
MGNL[3:0]bits=Ch, MGNR[3:0]bits=Ch 26 27 28
MGNL[3:0]bits=Dh, MGNR[3:0]bits=Dh 29 30 31
MGNL[3:0]bits=Eh, MGNR[3:0]bits=Eh 32 33 34
MGNL[3:0]bits=Fh, MGNR[3:0]bits=Fh 35 36 37
2. MIC Bias
(Ta=25C; AVDD=LVDD=TVDD1=TVDD2=VDD33=3.3V; AVSS=DVSS1=DVSS2=DVSS3=0V;
Measurement Frequency =20Hz~20kHz)
Parameter min typ max Unit
Output Voltage 2.3 2.5 2.7 V
MIC Bias Load Resistance 2 k
Load Capaitance 30 pF
Output Noise (A-weighted) -114 -108 dBV
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3. MIC AMP + ADC1
(Ta=25C; AVDD=LVDD=TVDD1=TVDD2=VDD33=3.3V; AVSS=DVSS1=DVSS2=DVSS3=0V; Signal
Frequency=1kHz; 24-bit Data; BICK=64fs, Measurement Frequency=20Hz ~ 20kHz @ fs=48kHz;
Measurement Frequency=20Hz ~ 40kHz @ fs=96kHz and fs=192kHz, Differential Input, Unless otherwise
specified.)
Parameter min typ max Unit
Resolution 24 Bit
Differential Input (Note 11) 2.1 2.3 2.5 Vpp
Input Voltage Differential Input (Note 12) 0.264 0.290 0.315
(Note 13) Single-ended Input (Note 11) 2.1 2.3 2.5 Vpp
Single-ended Input (Note 12) 0.264 0.290 0.315
fs=48kHz (Note 11) 80 90
fs=48kHz (Note 12) 82
S/(N+D) fs=96kHz (Note 11) 87 dB
(-1dBFS) fs=96kHz (Note 12) 79
fs=192kHz (Note 11, Note 14) 87
fs=192kHz (Note 12, Note 14) 79
MIC AMP fs=48kHz (A-weighted) (Note 11) 94 102
+ ADC1 fs=48kHz (A-weighted) (Note 12) 90
Dynamic Range fs=96kHz (Note 11) 95 dB
(Note 12) 87
(-60dBFS) fs=96kHz
fs=192kHz (Note 11) 95
fs=192kHz (Note 12) 87
fs=48kHz (A-weighted) (Note 11) 94 102
fs=48kHz (A-weighted) (Note 12) 90
S/N fs=96kHz (Note 11) 95 dB
fs=96kHz (Note 12) 87
fs=192kHz (Note 11) 95
fs=192kHz (Note 12) 87
Inter-Channel Isolation (fin=1kHz) (Note 10) 90 105 dB
Channel Gain Mismatch 0.0 0.3 dB
Note 10. Inter-channel isolation with -1dBFS signal input.
Note 11. MGNL/R[3:0] bits = 0h (0dB). Input full-scale voltage is propotional to AVDD (0.7 x AVDD).
Note 12. MGNL/R[3:0] bits = 9h (+18dB). Input full-scale voltage is propotional to AVDD (0.088 x
AVDD).
Note 13. -0.7dBFS is output when fs=192kHz and ADC1 digital filter is set to Slow Roll-Off or Short Delay
Slow Roll-Off filter.
Note 14. In the case of inputting -1.6dBFS when fs=192kHz and ADC1 digital filter is set to Slow Roll-Off
or Short Delay Slow Roll-Off filter.
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4. ADC2
(Ta=25C; AVDD=LVDD=TVDD1=TVDD2=VDD33=3.3V; AVSS= DVSS1=DVSS2=DVSS3=0V;
Signal Frequency=1kHz; 24-bit Data, BICK = 64fs; Measurement Frequency=20Hz ~ 20kHz @ fs=48kHz;
Measurement Frequency=20Hz ~ 40kHz @ fs=96kHz and fs=192kHz, Differential Input, Unless otherwise
specified.)
Parameter min typ max Unit
Resolution 24 Bit
Input Impedance 14 20 26 k
Input Voltage Differential Input (Note 15) 2.1 2.3 2.5 Vpp
(Note 18)
Single-ended Input (Note 16) 2.1 2.3 2.5 Vpp
Pseudo Differential Input (Note 17) 2.1 2.3 2.5 Vpp
S/(N+D) fs=48kHz 80 90
(-1dBFS) fs=96kHz
fs=192kHz 87 dB
ADC2 (Note 19) 87
Dynamic Range fs=48kHz (A-weighted) 94 102
(-60dBFS) fs=96kHz
fs=192kHz 95 dB
95
fs=48kHz (A-weighted) 94 102
S/N fs=96kHz 95 dB
fs=192kHz 95
Inter-Channel Isolation (fin=1kHz) (Note 10) 90 105 dB
Channel Gain Mismatch 0.0 0.3 dB
Note 15. AIN2LP, AIN2LN, AIN2RP and AIN2RN pins.
Note 16. AIN3L, AIN3R, AIN4L and AIN4R pins.
Note 17. AIN5L and AIN5R pins.
Note 18. -0.7dBFS is output when fs=192kHz and ADC2 digital filter is set to Slow Roll-Off or Short Delay
Slow Roll-Off filter.
Note 19. In the case of inputting -1.6dBFS when fs=192kHz and ADC2 digital filter is set to Slow Roll-Off
or Short Delay Slow Roll-Off filter.
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5. ADCM
(Ta=25C; AVDD=LVDD=TVDD1=TVDD2=VDD33=3.3V; AVSS= DVSS1=DVSS2=DVSS3=0V;
Signal Frequency=1kHz; 24-bit Data, BICK = 64fs; Measurement Frequency=20Hz ~ 20kHz @ fs=48kHz;
Measurement Frequency=20Hz ~ 40kHz @ fs=96kHz and fs=192kHz, Differential Input, Unless otherwise
specified.)
Parameter min typ max Unit
Resolution 24 Bit
Input Impedance 14 20 26 k
Input Voltage Differential Input (Note 20) 2.1 2.3 2.5 Vpp
(Note 22) Single-ended Input (Note 21) 2.1 2.3 2.5 Vpp
S/(N+D) fs=48kHz 80 90
ADCM (-1dBFS) fs=96kHz
fs=192kHz 87 dB
(Note 23) 87
Dynamic Range fs=48kHz (A-weighted) 94 102
(-60dBFS) fs=96kHz
fs=192kHz 95 dB
95
fs=48kHz (A-weighted) 94 102
S/N fs=96kHz 95 dB
fs=192kHz 95
Note 20. AINMP and AINMN pins.
Note 21. AINM pin.
Note 22. -0.7dBFS is output when fs=192kHz and ADCM digital filter is set to Slow Roll-Off or Short
Delay Slow Roll-Off filter.
Note 23. In the case of inputting -1.6dBFS when fs=192kHz and ADCM digital filter is set to Slow
Roll-Off or Short Delay Slow Roll-Off filter.
6. DAC
(Ta=25C; AVDD= LVDD =TVDD1=TVDD2= VDD33=3.3V; AVSS= DVSS1=DVSS2=DVSS3=0V;
Signal Frequency=1kHz; 32-bit Data, BICK = 64fs; Measurement Frequency=20Hz ~ 20kHz @ fs=48kHz;
Measurement Frequency=20Hz ~ 40kHz @ fs=96kHz and fs=192kHz; Unless otherwise specified. )
Parameter min typ max Unit
Resolution 32 Bit
Output Voltage (Note 24) 2.55 2.83 3.11 Vpp
S/(N+D) fs=48kHz 80 91
(0dBFS) fs=96kHz
fs=192kHz 89 dB
89
Dynamic Range fs=48kHz (A-weighted) 100 108
(-60dBFS)
DAC1 fs=96kHz 101 dB
DAC2 fs=192kHz
101
fs=48kHz (A-weighted) 100 108
S/N fs=96kHz 101 dB
fs=192kHz 101
Inter-Channel Isolation (fin=1kHz) (Note 25) 90 110 dB
Channel Gain Mismatch 0.0 0.7 dB
Load Resistance (Note 26) 10 k
Load Capaitance 30 pF
Note 24. The output voltage when 0dBFS signal input. The output voltage is proportional to AVDD
(AVDD x 0.86).
Note 25. Inter-channel isolation between each DAC of Lch and Rch with 0dBFS signal input. (AOUT1L
and AOUT1R, and AOUT2L and AOUT2R)
Note 26. to AC load
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7. SRC
(Ta=25C; AVDD=LVDD=TVDD1=TVDD2=VDD33=3.3V; AVSS= DVSS1=DVSS2=DVSS3=0V;
Signal Frequency=1kHz; 24-bit Data; Measurement Frequency=20Hz ~ FSO/2)
Parameter Symbol min typ max Unit
Resolution 24 Bit
Input Sample Rate FSI 8 192 kHz
(Note 27)
Output Sample Rate FSO 8 192 kHz
THD+N (Input=1kHz, 0dBFS)
FSO/FSI=192kHz/48kHz -113 dB
FSO/FSI=192kHz/44.1kHz -113 dB
FSO/FSI=44.1kHz/48kHz -112 dB
FSO/FSI=44.1kHz/96kHz -111 dB
FSO/FSI=48kHz/44.1kHz -112 -103 dB
FSO/FSI=48kHz/96kHz -113 dB
FSO/FSI=48kHz/8kHz -111 dB
FSO/FSI=16kHz/48kHz -113 dB
FSO/FSI=16kHz/44.1kHz -100 dB
FSO/FSI=8kHz/48kHz -113 dB
FSO/FSI=8kHz/44.1kHz -95 dB
FSO/FSI=48kHz/192kHz -105 dB
SRC FSO/FSI=44.1kHz/192kHz -102 dB
Dynamic Range (Input=1kHz, -60dBFS)
FSO/FSI=192kHz/48kHz 113 dB
FSO/FSI=192kHz/44.1kHz 113 dB
FSO/FSI=44.1kHz/48kHz 113 dB
FSO/FSI=44.1kHz/96kHz 113 dB
FSO/FSI=48kHz/44.1kHz 108 113 dB
FSO/FSI=48kHz/96kHz 113 dB
FSO/FSI=48kHz/8kHz 113 dB
FSO/FSI=16kHz/48kHz 113 dB
FSO/FSI=16kHz/44.1kHz 113 dB
FSO/FSI=8kHz/48kHz 111 dB
FSO/FSI=8kHz/44.1kHz 114 dB
FSO/FSI=48kHz/192kHz 111 dB
FSO/FSI=44.1kHz/192kHz 110 dB
Dynamic Range
(Input=1kHz, -60dBFS, A-weighted)
FSO/FSI=44.1kHz/48kHz 115 dB
Ratio between Input and Output Sample Rate FSO/FSI 0.167 6 -
Note 27. Set FSI frequency of each operating SRC as the sum of the frequencies is below 384kHz. For
example, if the frequency of FSI is 96kHz, four SRCs can operate at the same time, if the
frequency of FSI is 192kHz, only two SRCs are allowed to operate at the same time.
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8. FSCONV
(Ta=25C; AVDD=LVDD=TVDD1=TVDD2=VDD33=3.3V; AVSS= DVSS1=DVSS2=DVSS3=0V;
Signal Frequency=1kHz; 24-bit Data; Measurement Frequency=20Hz ~ FSO/2)
Parameter Symbol min typ max Unit
Resolution 24 Bit
Input Sample Rate FSI 44.1 48 kHz
Output Sample Rate FSO 8 16 kHz
THD+N (Input=1kHz, 0dBFS)
FSO/FSI=16kHz/48kHz -114 dB
FSO/FSI=16kHz/44.1kHz -95 dB
FSO/FSI=8kHz/48kHz -115 dB
FSCONV FSO/FSI=8kHz/44.1kHz -97 dB
Dynamic Range (Input=1kHz, -60dBFS)
FSO/FSI=16kHz/48kHz 114 dB
FSO/FSI=16kHz/44.1kHz 114 dB
FSO/FSI=8kHz/48kHz 114 dB
FSO/FSI=8kHz/44.1kHz 114 dB
Dynamic Range
(Input=1kHz, -60dBFS, A-weighted)
FSO/FSI=8kHz/48kHz 117 dB
Ratio between Input and Output Sample Rate FSO/FSI 0.167 0.363 -
Power Consumption
(Ta=25C; AVDD=3.0~3.6V(typ=3.3V, max=3.6V); LVDD=3.0~3.6V(typ=3.3V, max=3.6V);
TVDD1=1.7~3.6V(typ=3.3V, max=3.6V); TVDD2=1.7~3.6V (typ=3.3V, max=3.6V); VDD33=3.0~3.6V
(typ=3.3V, max=3.6V); AVSS= DVSS1=DVSS2=DVSS3=0V; fs=192kHz; BICK=64fs;
SDOUT1~6/LRCK1~5/BICK1~5=Output; CL=20pF)
Parameter Symbol min typ max Unit
AVDD 26 37 mA
Power-Up (PDN pin= "H") LVDD 70 140 mA
(Note 28) TVDD1
TVDD2 1.6 2.4 mA
1.6 2.4 mA
VDD33 4 6 mA
AVDD 0.01 mA
LVDD 0.01 mA
Power-Down (PDN pin= "L") TVDD1 0.01 mA
TVDD2 0.01 mA
VDD33 0.01 mA
Note 28. The current of LVDD changes depending on the system frequency and contents of DSP program.
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9. Digital Filter Characteristics
1. ADC Block
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V)
1-1 Sharp Roll-Off Filter (ADSD bit = "0", ADSL bit = "0")
fs=48kHz
Parameter Symbol min typ max Unit
SHARP ROLL-OFF
Passband (Note 29) 0dB ~ -0.06dB PB 0 22.1 kHz
-6.0dB PB
24.4 kHz
Stopband (Note 29) SB 27.8 kHz
Stopband Attenuation SA 85 dB
Group Delay Distortion : 0Hz~20kHz GD 0 1/fs
Group Delay (Note 30) GD 19 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 1.0 Hz
fs=96kHz
Parameter Symbol min typ max Unit
SHARP ROLL-OFF
Passband (Note 29) 0dB ~ -0.06dB PB 0 44.2 kHz
-6.0dB PB 48.7
kHz
Stopband (Note 29) SB 55.6 kHz
Stopband Attenuation SA 85 dB
Group Delay Distortion : 0Hz~40kHz GD 0 1/fs
Group Delay (Note 30) GD 19 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 1.9 Hz
fs=192kHz
Parameter Symbol min typ max Unit
SHARP ROLL-OFF
Passband (Note 29) 0dB ~ -0.04dB PB 0 83.7 kHz
-6.0dB PB
100.1 kHz
Stopband (Note 29) SB 122.9 kHz
Stopband Attenuation SA 85 dB
Group Delay Distortion : 0Hz~40kHz GD 0 1/fs
Group Delay (Note 30) GD 15 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 3.9 Hz
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1-2 Slow Roll-Off Filter (ADSD bit = "0", ADSL bit = "1")
fs=48kHz
Parameter Symbol min typ max Unit
SLOW ROLL-OFF
Passband (Note 29) 0dB ~ -0.074dB PB 0 12.5 kHz
-6.0dB PB 21.9
kHz
Stopband (Note 29) SB 36.5 kHz
Stopband Attenuation SA 85 dB
Group Delay Distortion : 0Hz~20kHz GD 0 1/fs
Group Delay (Note 30) GD 7 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 1.0 Hz
fs=96kHz
Parameter Symbol min typ max Unit
SLOW ROLL-OFF
Passband (Note 29) 0dB ~ -0.074dB PB 0 25 kHz
-6.0dB PB 43.7
kHz
Stopband (Note 29) SB 73 kHz
Stopband Attenuation SA 85 dB
Group Delay Distortion : 0Hz~40kHz GD 0 1/fs
Group Delay (Note 30) GD 7 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 1.9 Hz
fs=192kHz
Parameter Symbol min typ max Unit
SLOW ROLL-OFF
Passband (Note 29) 0dB ~ -0.7dB PB 0 49.9 kHz
-6.0dB PB 79.9
kHz
Stopband (Note 29) SB 146 kHz
Stopband Attenuation SA 85 dB
Group Delay Distortion : 0Hz~40kHz GD 0 1/fs
Group Delay (Note 30) GD 8 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 3.88 Hz
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1-3 Short Delay Sharp Roll-Off Filter (ADSD bit = "1", ADSL bit = "0")
fs=48kHz
Parameter Symbol min typ max Unit
SHORT DELAY SHARP ROLL-OFF
Passband (Note 29) 0dB ~ -0.06dB PB 0 22.1 kHz
-6.0dB PB
24.4 kHz
Stopband (Note 29) SB 27.8 kHz
Stopband Attenuation SA 85 dB
Group Delay Distortion : 0Hz~20kHz GD 2.6 1/fs
Group Delay (Note 30) GD 5 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 1.0 Hz
fs=96kHz
Parameter Symbol min typ max Unit
SHORT DELAY SHARP ROLL-OFF
Passband (Note 29) 0dB ~ -0.06dB PB 0 44.2 kHz
-6.0dB PB 48.7
kHz
Stopband (Note 29) SB 55.6 kHz
Stopband Attenuation SA 85 dB
Group Delay Distortion : 0Hz~40kHz GD 2.6 1/fs
Group Delay (Note 30) GD 5 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 1.9 Hz
fs=192kHz
Parameter Symbol min typ max Unit
SHORT DELAY SHARP ROLL-OFF
Passband (Note 29) 0dB ~ -0.04dB PB 0 83.7 kHz
-6.0dB PB
100.1 kHz
Stopband (Note 29) SB 122.9 kHz
Stopband Attenuation SA 85 dB
Group Delay Distortion : 0Hz~40kHz GD 0.2 1/fs
Group Delay (Note 30) GD 6 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 3.88 Hz
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1-4 Short Delay Slow Roll-Off Filter (ADSD bit = "1", ADSL bit = "1")
fs=48kHz
Parameter Symbol min typ max Unit
SHORT DELAY SLOW ROLL-OFF
Passband (Note 29) 0dB ~ -0.074dB PB 0 12.5 kHz
-6.0dB PB 21.9
kHz
Stopband (Note 29) SB 36.5 kHz
Stopband Attenuation SA 85 dB
Group Delay Distortion : 0Hz~20kHz GD 2.6 1/fs
Group Delay (Note 30) GD 5 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 1.0 Hz
fs=96kHz
Parameter Symbol min typ max Unit
SHORT DELAY SLOW ROLL-OFF
Passband (Note 29) 0dB ~ -0.074dB PB 0 25 kHz
-6.0dB PB 43.7
kHz
Stopband (Note 29) SB 73 kHz
Stopband Attenuation SA 85 dB
Group Delay Distortion : 0Hz~40kHz GD 2.6 1/fs
Group Delay (Note 30) GD 5 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 1.9 Hz
fs=192kHz
Parameter Symbol min typ max Unit
SHORT DELAY SLOW ROLL-OFF
Passband (Note 29) 0dB ~ -0.7dB PB 0 49.9 kHz
-6.0dB PB
77.7 kHz
Stopband (Note 29) SB 145.9 kHz
Stopband Attenuation SA 85 dB
Group Delay Distortion : 0Hz~40kHz GD 0.5 1/fs
Group Delay (Note 30) GD 6 1/fs
ADC Digital Filter(HPF)
Frequency Response -3.0dB FR 3.88 Hz
Note 29. The passband and stopband frequencies are proportional to fs (sampling rate). High-pass filter
characteristics are not included.
Note 30. Delay time caused by the digital filter calculation. This time is measured from an analog signal
input until 24-bit data of both channels are set into the output register.
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2. DAC Block
(Ta= 25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V)
2-1 Sharp Roll-Off Filter (DASD bit = "0", DASL bit = "0")
fs=48kHz
Parameter Symbol min typ max Unit
SHARP ROLL-OFF PB 0
PB -0.08
Passband (Note 31) -0.08dB~0.08dB PR 26.2 22.2 kHz
-6.0dB SB 69.9
SA 23.99 kHz
GD -0.20
Passband Ripple +0.08 dB
FR
Stopband (Note 31) kHz
Stopband Attenuation dB
Group Delay (Note 32) 26.4 1/fs
Digital Filter + SCF
Frequency Response : 0Hz 20kHz 0.10 dB
fs=96kHz
Parameter Symbol min typ max Unit
SHARP ROLL-OFF PB 0
PB -0.08
Passband (Note 31) -0.08dB~0.08dB PR 52.5 44.4 kHz
-6.0dB SB 69.8
SA 48.00 kHz
GD -0.50
Passband Ripple +0.08 dB
FR
Stopband (Note 31) kHz
Stopband Attenuation dB
Group Delay (Note 32) 26.4 1/fs
Digital Filter + SCF
Frequency Response : 0Hz 40kHz 0.10 dB
fs=192kHz
Parameter Symbol min typ max Unit
SHARP ROLL-OFF
Passband (Note 31) -0.08dB~0.08dB PB 0 88.8 kHz
-6.0dB PB
96.00 kHz
Passband Ripple PR -0.08 +0.08 dB
Stopband (Note 31) SB 104.9 kHz
Stopband Attenuation SA 69.8 dB
Group Delay (Note 32) GD 26.4 1/fs
Digital Filter + SCF
Frequency Response : 0Hz 80kHz FR -2.00 -0.00 dB
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2-2 Slow Roll-Off Filter (DASD bit = "0", DASL bit = "1")
fs=48kHz
Parameter Symbol min typ max Unit
SLOW ROLL-OFF PB 0
PB -0.07
Passband (Note 31) -0.07dB~ +0.021dB PR 42.6 9.0 kHz
-3.0dB SB 72.6
SA 19.75 kHz
GD -3.75
Passband Ripple +0.021 dB
FR
Stopband (Note 31) kHz
Stopband Attenuation (Note 33) dB
Group Delay (Note 32) 26.4 1/fs
Digital Filter + SCF
Frequency Response : 0Hz 20kHz -2.75 dB
fs=96kHz
Parameter Symbol Min typ max Unit
SLOW ROLL-OFF PB 0
PB -0.07
Passband (Note 31) -0.07dB~+0.023dB PR 85.1 18.1 kHz
-3.0dB SB 72.6
SA 39.6 kHz
GD -4.25
Passband Ripple +0.023 dB
FR
Stopband (Note 31) kHz
Stopband Attenuation (Note 33) dB
Group Delay (Note 32) 26.4 1/fs
Digital Filter + SCF
Frequency Response : 0Hz 40kHz -2.75 dB
fs=192kHz
Parameter Symbol min typ max Unit
SLOW ROLL-OFF PB 0
PB -0.07
Passband (Note 31) -0.07dB~+0.023dB PR 170.3 36.1 kHz
-3.0dB SB 72.6
SA 79.3 kHz
GD -5.00
Passband Ripple +0.023 dB
FR
Stopband (Note 31) kHz
Stopband Attenuation (Note 33) dB
Group Delay (Note 32) 26.4 1/fs
Digital Filter + SCF
Frequency Response : 0Hz 80kHz -3.00 dB
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2-3 Short Delay Sharp Roll-Off Filter (DASD bit = "1", DASL bit = "0")
fs=48kHz
Parameter Symbol min typ max Unit
SHORT DELAY SHARP ROLL-OFF
Passband (Note 31) -0.07dB~+0.07dB PB 0 22.0 kHz
-6.0dB PB
24.11 kHz
Passband Ripple PR -0.07 +0.07 dB
Stopband (Note 31) SB 26.2 kHz
Stopband Attenuation SA 56.6 dB
Group Delay (Note 32) GD 5.9 1/fs
Digital Filter + SCF
Frequency Response : 0Hz 20kHz FR -0.20 0.10 dB
fs=96kHz
Parameter Symbol min typ max Unit
SHORT DELAY SHARP ROLL-OFF
Passband (Note 31) -0.08dB~+0.08dB PB 0 44.3 kHz
-6.0dB PB
48.25 kHz
Passband Ripple PR -0.08 +0.08 dB
Stopband (Note 31) SB 52.5 kHz
Stopband Attenuation SA 56.4 dB
Group Delay (Note 32) GD 5.9 1/fs
Digital Filter + SCF
Frequency Response : 0Hz 40kHz FR -0.50 0.10 dB
fs=192kHz
Parameter Symbol Min typ max Unit
SHORT DELAY SHARP ROLL-OFF
Passband (Note 31) -0.08dB~+0.08dB PB 0 88.6 kHz
-6.0dB PB
96.50 kHz
Passband Ripple PR -0.08 +0.08 dB
Stopband (Note 31) SB 104.9 kHz
Stopband Attenuation SA 56.4 dB
Group Delay (Note 32) GD 5.9 1/fs
Digital Filter + SCF
Frequency Response : 0Hz 80kHz FR -2.00 -0.00 dB
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[AK7738]
2-4 Short Delay Slow Roll-Off Filter (DASD bit = "1", DASL bit = "1")
fs=48kHz
Parameter Symbol min typ max Unit
SHORT DELAY SLOW ROLL-OFF
Passband (Note 31) -0.07dB~+0.05dB PB 0 10.1 kHz
-3.0dB PB
20.24 kHz
Passband Ripple PR -0.07 +0.05 dB
Stopband (Note 31) SB 43.0 kHz
Stopband Attenuation (Note 33) SA 74.9 dB
Group Delay (Note 32) GD 5.2 1/fs
Digital Filter + SCF
Frequency Response : 0Hz 20kHz FR -3.50 -2.50 dB
fs=96kHz
Parameter Symbol min typ max Unit
SHORT DELAY SLOW ROLL-OFF
Passband (Note 31) -0.07dB~+0.05dB PB 0 20.3 kHz
-3.0dB PB
40.50 kHz
Passband Ripple PR -0.07 +0.05 dB
Stopband (Note 31) SB 86.0 kHz
Stopband Attenuation (Note 33) SA 74.9 dB
Group Delay (Note 32) GD 5.2 1/fs
Digital Filter + SCF
Frequency Response : 0Hz 40kHz FR -4.00 -2.50 dB
fs=192kHz
Parameter Symbol min typ max Unit
SHORT DELAY SHARP ROLL-OFF
Passband (Note 31) -0.07dB~+0.05dB PB 0 40.6 kHz
-3.0dB PB
81.00 kHz
Passband Ripple PR -0.07 +0.05 dB
Stopband (Note 31) SB 172.0 kHz
Stopband Attenuation (Note 33) SA 74.9 dB
Group Delay (Note 32) GD 5.2 1/fs
Digital Filter + SCF
Frequency Response : 0Hz 80kHz FR -4.75 -2.75 dB
Note 31. The passband and stopband frequencies are proportional to fs (sampling rate).
Note 32. Delay time caused by the digital filter calculation. This time is measured from setting of the
16/24/32-bit impulse data to the input registers to output of the analog peak signal.
Note 33. Band width of Stopband Attenuation ranges from SB to fs.
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[AK7738]
3. SRC Block
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V)
Parameter Symbol min typ max Unit
-0.01dB 0.980 FSO/FSI 6.000 PB 0 0.4583FSI kHz
-0.01dB 0.900 FSO/FSI < 0.990 PB 0 0.4167FSI kHz
Passband -0.01dB 0.533 FSO/FSI < 0.909 (Note 35) PB 0 0.2182FSI kHz
-0.50dB 0.533 FSO/FSI < 0.909 (Note 36) PB 0 0.3007FSI kHz
-0.01dB 0.490 FSO/FSI < 0.539 PB 0 0.2177FSI kHz
-0.01dB 0.450 FSO/FSI < 0.495 PB 0 0.1948FSI kHz
-0.01dB 0.225 FSO/FSI < 0.455 PB 0 0.1312FSI kHz
-0.50dB 0.167 FSO/FSI < 0.227 PB 0 0.0658FSI kHz
0.980 FSO/FSI 6.000 SB 0.5417FSI kHz
0.900 FSO/FSI < 0.990 SB 0.5021FSI kHz
0.533 FSO/FSI < 0.909 (Note 35) SB 0.2974FSI kHz
Stopband 0.533 FSO/FSI < 0.909 (Note 36) SB 0.3320FSI kHz
0.490 FSO/FSI < 0.539 SB 0.2812FSI kHz
0.450 FSO/FSI < 0.495 SB 0.2604FSI kHz
0.225 FSO/FSI < 0.455 SB 0.1802FSI kHz
0.167 FSO/FSI < 0.227 SB 0.0970FSI kHz
0.900 FSO/FSI 6.000 PR 0.01 dB
0.533 FSO/FSI < 0.909 (Note 35) PR 0.01 dB
Passband Ripple 0.533 FSO/FSI < 0.909 (Note 36) PR 0.50 dB
0.225 FSO/FSI 0.539 PR 0.01 dB
0.167 FSO/FSI < 0.227 PR 0.50 dB
0.900 FSO/FSI 6.000 SA 95.2 dB
0.533 FSO/FSI < 0.909 (Note 35) SA 95.2 dB
Stopband 0.533 FSO/FSI < 0.909 (Note 36) SA 90.0 dB
Attenuation 0.450 FSO/FSI 0.539 SA 95.2 dB
0.225 FSO/FSI < 0.455 SA 90.0 dB
0.167 FSO/FSI < 0.227 SA 85.0 dB
Group Delay 61
(Ts=1/fs) GD (54/FSI+ Ts
(Note 34) 7/FSO)
Note 34. This value is SRC block only. It is the time from a rising edge of input LRCK after data is input to a
rising edge of output LRCK just before the data is output when there is no phase difference
between input and output LRCK.
Note 35. In the case of SRCFAUD bit = "1"
Note 36. In the case of SRCFAUD bit = "0"
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[AK7738]
4. FSCONV
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V)
Parameter Symbol min typ max Unit
Passband -0.01dB 0.167 FSO/FSI 0.363 PB 0 0.1814FSI kHz
Stopband 0.167 FSO/FSI 0.363 SB 0.8185FSI kHz
Passband Ripple 0.167 FSO/FSI 0.363 PR 0.005 dB
Stopband Attenuation 0.167 FSO/FSI 0.363 SA 94.0 dB
Group Delay (Ts=1/FSI) GD 9 Ts
(Note 37)
Note 37. It is the time from a rising edge of input LRCK after data is input to a rising edge of output LRCK
just before the data is output when there is no phase difference between input and output LRCK.
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[AK7738]
10. DC Characteristics
DC Characteristics
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V)
Parameter Symbol min typ max Unit
High-Level Input Voltage 1 (Note 38) VIH1 80%TVDD1 V
Low-Level Input Voltage 1 (Note 38) VIL1 20%TVDD1 V
High-Level Input Voltage 2 (Note 39) VIH2 80%TVDD2 V
Low-Level Input Voltage 2 (Note 39) VIL2 20%TVDD2 V
High-Level Input Voltage 3 (Note 40) VIH3 80%VDD33 V
Low-Level Input Voltage 3 (Note 40) VIL3 20%VDD33 V
SCL, SDA High-Level Input Voltage VIH4 70%TVDD2 V
SCL, SDA Low-Level Input Voltage VIL4 30%TVDD2 V
High-Level Output Voltage Iout= -100A (Note 38) VOH1 TVDD1-0.3 V
Low-Level Output Voltage Iout=100A (Note 38) VOL1 0.3 V
High-Level Output Voltage Iout= -100A (Note 39) VOH2 TVDD2-0.3 V
Low-Level Output Voltage Iout=100A (Note 39) VOL2 0.3 V
High-Level Output Voltage Iout= -100A (Note 40) VOH3 VDD33-0.3 V
Low-Level Output Voltage Iout=100A (Note 40) VOL3 0.3 V
Fast Mode
SCL, SDA TVDD2 2.0V (Iout=3mA) VOL4 0.4 V
Low Level TVDD2< 2.0V (Iout=3mA) VOL4 20%TVDD2 V
Output Fast Mode Plus
Voltage TVDD2 2.0V (Iout=20mA) VOL4 0.4 V
TVDD2 < 2.0V (Iout=3mA) VOL4 20%TVDD2 V
Input Leak Current (Note 41) Iin 10 A
Input Leak Current, Pulled down pin (Note 42) Iid 66 A
Power Down
Input Leak Current, Pulled down pin Iid 72 A
Power Down Release (Note 43)
Input Leak Current, TESTI pin lid 132 A
Input Leak Current, XTI pin lix 17 A
Note 38. SDIN1, SDIN2/JX0, SDOUT1, SDOUT2/GPO0, LRCK1, BICK1, LRCK2 and BICK2 pins.
Note 39. SDIN3/JX1, SDIN4, SDOUT3/GPO1, STO/RDY/SDOUT4, LRCK3/JX2, BICK3/JX3, LRCK4,
BICK4, PDN, SCLK/SCL, SO/SDA, CSN, and SI/I2CFIL pins. The SCL and SDA pins are not
included.
Note 40. SDIN5/JX0, SDIN6, SDOUT5/GPO2, SDOUT6/DIT/GPO3, LRCK5, BICK5, CLKO, XTO, XTI
and TESTI pins
Note 41. Except internal pulled-down pins and the XTI pin.
Note 42. LRCK5, BICK5, LRCK2, BICK2, LRCK1, BICK1, LRCK3/JX2, BICK3/JX3, LRCK4 and BICK4
pins are internal pulled-down pins (typ. 50 k@3.3V) when the AK7738 is powered down (PDN
pin = "L"). The TESTI pin is not included.
Note 43. LRCK5, BICK5, LRCK2, BICK2, LRCK1, BICK1, LRCK3/JX2, BICK3/JX3, LRCK4 and BICK4
pins are internal pulled-down pins (typ. 46 k@3.3V) when power-down is released (PDN pin =
"H"). The TESTI pin is not included.
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[AK7738]
11. Switching Characteristics
1. System Clock
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V; CL=20pF)
Parameter Symbol min typ max Unit
XTI Input Timing fXTI 11.2896 18.432 MHz
a) X'tal Oscillator fXTI %
Input Frequency 40 50 60
b) XTI Clock Input 0.256 MHz
Duty Cycle 24.576
Input Frequency MHz
%
CLKO Output Timing fCLKO 2.048 24.576
Output Frequency kHz
Duty Cycle dCLKO 50 MHz
ns
LRCK/BICK Input Timing (Slave Mode) ns
LRCK Input Timing kHz
ns
Frequency fs 8 192 %
BICK Input Timing MHz
%
Frequency (Note 44) fBCLK 0.256 24.576
Pulse Width Low tBCLKL 0.4/fBCLK
Pulse Width High tBCLKH 0.4/fBCLK
LRCK/BICK Output Timing (PLL Master Mode)
LRCK Output Timing
Frequency fs 8 192
Pulse Width High
PCM Mode tLRCKH 1/fBCLK
Except PCM Mode tLRCKH 50
BICK Output Timing
Frequency (Note 44) fBCLK 0.256 24.576
Duty dBCLK 50
Note 44. Required to meet the following expression: fBCLK 2 x fs x (Input/Output Data Length).
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1/fXTI [AK7738]
1/fXTI
VIH3
XTI VIL3
1/fs
1/fs
LRCK1~5 VIH1, 2, 3
VIL1, 2, 3
BICK1~5 1/fBCLK VIH1, 2, 3
1/fBCLK VIL1, 2, 3
tBCLKH tBCLKL
Figure 5. System Clock Timing
2. Power Down
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V)
Parameter Symbol Min typ max Unit
PDN Pluse Width (Note 45) tRST 600 ns
Note 45. The PDN pin must be "L" when power up the AK7738.
PDN
tRST
VIL2
Figure 6. Reset Timing
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[AK7738]
3. Serial Data Interface (SDIN1 ~ SDIN6, SDOUT1 ~ SDOUT6)
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V; CL=20pF)
Parameter Symbol min typ max Unit
Slave Mode
Delay Time from BICK "" to LRCK (Note 46) tBLRD 10 ns
Delay Time from LRCK to BICK "" (Note 46) tLRBD 10 ns
Serial Data Input Latch Setup Time tBSIDS 10 ns
Serial Data Input Latch Hold Time tBSIDH 5 ns
Delay Time from BICK""to Serial Data Output tBSOD1 20 ns
(Note 47)
Delay Time from BICK ""to Serial Data Output tBSOD2 5 30 ns
(Note 46, Note 48)
Master Mode
BICK frequency fBCLK - 32, 48, 64, - fs
128, 256
BICK Duty cycle 50 %
Delay Time from BICK "" to LRCK (Note 47) tMBL -10 10 ns
Serial Data Input Latch Setup Time tBSIDS 20 ns
Serial Data Input Latch Hold Time tBSIDH 10 ns
Delay Time from BICK""to Serial Data Output tBSOD 10 ns
(Note 47, Note 48)
Note 46. It is measured from BICK "" when the BICK polarity is inverted by setting BCKPx bit = "1".
Note 47. It is measured from BICK "" when the BICK polarity is inverted by setting BCKPx bit = "1".
Note 48. Set SDOPHx bit to "1" and the data should be output based on BICK "" when using TDM256
mode with 96kHz sampling frequency in slave mode. SDOPHx bit must be set to "0" in master
mode.
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[AK7738]
3-1. Slave Mode
LRCK(I) VIH
D VIL
tBLRD tLRBD D
D VIH
BICK(I)
VIL
D
tBSIDS tBSIDH
D
SDIN1~6 VIH
D VIL
Figure 7. Serial Interface Input Timing in Slave Mode D
LRCK(I) tBLRD tLRBD VIH
BICK(I) D VIL
SDOUT1~6
tBSOD1 tBSOD1 VIH
D D VIL
50%TVDD1/2
50%VDD33
Figure 8. Serial Interface Output Timing in Slave Mode (SDOPHx bit = "0")
LRCK(I) tBLRD tLRBD VIH
BICK(I) D VIL
SDOUT1~6
tBSOD2 tBSOD2 VIH
D D VIL
50%TVDD1/2
50%VDD33
Figure 9. Serial Interface Output Timing in Slave Mode (SDOPHx bit = "1")
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[AK7738]
3-2. Master Mode 50%TVDD1/2
50%VDD33
LRCK(O)
BICK(O) tMBL tMBL
SDIN1~6 D
50%TVDD1/2
tBSIDS 50%VDD33
tBSIDH
VIH
D VIL
Figure 10. Serial Interface Input Timing in Master Mode
LRCK(O) 50%TVDD1/2
50%VDD33
BICK(O) tBSOD tBSOD 50%TVDD1/2
SDOUT1~6 D D 50%VDD33
50%TVDD1/2
50%VDD33
Figure 11. Serial Interface Output Timing in Master Mode (SDOPHx bit = "0")
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[AK7738]
4. SPI Interface
4-1. Clock Reset (CKRESETN bit = "0")
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V; CL=20pF)
Parameter Symbol min typ max Unit
P Interface Signal
SCLK Frequency (Note 51) fSCLK 3.5 MHz
SCLK Low-level Width tSCLKL 120 ns
SCLK High-level Width tSCLKH 120 ns
Microcontroller AK7738
CSN High-level Width tWRQH 300 ns
From CSN "" to PDN "" tRST 360 ns
From PDN "" to CSN "" tIRRQ 1 ms
From CSN "" to SCLK "" tWSC 300 ns
From SCLK "" to CSN "" tSCW 480 ns
SI Latch Setup Time tSIS 120 ns
SI Latch Hold Time tSIH 120 ns
AK7738 Microcontroller tSOS 120 ns
Delay Time from SCLK "" to SO Output
SO Output Hold Time from SCLK "" (Note 49) tSOH 120 ns
Note 49. Except when writing the 24th bit (8 bits command + 16 bits address) of the command code. This
will be the 8th bit (8 bits command) with "write preparation data read command (24H and 25H)".
4-2. PLL Lock (CKRESETN bit = "1" and PLL is locked)
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V; CL=20pF)
Parameter Symbol min typ max Unit
P Interface Timing (SPI mode)
SCLK Frequency (Note 50) (Note 51) fSCLK 7 MHz
SCLK Low Level Width tSCLKL 60 ns
SCLK High Level Width tSCLKH 60 ns
P AK7738
CSN High Level Width tWRQH 150 ns
From CSN ""to PDN "" tRST 180 ns
From PDN ""to CSN "" tIRRQ 1 ms
From CSN ""to SCLK "" tWSC 150 ns
From SCLK ""to CSN "" tSCW 240 ns
SI Latch Setup Time tSIS 60 ns
SI Latch Hold Time tSIH 60 ns
AK7738 P
Delay Time from SCLK ""to SO Output tSOS 60 ns
SO Output Hold Time from SCLK "" (Note 49) tSOH 60 ns
Note 50. It takes maximum 10ms to lock PLL after setting CKRESETN bit = "0" "1".
Note 51. Control registers can always be accessed by a maximum speed of 7MHz. Interfacing with the
AK7738 except control registers should be made at a maximum speed of 3.5MHz when PLL is
unlocked or at a maximum speed of 7MHz when PLL is locked. It is necessary to set DLRDY bit
to "1" when interfacing with the AK7738 except control registers if PLL is unlocked.
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[AK7738]
SCLK tSCLKL tSCLKH VIH2
VIL2
PDN 1/fSCLK
CSN VIH2
1/fSCLK VIL2
VIH2
VIL2
tRST tIRRQ
Figure 12. SPI Interface Timing 1
CSN tWRQH VIH2
VIL2
SI tSIS tSIH
SCLK VIH2
VIL2
tWSC tSCW tWSC tSCW VIH2
VIL2
Figure 13. SPI Interface Timing 2 (Microcontroller AK7738)
VIH2
SCLK VIL2
SO VIH2
VIL2
tSOS tSOH
Figure 14. SPI Interface Timing 3 (AK7738 Microcontroller)
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[AK7738]
5. I2C Interface
(Ta=25C; AVDD=3.0~3.6V; LVDD=3.0~3.6V; TVDD1=1.7~3.6V; TVDD2=1.7~3.6V;
VDD33=3.0~3.6V; AVSS=DVSS1=DVSS2=DVSS3=0V)
Symbol min typ max Unit
Parameter
I2C Timing fSCL - - 400 kHz
SCL clock frequency
Bus Free Time Between Transmissions tBUF 1.3 - - s
Start Condition Hold Time (prior to first Clock pulse)
Clock Low Time tHD:STA 0.6 - - s
Clock High Time
Setup Time for Repeated Start Condition tLOW 1.3 - - s
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising tHIGH 0.6 - - s
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines tSU:STA 0.6 - - s
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed By Input Filter tHD:DAT 0 - - s
Capacitive load on bus
tSU:DAT 0.1 - - s
tR - - 0.3 s
tF - - 0.3 s
tSU:STO 0.6 - - s
tSP 0 - 50 ns
Cb - - 400 pF
Symbol min typ max Unit
Parameter
I2C Timing fSCL - - 1 MHz
SCL clock frequency
Bus Free Time Between Transmissions tBUF 0.5 - - s
Start Condition Hold Time (prior to first Clock pulse)
Clock Low Time tHD:STA 0.26 - - s
Clock High Time
Setup Time for Repeated Start Condition tLOW 0.5 - - s
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising tHIGH 0.26 - - s
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines tSU:STA 0.26 - - s
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed By Input Filter tHD:DAT 0 - - s
Capacitive load on bus
tSU:DAT 0.05 - - s
tR - - 0.12 s
tF - - 0.12 s
tSU:STO 0.26 - - s
tSP 0 - 50 ns
Cb - - 550 pF
SDA VIH2
VIL2
tBUF tLOW tR tHIGH tF
tSP
SCL tHD:DAT tSU:DAT tSU:STA
Start VIH2
tHD:STA VIL2
Stop Start
tSU:STO
Figure 15. I2C-bus Interface Timing Stop
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[AK7738]
12. Package
Outline Dimensions
64-pin LQFP (Unit: mm)
Material and Lead Finish
Package: Epoxy
Lead frame: Copper
Lead-finish: Soldering (Pb free) plate
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[AK7738]
Marking
AKM
AK7738VQ
XXXXXXX
64
1
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK7738VQ
4) Asahi Kasei Logo
13. Revision History
Date (Y/M/D) Revision Reason Page Contents
15/01/08 00 First Edition
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[AK7738]
Thank you for your access to AKM product information.
More detail product information is available, please contact
our sales office or authorized distributors.
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation ("AKM") reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application
of AKM product stipulated in this document ("Product"), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor grants
any license to any intellectual property rights or any other rights of AKM or any third party with
respect to the information in this document. You are fully responsible for use of such information
contained in this document in your product design or applications. AKM ASSUMES NO
LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM
THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which
may cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace
industry, medical equipment, equipment used for automobiles, trains, ships and other
transportation, traffic signaling equipment, equipment used to control combustions or explosions,
safety devices, elevators and escalators, devices related to electric power, and equipment used in
finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in
writing.
3. Though AKM works continually to improve the Product's quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and safeguards
for your hardware, software and systems which minimize risk and avoid situations in which a
malfunction or failure of the Product could cause loss of human life, bodily injury or damage to
property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and
regulations. The Products and related technology may not be used for or incorporated into any
products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or
foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation,
the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
015000122-E-00-PB 2015/01
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