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AGLP060-V5VQG289ES

器件型号:AGLP060-V5VQG289ES
器件类别:半导体    可编程逻辑器件   
厂商名称:Actel
厂商官网:http://www.actel.com/
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器件描述

FPGA, 3120 CLBS, 125000 GATES, PBGA289

现场可编程门阵列, 3120 CLBS, 125000 门, PBGA289

参数
功能数量1
端子数量289
最大工作温度85 Cel
最小工作温度-40 Cel
最大供电/工作电压1.58 V
最小供电/工作电压1.42 V
额定供电电压1.5 V
加工封装描述14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-289
无铅Yes
欧盟RoHS规范Yes
状态ACTIVE
工艺CMOS
包装形状SQUARE
包装尺寸GRID ARRAY, THIN PROFILE, FINE PITCH
表面贴装Yes
端子形式BALL
端子间距0.8000 mm
端子涂层NOT SPECIFIED
端子位置BOTTOM
包装材料PLASTIC/EPOXY
温度等级INDUSTRIAL
组织3120 CLBS, 125000 GATES
可配置逻辑模块数量3120
可编程逻辑类型FIELD PROGRAMMABLE GATE ARRAY
等效门电路数量125000

文档预览

v1.3
IGLOO PLUS Low-Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
5 µW Power Consumption in Flash*Freeze Mode
Low-Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Configurable Hold Previous State, Tristate, HIGH, or LOW
State per I/O in Flash*Freeze Mode
• Easy Entry To / Exit From Ultra-Low-Power Flash*Freeze Mode
®
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—4 Banks per Chip on All
IGLOO
®
PLUS Devices
• Single-Ended
I/O
Standards:
LVTTL,
LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V
• Selectable Schmitt Trigger Inputs
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Small-Footprint Packages across the IGLOO
PLUS Family
• Six CCC Blocks, One with an Integrated PLL
• Configurable
Phase
Shift, Multiply/Divide,
Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Feature Rich
• 30 k to 125 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 212 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)
AGLP030
30 k
256
792
5
1k
6
4
120
CS201, CS289
VQ128
AGLP060
60 k
512
1,584
10
18
4
Yes
1k
1
18
4
157
CS201, CS289
VQ176
AGLP125
125 k
1,024
3,120
16
36
8
Yes
1k
1
18
4
212
CS281, CS289
Table 1-1 •
IGLOO PLUS Product Family
IGLOO PLUS Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM kbits (1,024 bits)
4,608-Bit Blocks
Secure (AES) ISP
FlashROM Bits
Integrated PLL in CCCs
1
VersaNet Globals
2
I/O Banks
Maximum User I/Os
Package Pins
CS
VQ
Notes:
1. AGLP060 in CS201 does not support the PLL.
2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.
† The AGLP030 device does not support this feature.
December 2008
© 2008 Actel Corporation
I
I/Os Per Package
1
IGLOO PLUS Devices
Package
CS201
CS281
CS289
VQ128
VQ176
120
120
101
AGLP030
AGLP060
Single-Ended I/Os
157
157
137
212
212
AGLP125
Note:
When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of
single-ended user I/Os available is reduced by one.
Table 1-2 •
Package Dimensions
Package
Length × Width (mm/mm)
Nominal Area (mm
2
)
Pitch (mm)
Height (mm)
CS201
8×8
64
0.5
0.89
CS281
10 × 10
100
0.5
1.05
CS289
14 × 14
196
0.8
1.20
VQ128
14 × 14
196
0.4
1.0
VQ176
20 × 20
400
0.4
1.0
II
v1.3
IGLOO PLUS Low-Power Flash FPGAs
IGLOO PLUS Ordering Information
AGLP125
V2
_
CS
G
289
I
Application (Temperature Range)
Blank =
Commercial
(0°C to +70°C ambient temperature)
I = Industrial (
40°C to +85°C ambient temperature)
PP = Pre-Production
ES = Engineering
Sample
(room temperature only)
Package Lead
Count
Lead-Free Packaging
Blank =
Standard
Packaging
G=
RoHS-Compliant Packaging
Package Type
CS
=
Chip Scale
Package (0.5 mm and 0.8 mm pitches)
VQ = Very Thin Quad Flat Pack (0.4 mm pitch)
Speed Grade
F = 20%
Slower
than
Standard*
Blank =
Standard
Supply
Voltage
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
AGLP030 = 30,000
System Gates
AGLP060 =
60,000 System Gates
AGLP125 = 125,000
System Gates
Notes:
1. Marking information: IGLOO PLUS V2 devices do not have a V2 marking, but IGLOO PLUS V5 devices are marked
accordingly.
2. The DC and switching characteristics for the –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only
supported in the Commercial temperature range.
3. "G" indicates RoHS-compliant packages.
v1.3
III
Temperature Grade Offerings
Package
CS201
CS281
CS289
VQ128
VQ176
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
AGLP030
C, I
C, I
C, I
AGLP060
C, I
C, I
C, I
AGLP125
C, I
C, I
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
2
I
3
Notes:
1. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only
supported in the Commercial temperature range.
2. C = Commercial temperature range: 0°C to 70°C ambient temperature.
3. I = Industrial temperature range: –40°C to 85°C ambient temperature.
Contact your local Actel representative for device availability:
http://www.actel.com/company/contact/default.aspx.
–F
1
Std.
IV
v1.3
1 – IGLOO PLUS Device Family Overview
General Description
The IGLOO PLUS family of flash FPGAs, based on a 130 nm flash process, offers the lowest power
FPGA, a single-chip solution, small-footprint packages, reprogrammability, and an abundance of
advanced features.
The Flash*Freeze technology used in IGLOO PLUS devices enables entering and exiting an ultra-
low-power mode that consumes as little as 5 µW while retaining the design information, SRAM
content, registers, and I/O states. Flash*Freeze technology simplifies power management through
I/O and clock management with rapid recovery to operation mode.
The Low Power Active capability (static idle) allows for ultra-low-power consumption while the
IGLOO PLUS device is completely functional in the system. This allows the IGLOO PLUS device to
control system power management based on external inputs (e.g., scanning for keyboard stimulus)
while consuming minimal power.
Nonvolatile flash technology gives IGLOO PLUS devices the advantage of being a secure, low-
power, single-chip solution that is live at power-up (LAPU). IGLOO PLUS is reprogrammable and
offers time-to-market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
IGLOO PLUS devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well
as clock conditioning circuitry based on an integrated phase-locked loop (PLL). IGLOO PLUS devices
have up to 125 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 212
user I/Os. The AGLP030 devices have no PLL or RAM support.
Flash*Freeze Technology
The IGLOO PLUS device offers unique Flash*Freeze technology, allowing the device to enter and
exit ultra-low-power Flash*Freeze mode. IGLOO PLUS devices do not need additional components
to turn off I/Os or clocks while retaining the design information, SRAM content, registers, and I/O
states. Flash*Freeze technology is combined with in-system programmability, which enables users
to quickly and easily upgrade and update their designs in the final stages of manufacturing or in
the field. The ability of IGLOO PLUS V2 devices to support a wide range of core and I/O voltages
(1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total
system power.
During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state,
tristate, or set as HIGH or LOW.
The availability of low-power modes, combined with reprogrammability, a single-chip and single-
voltage solution, and availability of small-footprint, high-pin-count packages, make IGLOO PLUS
devices the best fit for portable electronics.
Flash Advantages
Low Power
IGLOO PLUS devices exhibit power characteristics similar to those of an ASIC, making them an ideal
choice for power-sensitive applications. IGLOO PLUS devices have only a very limited power-on
current surge and no high-current transition period, both of which occur on many FPGAs.
IGLOO PLUS devices also have low dynamic power consumption to further maximize power savings;
power is even further reduced by the use of a 1.2 V core voltage.
Low dynamic power consumption, combined with low static power consumption and Flash*Freeze
technology, gives the IGLOO PLUS device the lowest total system power offered by any FPGA.
v1.3
1-1

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