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ADSP-21365SKBCZENG

器件型号:ADSP-21365SKBCZENG
厂商名称:ADI [Analog Devices Inc]
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器件描述

SHARC Processor

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a
SUMMARY
Preliminary Technical Data
High performance 32-bit/40-bit floating point processor
optimized for high performance automotive audio
processing
Audio decoder and post processor-algorithm support with
32-bit floating-point implementations
Non-volatile memory may be configured to support audio
decoders and post processor-algorithms like PCM, Dolby
Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES,
MPEG2 AAC, MPEG2 2channel, MP3, and functions like
Bass management, Delay, Speaker equalization, Graphic
equalization, and more. Decoder/post-processor algo-
rithm combination support will vary depending upon the
chip version and the system configurations. Please visit
www.analog.com/SHARC
SHARC
®
Processor
ADSP-21365/ADSP-21366
Single-Instruction Multiple-Data (SIMD) computational
architecture
On-chip memory—3M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21365/6 is available with a 333 MHz core instruc-
tion rate and unique audio centric peripherals such as the
Digital Audio Interface, S/PDIF transceiver, DTCP (Digital
Content Transmission Protocol) available on the ADSP-
21365 only, serial ports, 8-channel asynchronous sample
rate converter, precision clock generators and more. For
complete ordering information, see
Ordering Guide on
page 51
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 X 48-BIT
4 BLOCKS OF ON-CHIP MEMORY
BLOCK 0
SRAM
1M BIT
BLOCK 1
SRAM
1M BIT
BLOCK 2
SRAM
0.5M BIT
BLOCK 3
SRAM
0.5M BIT
ROM
2M BIT
ROM
2M BIT
DAG1
8X4X32
DAG2
8X4X32
PROGRAM
SEQUENCER
ADDR
DATA
ADDR
DATA
ADDR
DATA
ADDR
DATA
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
32
32
64
DM DATA BUS
64
IOA
IOD
IOA
IOD
IOA
IOD
IOA
IOD
PX REGISTER
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
IOP REGISTERS
(MEMORY MAPPED)
6
JTAG TEST & EMULATION
SPI
SPORTS
IDP
PCG
TIMERS
SRC
SPDIF
DTCP
SIGNAL
ROUTING
UNIT
I/O PROCESSOR
AND PERIPHERALS
S
Figure 1. Functional Block Diagram – Processor Core
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SEE “ADSP-21365/6 MEMORY
AND I/O INTERFACE FEATURES”
SECTION FOR DETAILS
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781.329.4700
www.analog.com
Fax:781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADSP-21365/6
KEY FEATURES – PROCESSOR CORE
At 333 MHz (3.0 ns) core instruction rate, the ADSP-21365/6
performs 2 GFLOPS/666 MMACS
3M bit on-chip SRAM (1M Bit in blocks 0 and 1, and 0.50M Bit
in blocks 2 and 3) for simultaneous access by the core pro-
cessor and DMA
4M bit on-chip mask-programmable ROM (2M bit in block 0
and 2M bit in block 1)
Dual Data Address Generators (DAGs) with modulo and bit-
reverse addressing
Zero-overhead looping with single-cycle loop setup, provid-
ing efficient program sequencing
Single Instruction Multiple Data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
the assembly level
Parallelism in busses and computational units allows sin-
gle cycle execution (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch
Transfers between memory and core at a sustained 5.4G
bytes/s bandwidth at 333 MHz core instruction rate
Preliminary Technical Data
Up to 12 TDM stream support, each with 128 channels per
frame
Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the pro-
cessor core, configurable as eight channels of serial data or
seven channels of serial data and a single channel of up to
a 20-bit wide parallel data
Signal routing unit provides configurable and flexible con-
nections between all DAI components–six serial ports, one
SPI port, eight channels of asynchronous sample rate con-
verters, an S/PDIF receiver/transmitter, DTCP (Digital
Content Transmission Protocol (ADSP-21365 only), three
timers, an SPI port,10 interrupts, six flag inputs, six flag
outputs, and 20 SRU I/O pins (DAI_Px)
Two Serial Peripheral Interfaces (SPI): primary on dedicated
pins, secondary on DAI pins provide:
Master or slave serial boot through primary SPI , Full-
duplex operation, Master-Slave mode multi-master sup-
port, Open drain outputs, Programmable baud rates, clock
polarities and phases
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
DEDICATED AUDIO COMPONENTS
S/PDIF Compatible Digital Audio receiver/transmitter sup-
ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left-justified, I
2
S or right-justified serial data input with
16, 18, 20 or 24-bit word widths (transmitter)
Two channel mode and Single Channel Double Frequency
(SCDF) mode
Digital Transmission Content Protection (DTCP)—a crypto-
graphic protocol for protecting audio content from
unauthorized copying, intercepting, and tampering
(ADSP-21365 only).
Sample Rate Converter (SRC) Contains a Serial Input Port, De-
emphasis Filter, Sample Rate Converter (SRC) and Serial
Output Port providing up to -128db SNR performance
Supports Left Justified, I
2
S, TDM and Right Justified 24, 20,
18 and 16-bit serial formats (input)
Pulse Width Modulation provides:
16 PWM outputs configured as four groups of four outputs
Supports center-aligned or edge-aligned PWM waveforms
Can generate complementary signals on two outputs in
paired mode or independent signals in non-paired mode
ROM Based Security features include:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball Mini-BGA and 144-lead LQFP Packages
(see
Ordering Guide on page 51)
INPUT/OUTPUT FEATURES
DMA Controller supports:
25 DMA channels for transfers between ADSP-21365/6 inter-
nal memory and a variety of peripherals
32-bit DMA transfers at core clock speed, in parallel with full-
speed processor execution
Asynchronous parallel port provides access to asynchronous
external memory
16 multiplexed address/data lines support 24-bit address
external address range with 8-bit data or 16-bit address
external address range with 16-bit data
55M byte per sec transfer rate
External memory access in a dedicated DMA channel
8- to 32-bit and 16- to 32-bit packing options
Programmable data cycle duration: 2 to 31 CCLK
Digital Audio Interface (DAI) includes six serial ports, two
Precision Clock Generators, an Input Data Port, three tim-
ers, an S/PDIF transceiver, a DTCP cipher (ADSP-21365
only), an 8-channel asynchronous sample rate converter,
an SPI port, and a Signal Routing Unit
Six dual data line serial ports that operate at up to 50M bits/s
on each data line — each has a clock, frame sync and two
data lines that can be configured as either a receiver or
transmitter pair
Left-justified Sample Pair and I
2
S Support, programmable
direction for up to 24 simultaneous receive or transmit
channels using two I
2
S compatible stereo devices per serial
port
TDM support for telecommunications interfaces including
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
Rev. PrA |
Page 2 of 54 | September 2004
Preliminary Technical Data
GENERAL DESCRIPTION
The ADSP-21365/6 SHARC processors are members of the
SIMD SHARC family of DSPs that feature Analog Devices'
Super Harvard Architecture. The ADSP-21365/6 are source
code compatible with the ADSP-2126x, and ADSP-2116x, DSPs
as well as with first generation ADSP-2106x SHARC processors
in SISD (Single-Instruction, Single-Data) mode. The ADSP-
21365/6 are 32-bit/40-bit floating point processors optimized
for high performance automotive audio applications with its
large on-chip SRAM and mask-programmable ROM, multiple
internal buses to eliminate I/O bottlenecks, and an innovative
Digital Audio Interface (DAI).
As shown in the functional block diagram
on page 1,
the
ADSP-21365/6 uses two computational units to deliver a signif-
icant performance increase over the previous SHARC
processors on a range of signal processing algorithms. Fabri-
cated in a state-of-the-art, high speed, CMOS process, the
ADSP-21365/6 processor achieves an instruction cycle time of
3.0 ns at 333 MHz. With its SIMD computational hardware, the
ADSP-21365/6 can perform 2 GFLOPS running at 333 MHz.
Table 1
shows performance benchmarks for the ADSP-21365/6.
Table 1. ADSP-21365/6 Benchmarks (at 333 MHz)
Speed
(at 333 MHz)
1024 Point Complex FFT (Radix 4, with reversal) 27.9
µs
FIR Filter (per tap)
1
1.5 ns
IIR Filter (per biquad)
1
6.0 ns
Matrix Multiply (pipelined)
[3x3] × [3x1]
13.5 ns
[4x4] × [4x1]
23.9 ns
Divide (y/×)
10.5 ns
Inverse Square Root
16.3 ns
1
ADSP-21365/6
• On-Chip mask-programmable ROM (4M bit)
• 8- or 16-bit Parallel port that supports interfaces to off-chip
memory peripherals
• JTAG test access port
The block diagram of the ADSP-21365/6
on page 6,
illustrates
the following architectural features:
• DMA controller
• Six full duplex serial ports
• Two SPI-compatible interface ports—primary on dedi-
cated pins, secondary on DAI pins
• Digital Audio Interface that includes two precision clock
generators (PCG), an input data port (IDP), an S/PDIF
receiver/transmitter, eight channels asynchronous sample
rate converters, DTCP cipher, six serial ports, eight serial
interfaces, a 20-bit parallel input port, 10 interrupts, six flag
outputs, six flag inputs, three timers, and a flexible signal
routing unit (SRU) buses
Figure 2 on page 4
shows one sample configuration of a SPORT
using the precision clock generators to interface with an I
2
S
ADC and an I
2
S DAC with a much lower jitter clock than the
serial port would generate itself. Many other SRU configura-
tions are possible.
Benchmark Algorithm
ADSP-21365/6 FAMILY CORE ARCHITECTURE
The ADSP-21365/6 is code compatible at the assembly level
with the ADSP-2126x, ADSP-21160 and ADSP-21161, and with
the first generation ADSP-2106x SHARC processors. The
ADSP-21365/6 shares architectural features with the ADSP-
2126x and ADSP-2116x SIMD SHARC processors, as detailed
in the following sections.
SIMD Computational Engine
The ADSP-21365/6 contains two computational processing ele-
ments that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter and reg-
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive signal processing algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Assumes two files in multichannel SIMD mode
The ADSP-21365/6 continues SHARC’s industry leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram of the ADSP-21365/6
on page 1,
illustrates
the following architectural features:
• Two processing elements, each of which comprises an
ALU, Multiplier, Shifter and Data Register File
• Data Address Generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
• Three Programmable Interval Timers with PWM Genera-
tion, PWM Capture/Pulse width Measurement, and
External Event Counter Capabilities
• On-Chip SRAM (3M bit)
Rev. PrA |
Page 3 of 54 |
September 2004
ADSP-21365/6
ADSP -21365/6
CLK OU T
C LOC K
2
2
3
C LK IN
X TA L
C LK _C FG1-0
B OOTC FG1 -0
FLA G3-1
RD
WR
FLA G0
A DC
(OPTI ONA L)
C LK
FS
S D AT
A LE
AD 1 5-0
Preliminary Technical Data
LA TCH
A DD R
D ATA
OE
WE
CS
PA R A LLEL
POR T
R AM , ROM
BOO T R OM
I /O D EVI CE
CONTROL
DATA
ADDRESS
D A I_P1
DA I_ P2
DA I_ P3
SR U
D A I_P 18
D AI _P 19
DA I_ P2 0
S C LK 0
S FS0
S D 0A
S D 0B
SP OR T0-5
TIME R S
SPD IF
SR C
ID P
S PI
D AC
(OPTI ONA L)
C LK
FS
S D AT
C LK
FS
DAI
R ES ET
PC GA
P CG B
JTA G
6
Figure 2. ADSP-21365/6 System Sample Configuration
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21365/6 features an enhanced Harvard architecture
in which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see
Figure 1 on page 1).
With the ADSP-21365/6’s separate
program and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin-
gle cycle.
Instruction Cache
The ADSP-21365/6 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.
Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21365/6’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
Rev. PrA |
Page 4 of 54 | September 2004
Preliminary Technical Data
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21365/6 con-
tain sufficient registers to allow the creation of up to 32 circular
buffers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over-
head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
ADSP-21365/6
On-Chip Memory
The ADSP-21365/6 contains three megabits of internal SRAM
and four megabits of internal mask-programmable ROM. Each
block can be configured for different combinations of code and
data storage (see
Table 2).
Each memory block supports single-
cycle, independent accesses by the core processor and I/O pro-
cessor. The ADSP-21365/6 memory architecture, in
combination with its separate on-chip buses, allow two data
transfers from the core and one from the I/O processor, in a sin-
gle cycle.
The ADSP-21365/6’s, SRAM can be configured as a maximum
of 96K words of 32-bit data, 192K words of 16-bit data, 64K
words of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to three megabits. All of the memory can
be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
floating-point storage format is supported that effectively dou-
bles the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for-
mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21365/6 can conditionally execute a multiply, an add,
and a subtract in both processing elements while branching and
fetching up to four 32-bit values from memory—all in a single
instruction.
ADSP-21365/6 MEMORY AND I/O INTERFACE
FEATURES
The ADSP-21365/6 adds the following architectural features to
the SIMD SHARC family core.
Table 2. ADSP-21365/6 Internal Memory Space
IOP Registers 0x0000 0000 - 0003 FFFF
Long Word (64 bits)
BLOCK 0 ROM
0x0004 0000–0x0004 7FFF
Reserved
0x0004 8000–0x0004 BFFF
BLOCK 0 RAM
0x0004 C000–0x0004 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 7FFF
Reserved
0x0005 8000–0x0005 BFFF
BLOCK 1 RAM
0x0005 C000–0x0005 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 1FFF
Reserved
0x0006 2000– 0x0006 FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 1FFF
Reserved
0x0007 2000– 0x0007 FFFF
BLOCK 3 RAM
0x000E 0000–0x000E 2AAA
BLOCK 1 RAM
0x000B 0000–0x000B 5555
BLOCK 2 RAM
0x000C 0000–0x000C 2AAA
BLOCK 0 RAM
0x0009 0000–0x0009 5555
BLOCK 1 ROM
0x000A 0000–0x000A AAAA
Extended Precision Normal or Normal Word (32 bits)
Instruction Word (48 bits)
BLOCK 0 ROM
0x0008 0000–0x0008 AAAA
BLOCK 0 ROM
0x0008 0000–0x0008 FFFF
Reserved
0x0009 0000–0x0009 7FFF
BLOCK 0 RAM
0x0009 8000–0x0009 FFFF
BLOCK 1 ROM
0x000A 0000– 0x000A FFFF
Reserved
0x000B 0000– 0x000B 7FFF
BLOCK 1 RAM
0x000B 8000–0x000B FFFF
BLOCK 2 RAM
0x000C 0000–0x000C 3FFF
Reserved
0x000C 4000– 0x000D FFFF
BLOCK 3 RAM
0x000E 0000–0x000E 3FFF
Reserved
0x000E 4000–0x000F FFFF
Short Word (16 bits)
BLOCK 0 ROM
0x0010 0000–0x0011 FFFF
Reserved
0x0012 0000–0x0012 FFFF
BLOCK 0 RAM
0x0013 0000–0x0013 FFFF
BLOCK 1 ROM
0x0014 0000–0x0015 FFFF
Reserved
0x0016 0000–0x0016 FFFF
BLOCK 1 RAM
0x0017 0000–0x0017 FFFF
BLOCK 2 RAM
0x0018 0000–0x0018 7FFF
Reserved
0x0018 8000–0x001B FFFF
BLOCK 3 RAM
0x001C 0000–0x001C 7FFF
Reserved
0x001C 8000–0x001F FFFF
Reserved
0x0020 0000–0xFFFF FFFF
Rev. PrA |
Page 5 of 54 |
September 2004

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