电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索
 

93C86CT-I/MC

器件型号:93C86CT-I/MC
器件类别:存储    存储   
厂商名称:Microchip(微芯科技)
厂商官网:https://www.microchip.com
标准:
下载文档

器件描述

128 X 8 MICROWIRE BUS SERIAL EEPROM, PDIP8

128 × 8 总线串行电可擦除只读存储器, PDIP8

参数
是否无铅不含铅
是否Rohs认证符合
零件包装代码DFN
包装说明HVSON, SOLCC8,.11,20
针数8
Reach Compliance Codecompliant
Factory Lead Time5 weeks
备用内存宽度8
最大时钟频率 (fCLK)3 MHz
数据保留时间-最小值200
耐久性1000000 Write/Erase Cycles
JESD-30 代码R-PDSO-N8
JESD-609代码e3
长度3 mm
内存密度16384 bit
内存集成电路类型EEPROM
内存宽度16
湿度敏感等级1
功能数量1
端子数量8
字数1024 words
字数代码1000
工作模式SYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织1KX16
封装主体材料PLASTIC/EPOXY
封装代码HVSON
封装等效代码SOLCC8,.11,20
封装形状RECTANGULAR
封装形式SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
并行/串行SERIAL
峰值回流温度(摄氏度)260
电源5 V
认证状态Not Qualified
座面最大高度1 mm
串行总线类型MICROWIRE
最大待机电流0.000001 A
最大压摆率0.003 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Matte Tin (Sn)
端子形式NO LEAD
端子节距0.5 mm
端子位置DUAL
处于峰值回流温度下的最长时间40
宽度2 mm
最长写入周期时间 (tWC)2 ms
写保护HARDWARE/SOFTWARE
Base Number Matches1

文档预览

93AA76A/B/C, 93LC76A/B/C,
93C76A/B/C
8K Microwire Compatible Serial EEPROM
Device Selection Table
Part Number
93AA76A
93AA76B
93LC76A
93LC76B
93C76A
93C76B
93AA76C
93LC76C
93C76C
V
CC
Range
1.8-5.5
1.8-5-5
2.5-5.5
2.5-5.5
4.5-5.5
4.5-5.5
1.8-5.5
2.5-5.5
4.5-5.5
ORG Pin
No
No
No
No
No
No
Yes
Yes
Yes
PE Pin
No
No
No
No
No
No
Yes
Yes
Yes
Word Size
8-bit
16-bit
8-bit
16-bit
8-bit
16-bit
8- or 16-bit
8- or 16-bit
8- or 16-bit
Temp Ranges
I
I
I, E
I, E
I, E
I, E
I
I, E
I, E
Packages
P, SN, ST, MS, OT
P, SN, ST, MS, OT
P, SN, ST, MS, OT
P, SN, ST, MS, OT
P, SN, ST, MS, OT
P, SN, ST, MS, OT
P, SN, ST, MS, MC, MN
P, SN, ST, MS, MC, MN
P, SN, ST, MS, MC, MN
Features:
Low-Power CMOS Technology
ORG Pin to Select Word Size for ‘76C’ Version
1024 x 8-bit Organization ‘A’ Devices (no ORG)
512 x 16-bit Organization ‘B’ Devices (no ORG)
Program Enable Pin to Write-Protect the Entire
Array (‘76C’ version only)
Self-Timed Erase/Write Cycles (including
Auto-Erase)
Automatic ERAL Before WRAL
Power-On/Off Data Protection Circuitry
Industry Standard 3-Wire Serial I/O
Device Status Signal (Ready/
Busy
)
Sequential Read Function
1,000,000 Erase/Write Cycles
Data Retention > 200 Years
Pb-free and RoHS Compliant
Temperature Ranges Supported:
- Industrial (I)
-40°C to +85°C
- Automotive (E) -40°C to +125°C
Description:
The Microchip Technology Inc. 93XX76A/B/C devices
are 8Kbit, low-voltage, serial Electrically Erasable
PROMs (EEPROM). Word-selectable devices such as
the 93XX76C are dependent upon external logic levels
driving the ORG pin to set word size. The 93XX76A
devices provide dedicated 8-bit memory organization,
while the 93XX76B devices provide dedicated 16-bit
memory organization. A Program Enable (PE) pin allows
the user to write-protect the entire memory array.
Advanced CMOS technology makes these devices ideal
for low-power, nonvolatile memory applications. The
93XX Series is available in standard packages including
8-lead PDIP and SOIC, and advanced packaging includ-
ing 8-lead MSOP, 6-lead SOT-23, 8-lead 2x3 DFN/
TDFN and 8-lead TSSOP. All packages are Pb-free
(Matte Tin) finish.
Package Types (not to scale)
PDIP/SOIC
(P, SN)
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
PE
(1)
ORG
(1)
V
SS
DO
V
SS
DI
SOT-23
(OT)
1
2
3
6
5
4
V
CC
CS
CLK
Pin Function Table
Name
CS
CLK
DI
DO
V
SS
PE
ORG
V
CC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Program Enable – 93XX76C only
Memory Configuration – 93XX76C only
Power Supply
Function
TSSOP/MSOP
(ST, MS)
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
V
CC
PE
(1)
ORG
(1)
V
SS
CS
CLK
DI
DO
DFN/TDFN
(MC, MN)
1
2
3
4
8
7
6
5
V
CC
PE
ORG
V
SS
Note 1:
93XX76C only.
2003-2012 Microchip Technology Inc.
DS21796M-page 1
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins

4 kV
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.8V to 5.5V
Automotive (E): T
A
= -40°C to +125°C, V
CC
= +2.5V to 5.5V
Min
2.0
0.7 V
CC
-0.3
-0.3
2.4
V
CC
- 0.2
Typ
500
100
Max
V
CC
+1
V
CC
+1
0.8
0.2 V
CC
0.4
0.2
±1
±1
7
3
1
500
1
5
Units
V
V
V
V
V
V
V
V
A
A
pF
mA
A
mA
A
A
A
A
Conditions
V
CC
2.7V
V
CC
< 2.7V
V
CC
2.7V
V
CC
< 2.7V
I
OL
= 2.1 mA, V
CC
= 4.5V
I
OL
= 100
A,
V
CC
= 2.5V
I
OH
= -400
A,
V
CC
= 4.5V
I
OH
= -100
A,
V
CC
= 2.5V
V
IN
= V
SS
or V
CC
V
OUT
= V
SS
or V
CC
V
IN
/V
OUT
= 0V
(Note 1)
T
A
= 25°C, F
CLK
= 1 MHz
F
CLK
= 3 MHz, V
CC
= 5.5V
F
CLK
= 2 MHz, V
CC
= 2.5V
F
CLK
= 3 MHz, V
CC
= 5.5V
F
CLK
= 2 MHz, V
CC
= 3.0V
F
CLK
= 2 MHz, V
CC
= 2.5V
I – Temp
E – Temp
CLK = CS = 0V
ORG = DI = PE = V
SS
or V
CC
(Note 2) (Note 3)
(Note 1)
93AA76A/B/C, 93LC76A/B/C
93C76A/B/C
All parameters apply over the specified
ranges unless otherwise noted.
Param.
Symbol
No.
D1
D2
D3
D4
D5
D6
D7
D8
D9
V
IH
1
V
IH
2
V
IL
1
V
IL
2
V
OL
1
V
OL
2
V
OH
1
V
OH
2
I
LI
I
LO
C
IN
,
C
OUT
Parameter
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
Input leakage current
Output leakage current
Pin capacitance (all inputs/
outputs)
I
CC
write Write current
I
CC
read Read current
D10
I
CCS
Standby current
D11
V
POR
V
CC
voltage detect
1.5
3.8
V
V
Note 1:
2:
3:
This parameter is periodically sampled and not 100% tested.
ORG and PE pins not available on ‘A’ or ‘B’ versions.
Ready/
Busy
status must be cleared from DO; see
Section 3.4 “Data Out (DO)”.
DS21796M-page 2
2003-2012 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.8V to 5.5V
Automotive (E): T
A
= -40°C to +125°C, V
CC
= +2.5V to 5.5V
Min
Max
3
2
1
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
ms
Conditions
4.5V
V
CC
< 5.5V
2.5V
V
CC
< 4.5V
1.8V
V
CC
< 2.5V
4.5V
V
CC
< 5.5V
2.5V
V
CC
< 4.5V
1.8V
V
CC
< 2.5V
4.5V
V
CC
< 5.5V
2.5V
V
CC
< 4.5V
1.8V
V
CC
< 2.5V
4.5V
V
CC
< 5.5V
2.5V
V
CC
< 4.5V
1.8V
V
CC
< 2.5V
1.8V
V
CC
< 5.5V
1.8V
V
CC
< 5.5V
4.5V
V
CC
< 5.5V
2.5V
V
CC
< 4.5V
1.8V
V
CC
< 2.5V
4.5V
V
CC
< 5.5V
2.5V
V
CC
< 4.5V
1.8V
V
CC
< 2.5V
4.5V
V
CC
< 5.5V, CL = 100 pF
2.5V
V
CC
< 4.5V, CL = 100 pF
1.8V
V
CC
< 2.5V, CL = 100 pF
4.5V
V
CC
< 5.5V,
(Note 1)
1.8V
V
CC
< 4.5V,
(Note 1)
4.5V
V
CC
< 5.5V, CL = 100 pF
2.5V
V
CC
< 4.5V, CL = 100 pF
1.8V
V
CC
< 2.5V, CL = 100 pF
Erase/Write mode (AA and LC
versions)
Erase/Write mode
(93C versions)
ERAL mode, 4.5V
V
CC
5.5V
WRAL mode, 4.5V
V
CC
5.5V
All parameters apply over the specified
ranges unless otherwise noted.
Param.
Symbol
No.
A1
F
CLK
Parameter
Clock frequency
A2
T
CKH
Clock high time
200
250
450
100
200
450
50
100
250
0
250
50
100
250
50
100
250
A3
T
CKL
Clock low time
A4
T
CSS
Chip Select setup time
A5
A6
A7
T
CSH
T
CSL
T
DIS
Chip Select hold time
Chip Select low time
Data input setup time
A8
T
DIH
Data input hold time
A9
T
PD
Data output delay time
100
250
400
100
200
200
300
500
5
2
6
15
A10
A11
T
CZ
T
SV
Data output disable time
Status valid time
A12
A13
A14
A15
A16
Note 1:
2:
T
WC
T
WC
T
EC
T
WL
Program cycle time
Endurance
1M
cycles 25°C, V
CC
= 5.0V,
(Note 2)
This parameter is periodically sampled and not 100% tested.
This application is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which may be obtained from Microchip’s web
site at www.microchip.com.
2003-2012 Microchip Technology Inc.
DS21796M-page 3
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
FIGURE 1-1:
CS
V
IH
V
IL
V
IH
CLK
V
IL
T
DIS
V
IH
DI
V
IL
T
PD
DO
(Read)
DO
(Program)
V
OH
V
OL
V
OH
Status Valid
V
OL
T
SV
is relative to CS.
T
CZ
T
SV
T
PD
T
CZ
T
DIH
T
CSS
T
CKH
T
CKL
T
CSH
SYNCHRONOUS DATA TIMING
Note:
TABLE 1-3: INSTRUCTION SET FOR X16 ORGANIZATION (93XX76B OR 93XX76C WITH ORG =
1)
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
SB
1
1
1
1
1
1
1
Opcode
10
00
11
00
01
00
00
X
1
X
1
X
0
0
Address
A8 A7 A6 A5 A4 A3 A2 A1 A0
1
x
x
x
x
x
x
x
x
A8 A7 A6 A5 A4 A3 A2 A1 A0
0
X
X
X
X
X
X
X
X
A8 A7 A6 A5 A4 A3 A2 A1 A0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Data In
D15-D0
D15-D0
Data Out
D15-D0
High-Z
(RDY/
BSY
)
(RDY/
BSY
)
(RDY/
BSY
)
(RDY/
BSY
)
High-Z
Req. CLK
Cycles
29
13
13
13
29
29
13
TABLE 1-4: INSTRUCTION SET FOR X8 ORGANIZATION (93XX76A OR 93XX76C WITH ORG =
0)
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
SB
1
1
1
1
1
1
1
Opcode
10
00
11
00
01
00
00
X
1
X
1
X
0
0
Address
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1
x
x
x
x
x
x
x
x
x
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
x
x
x
x
x
x
x
x
x
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Data In
D7-D0
D7-D0
Data Out
D7-D0
High-Z
(RDY/
BSY
)
(RDY/
BSY
)
(RDY/
BSY
)
(RDY/
BSY
)
High-Z
Req. CLK
Cycles
22
14
14
14
22
22
14
DS21796M-page 4
2003-2012 Microchip Technology Inc.
93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C
2.0
FUNCTIONAL DESCRIPTION
2.3
Data Protection
When the ORG pin (93XX76C) is connected to V
CC
,
the (x16) organization is selected. When it is connected
to ground, the (x8) organization is selected. Instruc-
tions, addresses and write data are clocked into the DI
pin on the rising edge of the clock (CLK). The DO pin is
normally held in a High-Z state except when reading
data from the device, or when checking the Ready/
Busy
status during a programming operation. The
Ready/
Busy
status can be verified during an Erase/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS.
All modes of operation are inhibited when V
CC
is below
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
or 3.8V for ‘93C’ devices.
The
EWEN
and
EWDS
commands give additional
protection against accidentally programming during
normal operation.
Note:
For added protection, an
EWDS
command
should be performed after every write
operation and an external 10 k pull-
down protection resistor should be added
to the CS pin.
2.1
Start Condition
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
Note:
When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active high.
After power-up the device is automatically in the EWDS
mode. Therefore, an
EWEN
instruction must be
performed before the initial
ERASE
or
WRITE
instruction
can be executed.
Note:
To prevent accidental writes to the array in
the 93XX76C devices, set the PE pin to a
logic low.
Block Diagram
V
CC
V
SS
Address
Decoder
Memory
Array
Address
Counter
Data Register
DI
ORG*
CS
PE*
CLK
Clock
Register
Mode
Decode
Logic
Output
Buffer
DO
2.2
Data In/Data Out (DI/DO)
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation if A0 is a logic high-
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of the
driver, the higher the voltage at the Data Out pin. In
order to limit this current, a resistor should be
connected between DI and DO.
*ORG and PE inputs are not available on
A/B devices.
2003-2012 Microchip Technology Inc.
DS21796M-page 5
小广播

技术视频推荐

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
搜索索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
器件入口   12 4Y 9 BC GJ GM GO HE L1 L4 O0 OI SC TZ V9

北京市海淀区知春路23号集成电路设计园量子银座1305 电话:(010)82350740 邮编:100191

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2022 EEWORLD.com.cn, Inc. All rights reserved