Quad-Frequency Programmable XO IDT8N4Q001 REV G
DATA SHEET
General Description Features
The IDT8N4Q001 is a Quad-Frequency Programmable Clock • Fourth generation FemtoClock® NG technology
Oscillator with very flexible frequency programming capabilities. The • Programmable clock output frequency from 15.476MHz to
device uses IDT’s fourth generation FemtoClock® NG technology for 866.67MHz and from 975MHz to 1,300MHz
an optimum high clock frequency and low phase noise performance. • Four power-up default frequencies (see part number order
The device accepts 2.5V or 3.3V supply and is packaged in a small, codes), re-programmable by I2C
lead-free (RoHS 6) 10-lead ceramic 5mm x 7mm x 1.55mm package. • I2C programming interface for the output clock frequency and
Besides the four default power-up frequencies set by the FSEL0 and internal PLL control registers
FSEL1 pins, the IDT8N4Q001 can be programmed via the I2C • Frequency programming resolution is 435.9Hz ÷N
interface to output clock frequencies between 15.476MHz to • One 2.5V, 3.3V LVDS clock output
866.67MHz and from 975MHz to 1,300MHz to a very high degree of • Two control inputs for the power-up default frequency
precision with a frequency step size of 435.9Hz ÷ N (N is the PLL •
output divider). Since the FSEL0 and FSEL1 pins are mapped to four LVCMOS/LVTTL compatible control inputs
independent PLL divider registers (P, MINT, MFRAC and N), • RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.253ps
reprogramming those registers to other frequencies under control of (typical), integer PLL feedback configuration
FSEL0 and FSEL1 is supported. The extended temperature range • RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.263ps
supports wireless infrastructure, telecommunication and networking (typical), integer PLL feedback configuration
end equipment requirements. • Full 2.5V or 3.3V supply modes
• -40°C to 85°C ambient operating temperature
• Available in Lead-free (RoHS 6) package
Block Diagram Pin Assignment
÷P PFD FemtoClock® NG Q 10 SCLK 9 SDATA
OSC & VCO ÷N nQ
LPF 1950-2600MHz
fXTAL DNU 1 8 VDD
OE 2 7 nQ
÷MINT, MFRAC GND 3 6 Q
2 FSEL0 4 FSEL1 5
25 7
FSEL1 Pulldown Configuration Register (ROM)
FSEL0 Pulldown IDT8N4Q001
(Frequency, APR, Polarity) 10-lead ceramic 5mm x 7mm x 1.55mm
SCLK Pullup package body
SDATA Pullup I2C Control CD Package
Top View
OE Pullup
IDT8N4Q001GCD REVISION A MARCH 6, 2012 1 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Table 1. Pin Descriptions
Number Name Type Description
1 DNU Do not use.
2 OE Input Pullup Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels.
3 GND Power Power supply ground.
5, 4 FSEL1, FSEL0 Input Pulldown Default frequency select pins. See the Default Frequency Order Codes section.
LVCMOS/LVTTL interface levels.
6, 7 Q, nQ Output Differential clock output. LVDS interface levels.
8 VDD Power Power supply pin.
9 SDATA Input Pullup I2C Data Input. LVCMOS/LVTTL interface levels.
10 SCLK Input Pullup I2C Clock Input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 5.5 pF
RPULLUP Input Pullup Resistor 50 k
RPULLDOWN Input Pulldown Resistor 50 k
Function Tables
Table 3A. OE Configuration
Input
OE Output Enable
0 Outputs Q, nQ are in high-impedance state.
1 (default) Outputs are enabled.
NOTE: OE is an asynchronous control.
Table 3B. Output Frequency Range
Output Frequency Ranges
15.476MHz to 866.67MHz
975MHz to 1,300MHz
NOTE: Supported output frequency range. The output frequency
can be programmed to any frequency in this range and to a precision
of 218Hz or better.
IDT8N4Q001GCD REVISION A MARCH 6, 2012 2 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Block Diagram with Programming Registers
PFD Output Divider N
OSC ÷P FemtoClock® NG Q
& VCO ÷N nQ
LPF 1950-2600MHz
fXTAL MHz
2 Feedback Divider M (25 Bit) 7
MINT MFRAC
(7 bits) (18 bits)
7 18
Programming Registers 27
P0 MINT0 MFRAC0 N0 34
I2C Control I2C: 2 bits 7 bits 18 bits 7 bits
00
30 Def: 2 bits 7 bits 18 bits 7 bits 34
P1 MINT1 MFRAC1 N1
I2C: 2 bits 7 bits 18 bits 7 bits 01
30 Def: 2 bits 7 bits 18 bits 7 bits 34
P2 MINT2 MFRAC2 N2
Pullup I2C: 2 bits 7 bits 18 bits 7 bits 34
SCLK Pullup 10
SDATA 30 Def: 2 bits 7 bits 18 bits 7 bits 34
P3 MINT3 MFRAC3 N3
I2C: 2 bits 7 bits 18 bits 7 bits 11
30 Def: 2 bits 7 bits 18 bits 7 bits 34
FSEL[1:0] Pulldown, Pulldown
OE Pullup
Def: Power-up default register setting for I2C registers
Pn, MINTn, MFRACn and Nn
IDT8N4Q001GCD REVISION A MARCH 6, 2012 3 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Principles of Operation
The block diagram consists of the internal 3rd overtone crystal and As identified previously, the configurations of P, M (MINT & MFRAC)
oscillator which provide the reference clock fXTAL of either 114.285 and N divider settings are stored the I2C register, and the
MHz or 100MHz. The PLL includes the FemtoClock NG VCO along configuration loaded at power-up is determined by the FSEL[1:0]
with the Pre-divider (P), the feedback divider (M) and the post divider pins.
(N). The P, M, and N dividers determine the output frequency based
on the fXTAL reference and must be configured correctly for proper Table 4. Frequency Selection
operation. The feedback divider is fractional supporting a huge Input
number of output frequencies. The configuration of the feedback
divider to integer-only values results in an improved output phase FSEL1 FSEL0 Selects Register
noise characteristics at the expense of the range of output
frequencies. In addition, internal registers are used to hold up to four 0 (def.) 0 (def.) Frequency 0 P0, MINT0, MFRAC0, N0
different factory pre-set P, M, and N configuration settings. These 0 1 Frequency 1 P1, MINT1, MFRAC1, N1
default pre-sets are stored in the I2C registers at power-up. Each
configuration is selected via the the FSEL[1:0] pins and can be read 1 0 Frequency 2 P2, MINT2, MFRAC2, N2
back using the SCLK and SDATA pins. 1 1 Frequency 3 P3, MINT3, MFRAC3, N3
The user may choose to operate the device at an output frequency
different than that set by the factory. After power-up, the user may
write new P, N and M settings into one or more of the four
configuration registers and then use the FSEL[1:0] pins to select the Frequency Configuration
newly programmed configuration. Note that the I2C registers are
volatile and a power supply cycle will reload the pre-set factory An order code is assigned to each frequency configuration
default conditions. programmed by the factory (default frequencies). For more
If the user does choose to write a different P, M, and N configuration, information on the available default frequencies and order codes,
it is recommended to write to a configuration which is not currently please see the Ordering Information Section in this document. For
selected by FSEL[1:0] and then change to that configuration after the available order codes, see the FemtoClock NG Ceramic-Package
I2C transaction has completed. Changing the FSEL[1:0] controls XO and VCXO Ordering Product Information document.
results in an immediate change of the output frequency to the For more information and guidelines on programming of the device
selected register values. The P, M, and N frequency configurations for custom frequency configurations, the register description, the
support an output frequency range 15.476MHz to 866.67MHz and selection of fractional and integer-feedback configurations and the
975MHz to 1,300MHz. serial interface description, see the FemtoClock NG Ceramic 5x7
The devices use the fractional feedback divider with a delta-sigma Module Programming Guide.
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
The output frequency is determined by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency fOUT is
calculated by:
fOUT = fXT AL -----1------ M INT + M------F----R----A----C-----+-----0---.--5- (1)
PN 218
The four configuration registers for the P, M (MINT & MFRAC) and N
dividers which are named Pn, MINTn, MFRACn and Nn with n = 0 to
3. “n” denominates one of the four possible configurations.
IDT8N4Q001GCD REVISION A MARCH 6, 2012 4 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item Rating
Supply Voltage, VDD 3.63V
Inputs, VI -0.5V to VDD + 0.5V
Outputs, IO (SDATA) 10mA
Outputs, IO (LVDS)
Continuous Current 10mA
Surge Current 15mA
Package Thermal Impedance, JA 49.4C/W (0 mps)
Storage Temperature, TSTG -65C to 150C
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Power Supply Voltage 3.135 3.3 3.465 V
IDD Power Supply Current 160 mA
Table 5B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Power Supply Voltage 2.375 2.5 2.625 V
IDD Power Supply Current 155 mA
IDT8N4Q001GCD REVISION A MARCH 6, 2012 5 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Table 5C. LVCMOS/LVTTL DC Characteristic, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
FSEL[1:0], OE VCC =3.3V +5% 1.7 VCC +0.3 V
VIH Input High Voltage
FSEL[1:0], OE VCC =2.5V +5% 1.7 VCC +0.3 V
FSEL[1:0] VCC =3.3V +5% -0.3 0.5 V
OE VCC =3.3V +5% -0.3 0.8 V
VIL Input Low Voltage
FSEL[1:0] VCC =2.5V +5% -0.3 0.5 V
OE VCC =2.5V +5% -0.3 0.8 V
OE VDD = VIN = 3.465V or 2.625V 10 µA
IIH Input High Current SDATA, SCLK VDD = VIN = 3.465V or 2.625V 5 µA
FSEL0, FSEL1 VDD = VIN = 3.465V or 2.625V 150 µA
OE VDD = 3.465V or 2.625V, -500 µA
VIN = 0V
IIL Input Low Current SDATA, SCLK VDD = 3.465V or 2.625V, -150 µA
VIN = 0V
FSEL0, FSEL1 VDD = 3.465V or 2.625V, -5 µA
VIN = 0V
Table 5D. LVDS DC Characteristics, VDD = 3.3V ± 5%or 2.5V, ± 5%TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage 247 350 454 mV
VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.0 1.20 1.375 V
VOS VOS Magnitude Change 50 mV
IDT8N4Q001GCD REVISION A MARCH 6, 2012 6 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency Q, nQ Output Divider, N = 3 to126 15.476 866.67 MHz
Output Divider, N = 2 975 1,300 MHz
fI Initial Accuracy Measured at 25°C ±10 ppm
Option code = A or B ±100 ppm
fS Temperature Stability Option code = E or F ±50 ppm
Option code = K or L ±20 ppm
fA Aging Frequency drift over 10 year life ±3 ppm
Frequency drift over 15 year life ±5 ppm
Option code A or B (10 year life) ±113 ppm
fT Total Stability Option code E or F (10 year life) ±63 ppm
Option code K or L (10 year life) ±33 ppm
tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 20 ps
tjit(per) RMS Period Jitter; NOTE 1 2.85 4 ps
RMS Phase Jitter (Random):
Fractional PLL feedback and 17 MHz fOUT 1300 MHz, 0.440 0.995 ps
fXTAL=100.000MHz (2xxx order NOTE 2,3,4
codes)
500 MHz fOUT 1300 MHz, 0.240 0.390 ps
NOTE 2,3,4
RMS Phase Jitter (Random); 125 MHz fOUT 500 MHz, 0.245 0.425 ps
tjit(Ø) NOTE 2,3,4
Integer PLL feedback and 17 MHz fOUT 125 MHz,
fXTAL=100.00MHz (1xxx order codes) NOTE 2,3,4 0.350 0.555 ps
fOUT 156.25 MHz, NOTE 2, 3, 4 0.253 ps
fOUT 156.25 MHz,NOTE 2, 3, 5 0.263 ps
RMS Phase Jitter (Random) 17 MHz fOUT 1300 MHz,
Fractional PLL feedback and NOTE 2, 3, 4 0.475 0.990 ps
fXTAL=114.285MHz (0xxx order codes)
N(100) Single-side band phase noise, 156.25MHz -94.7 dBc/Hz
100Hz from Carrier
N(1k) Single-side band phase noise, 156.25MHz -121.5 dBc/Hz
1kHz from Carrier
N(10k) Single-side band phase noise, 156.25MHz -130.9 dBc/Hz
10kHz from Carrier
N(100k) Single-side band phase noise, 156.25MHz -137.2 dBc/Hz
100kHz from Carrier
N(1M) Single-side band phase noise, 156.25MHz -138.9 dBc/Hz
1MHz from Carrier
N(10M) Single-side band phase noise, 156.25MHz -153.7 dBc/Hz
10MHz from Carrier
PSNR Power Supply Noise Rejection 50mV Sinusoidal Noise -54 dB
1kHz - 50kHz
tR / tF Output Rise/Fall Time 20% to 80% 100 425 ps
IDT8N4Q001GCD REVISION A MARCH 6, 2012 7 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Symbol Parameter Test Conditions Minimum Typical Maximum Units
odc Output Duty Cycle 45 55 %
tSTARTUP Oscillator Start-Up Time 20 ms
tSET Output frequency settling time after 470 µs
FSEL0 and FSEL1 values are changed
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
NOTE 2: Please refer to the phase noise plots.
NOTE 3: Please see the FemtoClockNG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the
optimum configuration for phase noise. Integer PLL feedback is the default operation for the dddd = 1xxx order codes and configures
DSM_ENA = 0 and ADC_EN = 0..
NOTE 4: Integration range: 12kHz-20MHz.
NOTE 5: Integration range: 1kHz-40MHz.
IDT8N4Q001GCD REVISION A MARCH 6, 2012 8 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Typical Phase Noise at 156.25MHz (12kHz - 20MHz)
dBc Hz
Noise Power
Offset Frequency (Hz)
RMS Phase Noise (Random) for Integer PLL Feedback and fXTAL=100.000MHz.
IDT8N4Q001GCD REVISION A MARCH 6, 2012 9 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Parameter Measurement Information
SCOPE SCOPE
VDD Q Q
3.3V±5% 2.5V±5% VDD
POWER SUPPLY POWER SUPPLY
+ Float GND – + Float GND –
nQ nQ
3.3V LVDS Output Load AC Test Circuit 2.5V LVDS Output Load AC Test Circuit
Phase Noise Plot VOH
Noise Power VREF
1σ contains 68.26% of all measurements VOL
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
f1 Offset Frequency f2 Reference Point Histogram
(Trigger Edge) Mean Period
(First edge after trigger)
RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers
RMS Phase Jitter Period Jitter
nQ nQ
Q Q
t PW
t PERIOD ➤ tcycle n ➤ ➤ tcycle n+1 ➤
| | tjit(cc) =
t PW tcycle n – tcycle n+1
odc = x 100% 1000 Cycles
t PERIOD
Output Duty Cycle/Pulse Width/Period Cycle-to-Cycle Jitter
IDT8N4Q001GCD REVISION A MARCH 6, 2012 10 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Parameter Measurement Information (continued)
VDD
nQ out
80% 80%
VOD DC Input LVDS ➤
20% 20%
Q ➤
tR tF out VOS/Δ VOS
➤
Output Rise/Fall Time Offset Voltage Setup
VDD
out ➤
➤
DC Input LVDS 100 VOD/Δ VOD
out ➤
Differential Output Voltage Setup
IDT8N4Q001GCD REVISION A MARCH 6, 2012 11 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Applications Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Select Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
LVDS Driver Termination
For a general LVDS interface, the recommended value for the standard termination schematic as shown in Figure 1A can be used
termination impedance (ZT) is between 90 and 132. The actual with either type of output structure. Figure 1B, which can also be
value should be selected to match the differential impedance (Z0) of used with both output types, is an optional termination with center tap
your transmission line. A typical point-to-point LVDS design uses a capacitance to help filter common mode noise. The capacitor value
100 parallel resistor at the receiver and a 100 differential should be approximately 50pF. If using a non-standard termination, it
transmission-line environment. In order to avoid any is recommended to contact IDT and confirm if the output structure is
transmission-line reflection issues, the components should be current source or voltage source type. In addition, since these
surface mounted and must be placed as close to the receiver as outputs are LVDS compatible, the input receiver’s amplitude and
possible. IDT offers a full line of LVDS compliant devices with two common-mode input range should be verified for compatibility with
types of output structures: current source and voltage source. The the output.
LVDS ZO • ZT LVDS
Driver ZT Receiver
Figure 1A. Standard Termination
ZT
LVDS ZO • ZT 2 LVDS
Driver C ZT Receiver
2
Figure 1B. Optional Termination
LVDS Termination
IDT8N4Q001GCD REVISION A MARCH 6, 2012 12 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Schematic Layout
Figure 2 shows an example of IDT8N4Q001 application schematic. Power supply filter recommendations are a general guideline to be
In this example, the device is operated at VDD = 3.3V. As with any used for reducing external noise from coupling into the devices. The
high speed analog circuitry, the power supply pins are vulnerable to filter performance is designed for wide range of noise frequencies.
noise. To achieve optimum jitter performance, power supply isolation This low-pass filter starts to attenuate noise at approximately 10kHz.
is required. If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
In order to achieve the best possible filtering, it is recommended that be adjusted and if required, additional filtering be added. Additionally,
the placement of the filter components be on the device side of the good general design practices for power plane voltage stability
PCB as close to the power pins as possible. If space is limited, the suggests adding bulk capacitances in the local area of all devices.
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on The schematic example focuses on functional connections and is not
the opposite side. configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
VDD
R1 R2
SP SP
BL M18 BB22 1SN1 3. 3V
S C LK SDA TA VDD 1 2
C1 C2 F e rrite Be ad
U1 10 9 C3
0 .1 uF 10 uF 0. 1u F
S C LK SDA TA
1 DNU VD D 8
OE 2 OE nQ 7
3 GND Q 6
Q
+
F SEL0 FS EL1 Zo_ D if f = 10 0 Ohm R5
100
nQ -
4 5
LVDS Termination
V CC=3 .3V
F SEL0 FSE L1
Logic Control Input Examples Q
Set Logic Set Logic R6
VD D Input to VDD Input to Z o_D if f = 100 Ohm 50 +
'1' '0'
RU 1 RU2 C4 -
1K N ot Ins ta ll 0. 1u F
R7
To Logic To Logic 50
Inp ut Input nQ
p in s pins
RD 1 RD2
N o t I nst all 1K Alternate
LVDS
Termi nat ion
Figure 2. IDT8N4Q001 Application Schematic
IDT8N4Q001GCD REVISION A MARCH 6, 2012 13 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8N4Q001.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844S42I is the sum of the core power plus the power dissipated in the load(s). The following is the power
dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
• Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 160mA = 554.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.554W * 49.4°C/W = 112.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 10 Lead Ceramic 5mm x 7mm Package, Forced Convection
JA by Velocity
Meters per Second 0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 49.4°C/W 44.2°C/W 41.0°C/W
IDT8N4Q001GCD REVISION A MARCH 6, 2012 14 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Reliability Information
Table 8. JA vs. Air Flow Table for a 10-lead Ceramic 5mm x 7mm Package
JA vs. Air Flow
Meters per Second 0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 49.4°C/W 44.2°C/W 41.0°C/W
Transistor Count
The transistor count for IDT8N4Q001 is: 47,372
IDT8N4Q001GCD REVISION A MARCH 6, 2012 15 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Package Outline and Package Dimensions
IDT8N4Q001GCD REVISION A MARCH 6, 2012 16 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products
The programmable VCXO and XO devices support a variety of contains a 114.285MHz internal crystal as frequency source,
devices options such as the output type, number of default frequen- industrial temperature range, a lead-free (6/6 RoHS) 10-lead ceramic
cies, internal crystal frequency, power supply voltage, ambient 5mm x 7mm x 1.55mm package and is factory-programmed to the
temperature range and the frequency accuracy. The device options, default frequencies of 100MHz, 122.88MHz, 125MHz and
default frequencies and default VCXO pull range must be specified 156.25MHz and to the VCXO pull range of minimum 100 ppm.
at the time of order and are programmed by IDT before the shipment. Other default frequencies and order codes are available from IDT on
The table below specifies the available order codes, including the request. For more information on available default frequencies, see
device options and default frequency configurations. Example part the FemtoClock NG Ceramic-Package XO and VCXO Ordering
number: the order code 8N3QV01FG-0001CDI specifies a Product Information document.
programmable, quad default-frequency VCXO with a voltage supply
of 2.5V, a LVPECL output, a 50 ppm crystal frequency accuracy,
Part/Order Number
8N X X XXX X X - dddd XX X X
Shipping Package
8: Tape & Reel
FemtoClock NG (no letter): Tray
I/O Identifier Ambient Temperature Range
0: LVCMOS “I”: Industrial: (TA = -40°C to 85°C)
3: LVPECL (no letter) : (TA = 0°C to 70°C)
4: LVDS
Package Code
CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm
Number of Default Frequencies
S: 1: Single Default-Frequency and VCXO Pull Range
D: 2: Dual See document FemtoClock NG Ceramic-Package XO and VCXO
Q: 4: Quad Ordering Product Information.
dddd fXTAL (MHz) PLL feedback Use for
Part Number 0000 to 0999 114.285 Fractional VCXO, XO
Function #pins OE fct. at 1000 to 1999 Integer XO
pin 2000 to 2999 100.000 Fractional XO
001 XO 10 OE@2
003 XO 10 OE@1 Last digit = L: configuration pre-programmed and not changable
V01 VCXO 10 OE@2
V03 VCXO 10 OE@1 Die Revision
V75 VCXO 6 OE@2 G
V76 VCXO 6 nOE@2
V85 VCXO 6 —
085 XO 6 OE@1 Option Code (Supply Voltage and Frequency-Stability)
270 XO 6 OE@1 A: VCC = 3.3V±5%, ±100ppm
B: VCC = 2.5V±5%, ±100ppm
271 XO 6 OE@2 E: VCC = 3.3V±5%, ±50ppm
272 XO 6 nOE@2 F: VCC = 2.5V±5%, ±50ppm
273 XO 6 nOE@1 K: VCC = 3.3V±5%, ±20ppm
L: VCC = 2.5V±5%, ±20ppm
IDT8N4Q001GCD REVISION A MARCH 6, 2012 17 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Table 9. Device Marking
Industrial Temperature Range (TA = -40°C to 85°C) Commercial Temperature Range (TA = 0°C to 70°C)
Marking IDT8N4x001yG- IDT8N4x001yG-
ddddCDI ddddCD
x = Number of Default Frequencies, y = Option Code, dddd=Default-Frequency and VCXO Pull Range
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
IDT8N4Q001GCD REVISION A MARCH 6, 2012 18 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
Revision History Sheet
Rev Table Page Description of Change Date
A 9 18 Table 9 Device Marking, corrected marking. 3/6/12
IDT8N4Q001GCD REVISION A MARCH 6, 2012 19 ©2012 Integrated Device Technology, Inc.
IDT8N4Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO
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Copyright 2012. All rights reserved.
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1037CDI8 8N4Q001KG-0056CDI 8N4Q001KG-0047CDI8 8N4Q001FG-1086CDI8 8N4Q001FG-1086CDI
8N4Q001EG-1098CDI8 8N4Q001KG-0056CDI8 8N4Q001FG-1028CDI8 8N4Q001EG-1098CDI 8N4Q001FG-
1043CDI8 8N4Q001LG-0039CDI8 8N4Q001LG-0039CDI 8N4Q001KG-0092CDI8 8N4Q001FG-1043CDI
8N4Q001FG-1076CDI8 8N4Q001KG-0018CDI 8N4Q001KG-0047CDI 8N4Q001LG-1037CDI 8N4Q001KG-0009CDI8
8N4Q001KG-0009CDI 8N4Q001KG-0196CDI 8N4Q001KG-2193CDI 8N4Q001KG-1196CDI8 8N4Q001KG-
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8N4Q001KG-1208CDI8 8N4Q001FG-1207CDI 8N4Q001KG-2201CDI 8N4Q001EG-1207CDI 8N4Q001LG-1154CDI
8N4Q001KG-0122CDI8 8N4Q001LG-0009CDI8 8N4Q001KG-1164CDI 8N4Q001LG-1145CDI 8N4Q001LG-
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8N4Q001KG-1043CDI 8N4Q001FG-0076CDI 8N4Q001KG-0010CDI8 8N4Q001LG-0123CDI8 8N4Q001EG-
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0092CDI8 8N4Q001FG-2163CDI 8N4Q001KG-0132CDI 8N4Q001KG-0075CDI8 8N4Q001KG-1118CDI
8N4Q001LG-1127CDI8 8N4Q001FG-0124CDI8 8N4Q001KG-0058CDI8 8N4Q001FG-0099CDI8 8N4Q001EG-
1033CDI8 8N4Q001LG-1149CDI 8N4Q001KG-0072CDI8 8N4Q001LG-0159CDI 8N4Q001KG-1015CDI8
8N4Q001LG-0045CDI8 8N4Q001LG-1127CDI 8N4Q001KG-0160CDI8
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