Cover
88EM8010/88EM8011
Power Factor Correction Controller
Datasheet
Marvell. Moving Forward Faster Customer Use Only
Doc. No. MV-S104861-01, Rev.
September 30, 2009
Document Classification: Proprietary
88EM8010/88EM8011
Datasheet
For further information about Marvell products, see the Marvell website: http://www.marvell.com
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Doc. No. MV-S104861-01 Rev. Document Classification: Proprietary Copyright 2009 Marvell
Page 2 September 30, 2009, 2.00
88EM8010/88EM8011
Power Factor Correction Controller
Datasheet
PRODUCT OVERVIEW General Features
The Marvell 88EM8010/88EM8011 device is a high Patented DSP control with adaptive loop coefficient
performance Power Factor Correction (PFC) Controller for Continuous Conduction Mode (CCM) operation
boost applications. The device is used for universal PFC Average current mode control
front-end boost converters in system or standalone products. Adaptive control loop achieves high power factor for a
Both devices work at fixed frequencies. 88EM8010 at 60kHz wide range of voltage and load conditions
while 88EM8011 at 120kHz. Adaptive over current protection for universal voltage
Fixed frequency of operation
Marvell advanced mixed signal technology ensures low Total High power factor and low harmonic distortion for a wide
Harmonic Distortion (THD). The IC operates under average
Continuous Conduction Mode (CCM). range of load conditions
Up to 2A driver capability
The 88EM8010/88EM8011 PFC controller improves the steady Minimal external components required
state and transient performance through Marvell's innovative Under voltage lockout (UVLO)
Digital Signal Processing (DSP) solution. The proprietary Over voltage protection (OVP)
adaptive over-current protection has the ability to ensure almost Thermal shutdown
constant power constraint and provides safety provisions Input line frequency range from 45Hz to 65Hz
including open loop and over voltage protection protocols.
Applications
The internal voltage loop compensation and current loop control
guarantees system stability and thus reduces the external Universal front-end PFC boost controller
component count and costs. AC/DC adaptors and battery chargers
Electronic Ballasts front-end with PFC
The 8-pin SOIC package further facilitates the application
design process, saving board space. The resultant simple
system design and minimum cost makes 88EM8010/88EM8011
the ideal choice for PFC controllers.
Figure 1: PFC Boost Circuit Diagram
L DR2
Q1
VO ut
Bridge PFC iL
Retifier
CIN Rgate Load
CO2
AC Rsen
IN Rcs
Ra SW ISNS SGND
Rb
Rc VDD VIN 88EM8010/ PGND RS1
8011 RS2
CVDD VDD FB
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Datasheet
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Table of Contents
Table of Contents
Table of Contents ....................................................................................................................................... 5
List of Figures............................................................................................................................................. 7
List of Tables .............................................................................................................................................. 9
1 Signal Description ....................................................................................................................... 11
1.1 Pin Configurations ...........................................................................................................................................11
1.2 Pin Descriptions ..............................................................................................................................................11
2 Electrical Specifications ............................................................................................................. 13
2.1 Absolute Maximum Ratings ...........................................................................................................................13
2.2 Recommended Operating Conditions .............................................................................................................14
2.3 Electrical Characteristics ................................................................................................................................15
3 Functional Description................................................................................................................ 19
3.1 Overview .........................................................................................................................................................19
3.2 Signal Process and Functions.........................................................................................................................20
4 Functional Characteristics ......................................................................................................... 21
4.1 VDD Characteristics ........................................................................................................................................21
4.2 VFB Characteristics for Over Voltage Protection .............................................................................................23
4.3 Switching Frequency Characteristics ..............................................................................................................25
4.4 Over Current Threshold Characteristics..........................................................................................................26
5 Design and Applications Information ........................................................................................ 27
5.1 Input Voltage Resistor Divider on VIN Pin.......................................................................................................27
5.2 Voltage Loop & Output Voltage Feedback on FB Pin .....................................................................................30
5.3 Current Sensing and Over Current Protection ................................................................................................31
5.3.1 Current Sensing through ISNS Pin ...................................................................................................31
5.3.2 Over Current Limitation.....................................................................................................................33
5.4 SW Pin to MOSFET Gate ...............................................................................................................................33
5.5 VDD, Signal Ground (SGND) and Power Ground (PGND) .............................................................................34
5.6 Boost PFC Schematics ...................................................................................................................................35
6 Mechanical Drawings .................................................................................................................. 37
6.1 Mechanical Drawings ......................................................................................................................................37
7 Part Order Numbering/Package Marking .................................................................................. 39
7.1 Part Order Numbering ..................................................................................................................................39
7.2 Package Markings...........................................................................................................................................40
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Datasheet
G Revision History .......................................................................................................................... 41
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List of Figures
List of Figures
Figure 1: PFC Boost Circuit Diagram ................................................................................................................3
1 Signal Description ........................................................................................................................... 11
Figure 2: SOIC-8 Pin Diagram (Top View).......................................................................................................11
2 Electrical Specifications ................................................................................................................. 13
3 Functional Description.................................................................................................................... 19
Figure 3: Top Level Block Diagram..................................................................................................................19
4 Functional Characteristics.............................................................................................................. 21
Figure 4: IDD Quiescent (IDD_QST) vs. VDD ...................................................................................................21
Figure 5a: IDD vs. VDD (VDD_ON) ........................................................................................................................21
Figure 5b: IDD vs. VDD (VDD_ON), VFB Enable...................................................................................................21
Figure 6a: IDD Sleep (IDD_OP) vs. Temperature...............................................................................................22
Figure 6b: IDD Operation (IDD_OP) vs. Temperature ........................................................................................22
Figure 7: VDD On/Off vs. Temperature ...........................................................................................................22
Figure 8: IDD vs. VFB (OVP) .............................................................................................................................23
Figure 9: VFB_OVP vs. Temperature ..............................................................................................................23
Figure 10: VFB_OVP Hysteresis vs. Temperature ............................................................................................23
Figure 11: VFB_OVP_LATCH vs. Temperature ................................................................................................23
Figure 12: Normal Regulation Reference (VFB_REG) vs. Temperature ...........................................................24
Figure 13: IDD vs. VFB (Enable) .......................................................................................................................24
Figure 14: VFB_EN (Enable) vs. Temperature ..................................................................................................24
Figure 15: VFB_EN Hysteresis vs. Temperature ...............................................................................................24
Figure 16: Switching Frequency vs. Temperature .............................................................................................25
Figure 17: Over Current (VIOVER) vs. Input Voltage VIN Peak Value).............................................................26
Figure 18: Over Current (VIOVER) vs. Temperature .........................................................................................26
5 Design and Applications Information ............................................................................................ 27
Figure 19: Internal Block for Zero-cross Detection, Brown-out Protection .........................................................28
Figure 20: Peak Detecting Signal for Predictive Sinusoidal AC Voltage............................................................29
Figure 21: Input Voltage Resistor Divider Layout Guidelines ............................................................................30
Figure 22: Output Voltage Resistor Divider .......................................................................................................31
Figure 23: Current Sensing Circuit.....................................................................................................................31
Figure 24: SW Pin Layout Guidelines ................................................................................................................33
Figure 25: VDD Decoupling Capacitor and Ground Layout Guidelines .............................................................34
Figure 26: 64W/450V Front-End Boost PFC Schematic ....................................................................................35
Figure 27: 300W/380V Front-End Boost PFC Schematic ..................................................................................36
6 Mechanical Drawings ...................................................................................................................... 37
Figure 28: 8-Pin SOIC Mechanical Drawing ......................................................................................................37
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7 Part Order Numbering/Package Marking....................................................................................... 39
Figure 29: 88EM8010/88EM8011 Sample Ordering Part Number ....................................................................39
Figure 30: Package Marking and Pin 1 Location ...............................................................................................40
G Revision History ............................................................................................................................... 41
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List of Tables
List of Tables
1 Signal Description ............................................................................................................................ 11
Table 1: Pin Descriptions ................................................................................................................................11
Table 2: Pin Descriptions ................................................................................................................................12
2 Electrical Specifications .................................................................................................................. 13
Table 3: Absolute Maximum Ratings ..............................................................................................................13
Table 4: Recommended Operating Conditions...............................................................................................14
Table 5: Electrical Characteristics ..................................................................................................................15
3 Functional Description..................................................................................................................... 19
4 Functional Characteristics............................................................................................................... 21
5 Design and Applications Information ............................................................................................. 27
Table 6: Current Sensing Resistor Selection ..................................................................................................32
Table 7: Current Sensing Resistor Selection Reference ................................................................................32
6 Mechanical Drawings ....................................................................................................................... 37
7 Part Order Numbering/Package Marking........................................................................................ 39
Table 8: 88EM8010/88EM8011 Part Order Options .......................................................................................39
G Revision History ............................................................................................................................... 41
Table 9: Revision History ................................................................................................................................41
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Signal Description
Pin Configurations
1 Signal Description
1.1 Pin Configurations
Figure 2: SOIC-8 Pin Diagram (Top View)
PGND 1 8 SW
SGND 2 7 VDD
ISNS 3 6 NC
5 FB/EN
VIN 4
1.2 Pin Descriptions
Table 1: Pin Descriptions
Pin # Pin Name Pin Type Pin Description
1 PGND Ground Power Ground
2 SGND Ground Signal Ground
3 ISNS Input Current Sense
4 VIN Input Voltage Input
5 FB/EN Input Feedback/Enable/Shutdown
6 NC NC No Connect
7 VDD Supply IC Supply Voltage
8 SW Output Switch
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88EM8010/88EM8011
Datasheet
Table 2: Pin Descriptions
Pin # Pin Name Description
1 PGND Power Ground
Connected to the source of the primary MOSFET. The PCB trace from the power ground to the
source of the MOSFET must be kept as short as possible. To avoid any switching noise
interruption on signal processing, PGND and SGND remain separate inside the IC.
2 SGND Signal Ground
Must be connected to the power ground with Kelvin sensing connection, so that SGND has
dedicated trace and connections and provides noiseless environment for the signal processing.
3 ISNS Current Sense
Sense resistor varies for different loads. Pin used for current shaping and for over current
protection. Please refer to Section 5, Design and Applications Information, on page 27.
4 VIN Voltage Input
Connects to resistive divider at input AC line "phase" to GND. Voltage applied is a half
rectified sine wave scaled down by the input resistive divider.
Voltage input pin is a high impedance input pin. An impedance of 2M (typical) is
recommended to be designed from the input AC "phase" to GND in order to reduce the
standby power. Higher impedance is preferred with the right PCB design on this pin signal.
Voltage is compared with a threshold reference (VVIN_BR) to detect the zero-cross location
of the input sine wave and synthesize (regenerate) the input sine wave. This sine wave is
used to generate the current reference.
Brown-out protection1 function is also provided by this pin. A resistor devider with a 100:1
ratio from the highside resistor to the lowside resistor is corresponding to the "brown-out
protection" input voltage as 50V (RMS). Increasing that raio will increase the "brown-out
voltage". Please refer to footnote1 for further explaination.
5 FB/EN Feedback
The output voltage is scaled to 2.5V with 100% rated value. Transition from soft start to normal
regulation at 87.5% rated VFB. Over voltage shutdown SW gate signal at 107% rated VFB and
recover once below VFB_OVP. There is another threshold (VFB_OVP_LATCH) as 3.77V on the FB
pin. When FB Voltage reaches VFB_OVP_LATCH, SW signal is shutdown and latched until
another VDD power on reset.
EN: Enable/Shutdown
At VFB>VFB_EN (Table 5) IC is enabled.
Pulling this pin to VFB < VFB_SHDN (Table 5) disables the chip back to sleep mode
Note: A 200k resistor inside IL between FB pin to SGND. This should be included in the
calculation for the design of the output voltage feedback resistor devider.
6 NC No Connect
Float this pin.
7 VDD IC Supply Voltage
Nominal voltage is 12V (typical) and the Under Voltage Lockout (UVLO) for VDD
(Table 5). When VDD < VDD_UVLO, IC is shut down. Start voltage of IC is VDD_ON (Table 5) and
maximum voltage is 16V (Table 5). It should be clamped by a Zener for protection in the system
design.
8 SW Switch
PWM gate signal for the boost switch. Connects to the gate of external boost MOSFET. It is the
DSP core output for ON/OFF time buffered through the internal adaptive driver.
1. Brown-out voltage is determined by Ra , Rb, and Rc as shown in Figure 1. Please refer to Section 5.1 for a further
understanding.
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Electrical Specifications
Absolute Maximum Ratings
2 Electrical Specifications
2.1 Absolute Maximum Ratings
Table 3: Absolute Maximum Ratings1
NOTE: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device
reliability.
Symbol Parameter Min Max Units
VDD Power Supply (Voltage to PGND=SGND) -0.3 18 V
VIsns Voltage at ISNS pin -0.5 3 V
VVIN Voltage at VIN pin -0.3 5.5 V
VFB Voltage at FB pin -0.3 5.5 V
VSW Output Driver Voltage 18 V
JA Thermal Resistance SOIC-8 156.5 C/W
Thermal Resistance DIP-8 89.5 C/W
TA Operating Ambient Temperature Range2 -40 85 C
TJ Maximum Junction Temperature 125 C
TSTOR Storage Temperature Range -65 150 C
VESD ESD Rating3
2 kV
1. Exceeding the absolute maximum rating may damage the device.
2. Specifications over the -40C to 85C operating temperature ranges are assured by design, characterization and
correlation with statistical process controls.
3. Devices are ESD sensitive. Handling precautions recommended. Human Body model, 1.5k in series with 100pF.
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Datasheet
2.2 Recommended Operating Conditions
Table 4: Recommended Operating Conditions1
Symbol Parameter Min Ty p Max Units
TA Operating Ambient Temperature2 -40 85 C
TJ Junction Temperature -20 125 C
1. This device is not guaranteed to function outside the specified operating temperature range.
2. Over the 40C to 85C operating temperature ranges are assured by design, characterization, and correlation with
statistical process controls.
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Electrical Specifications
Electrical Characteristics
2.3 Electrical Characteristics
Table 5: Electrical Characteristics
NOTE: A 12V supply voltage is applied and the ambient temperature (TA) = 25C.
Symbol Parameter Conditions Min Ty p Max Units
VDD Supply
VDD Supply Voltage 7.0 12 16 V
VDD_ON VDD Power On Threshold First time power on 11.9 12.22 V
operation
VDD_UVLO VDD Power Off Threshold After VDD is powered 7.0 7.2 V
(UVLO) up and running
VDD_UVLO_HYS VDD_UVLO Hysteresis 4.7 5.3 V
IDD_QST VDD Quiescent Current1 VDD = 12V 95 A
IDD_OP VDD Operating Current VDD = 12V; 5.2 6.2 mA
CGate = 1nF
FSW = 118kHz
VIN= 0
Thermal Shutdown
TSD Thermal Shutdown 150 C
C
TSD_HYS Hysteresis for Thermal 25
Shutdown
Gate Driver Minimum Gate High Voltage2 VDD = 12V 10.0 V
VG_HI Maximum Gate Low Voltage3 CGate = 1nF
Sourcing 500mA 2.0 V
VG_LO
VDD = 12V
CGate = 1nF
Sinking 500mA
RDSON Gate Drive Resistance Sourcing 75mA 2.4
T=25 C
Gate Drive Resistance Sinking 20mA 2.0
T=25 C
ISW_PK Driver Peak Current CGate = 10 nF 2.0 A
VDD = 12 V
tR Rise Time CGate = 1 nF 35 ns
CGate = 10 nF 125 ns
tF Fall Time CGate = 1 nF 35 ns
CGate = 10 nF 145 ns
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88EM8010/88EM8011
Datasheet
Table 5: Electrical Characteristics
NOTE: A 12V supply voltage is applied and the ambient temperature (TA) = 25C.
Symbol Parameter Conditions Min Ty p Max Units
DMAX Maximum Duty Cycle 97 %
Feedback/Overvoltage
VFB_REG Normal Regulation Reference IC powered on 2.55 V
VFB_EN
VFB at Enable Threshold IC powered on by 0.278 V
VFB_SHDN VDD_ON. Transition
VFB at Shutdown Threshold from sleep mode to IC 0.248 V
VFB_EN_HYS enable at Enable
VFB_OVP VFB at Enable Hysteresis Threshold of VFB_EN 0.03 V
Over Voltage Protection
Threshold IC powered on by 2.67 2.71 2.75 V
VDD_ON. Transfe from
IC enable to sleep
mode at Shutdown
Threshold of VFB_SHDN
At 107% of VFB_REG.
VFB_OVP_HYS Over Voltage Protection 0.102 0.108 V
Hysteresis
VFB_OVP_LATCH Over Voltage Protection Latch 3.77 V
Current Sensing and Current Protection4
VIOVER_TH1 Over Current Threshold Zone Peak value of half-sine 397 mV
15 voltage at VIN:
1.26
VIOVER_TH2 Over Current Threshold Zone 329 mV
25 Peak value of half-sine
voltage at VIN:
VIOVER_TH3 Over Current Threshold Zone 1.89
35
Peak value of half-sine
VIOVER_TH4 Over Current Threshold Zone voltage at VIN: 202 mV
45 2.59< VIN<3.43Vpk8
Peak value of half-sine
voltage at VIN:
3.43
88EM8010 Switching Frequency Oscillator
FSW Frequency 59 kHz
88EM8011 Switching Frequency Oscillator
FSW Frequency 100.3 118 135.7 kHz
1. Quiescent Current: VDD power supply current before VDD first time reaches VDD_On.
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Electrical Specifications
Electrical Characteristics
2. Considering the voltage drop on the internal driver MOSFET during current sourcing.
3. Considering the voltage drop on the internal driver MOSFET during current sinking.
4. To achieve almost constant power limit for the universal input range, current protection self-adjusts thresholds in four
zones of input voltage levels. A margin of 50% compared to the rated current is considered for the threshold current
values.
5. Threshold of negative voltage drop across Rsns due to instantaneous current
6. With input divider ratio of 1/100, these values are equivalent to 90 Vrms
7. With input divider ratio of 1/100, these values are equivalent to 135 Vrms
8. With input divider ratio of 1/100, these values are equivalent to 185 Vrms
9. With input divider ratio of 1/100, these values are equivalent to 245 Vrms
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Functional Description
Overview
3 Functional Description
3.1 Overview
The 88EM8010/88EM8011 is a high performance, low-cost with minimum component count Power
Factor Correction (PFC) Controller. The device is used for Universal PFC front-end boost converters
in systems or standalone products. The high performance of 88EM8010/88EM8011 is accompanied
with its small system size and simplicity of application. Figure 3 shows the top level block diagram.
Figure 3: Top Level Block Diagram
88EM8010/8011 Clock Over T_over Protection
Temperature Vo_over Management
Oscillator I_over
Fault
Current Protection
Driver
ISNS Current MUX Disable
FB Amplifier Switcher
Output & DSP Gate SW
Voltage ADC Core
Level Detect Driver
State
Machine
Vo_over
VIN Zero Cross
Detect
Current Power Serial Data Startup Setting
Protection Distribution Interface or
Threshold
Selection and Frequency
Bandgaps Setting
PGND SGND VDD
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3.2 88EM8010/88EM8011
Datasheet
Signal Process and Functions
The 88EM8010/88EM8011 boost power board includes three inputs:
Resistive divider signal from AC line voltage
Feedback from the output DC bus
Voltage across the current sense resistor
The input phase voltage to ground (half rectified sine wave) scaled down by the input resistive
divider is applied to pin VIN. This signal used for estimation of the AC line voltage and regeneration
of the AC sine wave. It is also used for voltage level detection that produces adaptive multiple
thresholds for the over current limit and guarantees a constant power limit from the AC source.
Signal from the DC bus voltage through the output resistor devider and Analog-to-Digital Converter
(ADC) provides the feedback data for the voltage PI control loop.
HF switching current pulse signal is retrieved from the voltage drop across the current sense
resistor. Current sensing signal is negative to the ground. This signal after HF noise filter and fixed
gain amplification, is transferred through the ADC to the digital current loop and the current error
amplifier. The reference current for the current control PI loop is provided by multiplying the voltage
error amplifier output and the regenerated sinusoidal line voltage information.
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Functional Characteristics
VDD Characteristics
4 Functional Characteristics
4.1 The following applies unless otherwise noted: VIN = 60Hz half-wave sinusoidal from 0V to the peak
voltage (VPK) given in the test conditions of each graph. TA = 25C.
All measurement readings are typical.
VDD Characteristics
Figure 4: IDD Quiescent (IDD_QST) vs. VDD
100
90
80
70
IDD (A) 60
50
40
30
20
10
0
0 2 4 6 8 10 12
VDD (V)
Test Conditions: VFB = 0V
CGate = 1nF
VIN = 0V V_Isns = 0V
FSW = 118kHz
Figure 5a: IDD vs. VDD (VDD_ON) Figure 5b: IDD vs. VDD (VDD_ON), VFB Enable
0.18 7
0.16 6
0.14 5 VDD Falling
VDD Falling
IDD (mA) IDD (mA) 4 VDD Rising
0.12
VDD Rising
0.10
0.08 3
0.06
2
0.04
0.02 1
0.00 0
0
5 10 15 20 0 2 4 6 8 10 12 14 16
VDD (V) VDD (V)
Test Conditions: VFB = 0V Test Conditions: VFB = 2.4V
CGate = 1nF CGate = 1nF
VIN = 0V V_Isns = 0V VIN = 0V V_Isns = 0V
FSW = 118kHz FSW = 118kHz
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Datasheet
Figure 6a: IDD Sleep (IDD_OP) vs. Temperature Figure 6b: IDD Operation (IDD_OP) vs.
Temperature
0.25
7
0.20
6
0.15
IDD (mA) 5
IDD (mA)
0.10 4
3
0.05 2
0.00 1
-40 -20 0 20 40 60 80 0
Temperature ( C) -40 -20 0 20 40 60 80
Temperature ( C)
Test Conditions: VFB = 0V Test Conditions: VFB = 2.4V
CGate = 1nF CGate = 1nF
VDD = 12V V_Isns = 0V VDD = 12V V_Isns = 0V
VIN = 0V VIN = 0V
FSW = 118kHz FSW = 118kHz
Figure 7: VDD On/Off vs. Temperature
14
On
12
VDD (V) 10
Off
8
6
4
Hysteresis
2
0
-40 -20 0 20 40 60 80
Temperature ( C)
Test Conditions: FFB = 2.4V
CGate = 1nF
VIN = 0V V_Isns = 0V
FSW = 118kHz
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Functional Characteristics
VFB Characteristics for Over Voltage Protection
4.2 VFB Characteristics for Over Voltage Protection
Figure 8: IDD vs. VFB (OVP) Figure 9: VFB_OVP vs. Temperature
6.5 3.0
6.0 OVP Threshold
5.5 2.5
Recovery Threshold
2.0
IDD (mA) 5.0 VFB Falling V FB (V )
VFB Rising 1.5
4.5
4.0 1.0
3.5 0.5
3.0 0.0
2.0 2.2 2.4 2.6 2.8 3.0 -40 -20 0 20 40 60 80
VFB (V) Temperature ( C)
Test Conditions: FSW = 118kHz Test Conditions: FSW = 118kHz
CGate = 1nF CGate = 1nF
VDD = 12V V_Isns = 0V VDD = 12V V_Isns = 0V
VIN = 0V VIN = 0V
Figure 10: VFB_OVP Hysteresis vs. Temperature Figure 11: VFB_OVP_LATCH vs. Temperature
0.30 4.0
3.5
0.25
3.0
0.20 2.5
VFB (V) 0.15 VFB (V) 2.0
0.10 1.5
1.0
0.05 0.5
0.00 0.0
-40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80
Temperature ( C) Temperature (C)
Test Conditions: FSW = 118kHz Test Conditions: FSW = 118kHz
CGate = 1nF VDD = 12V CGate = 1nF
VDD = 12V V_Isns = 0V VIN = 0V V_Isns = 0V
VIN = 0V
Copyright 2009 Marvell Document Classification: Proprietary Doc. No. MV-S104861-01 Rev.
September 30, 2009, 2.00 Page 23
88EM8010/88EM8011
Datasheet
Figure 12: Normal Regulation Reference Figure 13: IDD vs. VFB (Enable)
(VFB_REG) vs. Temperature
7
3.0 6
2.9 5
VFB Falling
2.8
4
2.7 IDD (mA) VFB Rising
VFB (V) 2.6 3
2.5
2.4 2
2.3
2.2 1
2.1 0
2.0 0.0 0.2 0.4 0.6 0.8 1.0
-40 -20 0 20 40 60 80 VFB (V)
Temperature (C)
Test Conditions: FSW = 118kHz Test Conditions: FSW = 118kHz
CGate = 1nF VDD = 12V CGate = 1nF
VDD = 12V V_Isns = 0V VIN = 0V V_Isns = 0V
VIN = 2V
Figure 14: VFB_EN (Enable) vs. Temperature Figure 15: VFB_EN Hysteresis vs. Temperature
0.30
0.40
0.35 Enable High 0.25
Enable Low
0.30
VFB_En_hys (V) 0.20
VFB (V) 0.25
0.20 0.15
0.15
0.10 0.10
0.05 0.05
0.00
-40 -20 0 20 40 60 80 0.00
-40 -20 0 20 40 60 80
Temperature ( C) Temperature ( C)
Test Conditions: FSW = 118kHz Test Conditions: FSW = 118kHz
CGate = 1nF VDD = 12V CGate = 1nF
VDD = 12V V_Isns = 0V VIN = 0V V_Isns = 0V
VIN = 0V
Doc. No. MV-S104861-01 Rev. Document Classification: Proprietary Copyright 2009 Marvell
Page 24 September 30, 2009, 2.00
Functional Characteristics
Switching Frequency Characteristics
4.3 Switching Frequency Characteristics
Figure 16: Switching Frequency vs. Temperature
140
FSW (8011)
120
Frequency (kHz) 100
80
FSW (8010)
60
40
20
0
-40 -20 0 20 40 60 80
Temperature (C)
Test Conditions: VFB = 2.4V
CGate = 1nF
VDD = 12V V_Isns = 0V
VIN = 0V
Copyright 2009 Marvell Document Classification: Proprietary Doc. No. MV-S104861-01 Rev.
September 30, 2009, 2.00 Page 25
88EM8010/88EM8011
Datasheet
4.4 Over Current Threshold Characteristics
Figure 17: Over Current (VIOVER) vs. Input Voltage
VIN Peak Value)
0.50
0.45
0.40
0.35
V C S (V ) 0.30
0.25
0.20
0.15
0.10
0.05
0.00
0 1 2 3 4 5
VIN (V)
Test Conditions: VFB = 2.4V
CGate = 1nF
VDD = 12V V_Isns = 0V
FSW = 118kHz
Figure 18: Over Current (VIOVER) vs. Temperature
450
400 VIN = 1.5V
350 VIN = 2.25V
300 VIN = 3V
VCS (V) 250
VIN = 3.7V
200
150
100
50
0
-40 -20 0 20 40 60 80
Temperature ( C)
Test Conditions: VFB = 2.4V
CGate = 1nF
VDD = 12V V_Isns = 0V
FSW = 118kHz
Doc. No. MV-S104861-01 Rev. Document Classification: Proprietary Copyright 2009 Marvell
Page 26 September 30, 2009, 2.00
Design and Applications Information
Input Voltage Resistor Divider on VIN Pin
5 Design and Applications Information
5.1 The boost converter is the most popular topology for two stage front-end PFC pre-regulator system.
The 88EM8010/88EM8011 chip control algorithm uses Average Current Mode Control for power
factor correction applications based on Boost topology with low harmonic distortion and good noise
immunity. The IC senses the output voltage and forces it to follow the reference voltage to produce a
stable DC output voltage matching the design requirement. It also senses the inductor current and
forces the average signal of the inductor current to follow the sinusoidal current reference, therefore
achieving unity power factor.
Marvell's innovative PFC control technology improves the performance of the Boost converter used
in PFC applications. The 88EM8010/88EM8011 provides the higher drive current capability than that
of the competitors' ICs. The 88EM8010/8011 also achieves high power factor/low THD at high line
low load condition which is benefited from Marvell mixed signal technology. The Boost PFC solution
based on the 88EM8010/88EM8011 provides customers with the simplest structure, lowest cost and
best performance compared with the other industry solutions currently on the market.
The following sections provide guidelines for the application design, component selection, and board
layout in order to improve front-end Boost PFC performance. There are three analog input signals
listed below are required from the power train to the controller IC 88EM8010/88EM8011.
1. Input voltage signal at VIN pin is a half sinusoidal waveform. It is fed into the VIN pin through
the input voltage resistor divider. This is for the line frequency zero-cross detection for PFC.
2. Output voltage signal at FB pin is the output voltage through the resistor divider to feedback on
FB pin. This is for the voltage loop regulation.
3. Current sensing signal through the sensing resistor to the ISNS pin. This is for the average
current mode control to achieve a good sinusoidal current waveform and high power factor.
The output signal from the 88EM8010/88EM8011 is the PWM gate drive signal from the SW pin. The
switching frequency on the 88EM8010 device is fixed to 60kHz (typical) while the 88EM8011 is fixed
to 120kHz (typical). Both device tolerances are shown in Table 5, Electrical Characteristics, on
page 15.
Input Voltage Resistor Divider on VIN Pin
An accurate peak detection signal and zero-cross detection for regenerating the input sinusoidal
voltage is the most important issue for a proper current shaping and total harmonic distortion (THD)
improvement. If the threshold reference is too high, near the peak area, the calculation may lose
accuracy because of the low slope. On the other hand, if the threshold reference is too low due to
the possible distortions near the zero-crossing, there could be an error on zero-cross detection. For
a universal input voltage range (85VAC~270VAC) the optimum accuracy would be achieved if the
threshold level is around 30 degree of the line cycle.
Copyright 2009 Marvell Document Classification: Proprietary Doc. No. MV-S104861-01 Rev.
September 30, 2009, 2.00 Page 27
88EM8010/88EM8011
Datasheet
Figure 19: Internal Block for Zero-cross Detection, Brown-out Protection
88EM8010 Brown-Out
/8011 Protection
AC Vline _ pk
IN
Phase ( )
Ra Predictive
Sinusoidal Zero
Rb VIN AC Voltage Crossing
Rc Peak Power Limit
detecting Threshold
Selection
pulse
To get a proper sinusoidal AC voltage, UVLO, and peak voltage detection, we need to choose the
right value for the sensing resistors: Ra, Rb, and Rc (See Figure 19). If the value is too small there
will be higher power loss and if the value is too big the resistor will not properly work due to the
picking noise of the VIN signal. The recommended values are shown below:
Ra + Rb = 100 = 1.8M
Rc 1 18k
Equation (1)
For the input voltage resistor divider, the appropriate combination based on the voltage / power
rating of the resistors should also be considered.
Doc. No. MV-S104861-01 Rev. Document Classification: Proprietary Copyright 2009 Marvell
Page 28 September 30, 2009, 2.00
Design and Applications Information
Input Voltage Resistor Divider on VIN Pin
Figure 20: Peak Detecting Signal for Predictive Sinusoidal AC Voltage
Vline_pk Vline_pk
VVIN_BR = 0.72V (Typ.)
V ( ) = Vline_pk sin
Half line cycle Half line cycle
N M N
Peak detecting Pulse
As can be seen in Figure 20, the internal peak detecting circuit generates peak detecting pulse
through the inside comparator which has a threshold voltage of 0.72V (typical). Processing of this
pulse in DSP core calculates the mid-point (peak point) and the zero-crossing point of the sinusoidal
waveform. The phase angle of is calculated using the width of the high and low signal M&N.
N = ( 2) Equation (2)
M = ( + 2) Equation (3)
= (---M-----------N-----) Equation (4)
4
Peak value of the sinusoidal waveform is introduced by the relation:
Vline_pk = -s-V-i--n--(-(----)---) Equation (5)
The signal that appears on the VIN pin is a half sinusoidal voltage waveform and its peak line value
has to be higher than VVIN_BR of 0.72V (typical) for normal operation. Whenever the VVIN_BR is less
than 0.72V at the peak line value, it is considered as a Brown-out condition. The IC only generates
6% duty during the brown-out condition. To adjust the brown-out protection point, the resistance
value of Ra, Rb and Rc can be changed. With the recommended resistor values in Equation (1) the
brown-out protection voltage is 72V peak value, which is around a 50V RMS value for the input line
voltage.
The layout of Rb, Rc and Cc should be kept as close as possible to the VIN pin, as shown in
Figure 21 in order to have a proper layout on the input voltage resistor divider and to avoid noise
picking. It is also recommended that a 0.1nF10nF capacitor is connected between the VIN pin and
ground with the layout also close to this pin.
Copyright 2009 Marvell Document Classification: Proprietary Doc. No. MV-S104861-01 Rev.
September 30, 2009, 2.00 Page 29
88EM8010/88EM8011
Datasheet
Figure 21: Input Voltage Resistor Divider Layout Guidelines
Ra SW
ISNS 88EM8010/ PGND
Rb 8011 SGND
Rc Cc V IN
VDD FB
Keep layout of Rb, Rc and Cc as
close as possible to Vin pin to
have high noise immunity
5.2 Voltage Loop & Output Voltage Feedback on FB Pin
The 88EM8010/88EM8011 IC integrates the voltage loop into digital DSP core. This internal voltage
loop has the lower corner frequency for the PFC requirement. The FB pin is the internal voltage loop
feedback signal input. The voltage reference of the IC is 2.5V for the rated output voltage.
It is well known that the front-end PFC with Boost topology has to maintain low enough bandwidth
(less than 20Hz) in order to achieve a good sinusoidal current waveform and power factor under a
wide input voltage and load condition. In order to achieve a good sinusoidal current waveform and
power factor, the voltage loop regulation coefficient should also be designed properly corresponding
to the different input voltages. The adaptive voltage loop coefficient is designed inside the IC to
select different voltage regulation parameters corresponding to the different input voltage. This
achieves a much better power factor and sinusoidal current waveform compared to any of PFC
power system on the market now.
The design of RS1and RS2, as shown in Figure 22, is based on the rated output voltage and the
power loss of the resistor divider. In order to keep low power consumption on the resistor divider and
good signal to noise immunity, a total resistance of several M is recommended for the pair of
resistors RS1 and RS2. Because there is a 200k resistor inside of the IC between the FB pin to the
SGND, the value of RS1 and RS2 is designed based on Equation (6) as:
V----r--e--f + V----r--e--f = V----o---u--t--------V----r--e-f Equation (6)
Rs2 R0 Rs1
Where Vref is 2.5V and R0 is 200k.
Doc. No. MV-S104861-01 Rev. Document Classification: Proprietary Copyright 2009 Marvell
Page 30 September 30, 2009, 2.00
Design and Applications Information
Current Sensing and Over Current Protection
Figure 22: Output Voltage Resistor Divider
VOUT
FB RS1
88EM8010/
8011 RS2
5.3 Current Sensing and Over Current Protection
5.3.1 Current Sensing through ISNS Pin
The voltage drop on the current sense resistor should be kept very small in order to reduce the
power consumption on the sense resistor (Rsen). The voltage drop (Vsen) across resistor (Rsen)
represents the Boost current signal. As shown in Figure 23. Vsen is feedback to the ISNS pin
through a resistor RCS, which is around 200. This resistor is necessary for the protection of the
ISNS pin during inrush and lightning surge condition.
The resistor (Rsen) should be designed and calculated such as the example in Table 6 where Rsen is
designed for a 64W Boost converter. The specification are: output power = 64W, input voltage range
= 85-264V, output voltage = 450V, 30% margin of over current on top of the normal current.
Figure 23: Current Sensing Circuit
L DR2
iL
Q1 CO2 Load
Vsen Rsen Using Kelvin sensing connection for
Rcs current sensing signal and SGND
with separate trace from PGND
SW ISNS SGND
VIN 88EM8010/ PGND
VDD 8011 FB
Copyright 2009 Marvell Document Classification: Proprietary Doc. No. MV-S104861-01 Rev.
September 30, 2009, 2.00 Page 31
88EM8010/88EM8011
Datasheet
.
Table 6: Current Sensing Resistor Selection
Input Power PIN 64W
Minimum Input Voltage VINMIN 85V
Maximum Average Input Current 1.06A
IINMAX = 2 -----P----I--N------
Assume 30% Switching Frequency Ripple VINMIN 0.32A
Peak Current with Ripple 1.38A
ripple = IINMAX 30 %
ipeak = IINMAX + ripple
Over Current Threshold Zone 1 (Table 5) VIOVERTH1 0.391V
Over Current Margin IMARGIN 30%
Current Sensing Resistor Calculation 0.22
Rsns = -------------V----I--O----V---E---R----T---H---1--------------
Current Sensing Resistor Selection ipeak (1 + IMARGIN) 0.25
Rsns
Table 7 shows the reference value of the current sensing resistor. In the practical design, the current
sensing resistor value could be fine tuned around the value shown in the table based on the
specification and the primary inductance of the Boost transformer.
Table 7: Current Sensing Resistor Selection Reference
Input Power (W) 32 64 125 250
0.400.50 0.200.25 0.100.125 0.050.06
Current Sensing
Resistor ()
As the layout guideline, the current sensing signal should use Kelvin sensing connection, as shown
in Figure 23. It means the SGND should layout as a separate trace from the PGND to avoid any
heavy current and spike current sharing on that trace. The Vsen net should be layout as close as
possible to the Rsen resistor. The same time, the Rsen resistor should be layout as close as possible
to the ground as shown in Figure 23.
Doc. No. MV-S104861-01 Rev. Document Classification: Proprietary Copyright 2009 Marvell
Page 32 September 30, 2009, 2.00
Design and Applications Information
SW Pin to MOSFET Gate
5.3.2 Over Current Limitation
5.4 An adaptive current protection threshold is designed in the IC corresponding to the different input
voltage in order to get the cycle by cycle current protection to avoid the transformer saturation. The
four level threshold is shown in the electrical characteristic table. The universal input voltage is
identified into four range from 90V to 275V. With the input voltage resistor divider ratio value as
100:1, these four ranges are 90135V, 135185V, 185245V and 245V to 275V. If the resistor
divider ratio value is increased from 100:1 to a higher value, these ranges will shift to the higher
voltage side. On the other hand, if the resistor divider ratio value is decreased from 100:1 to a lower
value, these ranges will shift to the lower voltage side. Therefore, the customer has the flexibility to
adjust these ranges during the design by tuning the input voltage resistor divider ratio around the
default value as 100:1.
SW Pin to MOSFET Gate
The 88EM8010/88EM8011 provides a maximum 2A drive current, which is the strongest drive to
date in comparison with the competition on the market. A default resistor of 10 is designed to go
between the SW pin and the gate of the external MOSFET. The gate driver loop is subject to fast rise
and the layout trace should be kept as short as possible in order to minimize the parasitic
inductance, as shown in Figure 24.
Figure 24: SW Pin Layout Guidelines
Rgate Q1
SW ISNS SGND
Keep this trace as short
as possible in layout
VIN 88EM8010/ PGND
VDD 8011
FB
Copyright 2009 Marvell Document Classification: Proprietary Doc. No. MV-S104861-01 Rev.
September 30, 2009, 2.00 Page 33
88EM8010/88EM8011
Datasheet
5.5 VDD, Signal Ground (SGND) and Power Ground
(PGND)
VDD is the IC power supply pin. It has a typical value of 12V and a maximum operating voltage of
16V. A Zener circuit below 16V is recommended in order to guarantee that the voltage on VDD will
not go any higher than 16V. The IC begins to function when VDD powers on at 12V. Once the IC
powers on, it keeps functioning as long as the VDD is higher than VDD_UVLO, which is 7V (typical). In
a practical design, an electrolytic capacitor is recommended to connect between VDD and ground in
order to retain the IC functionality during startup. That capacitor will need to keep the VDD higher
than 7V before the bias transformer winding takes over and provides enough energy for the power
IC.
A 0.010.1F ceramic capacitor is strongly recommended to be placed between the VDD and IC
ground with the layout trace as close to the IC as possible. This capacitor is used for decoupling the
noise to VDD and clamping the VDD voltage during the switching of the internal driver circuit.
SGND is directly connected to the system ground by a Kelvin connection trace. The system ground
is the source of the MOSFET, as shown in Figure 25. PGND connects to the system ground
separately and can not share the same trace with SGND. This is due to pulse current on PGND
while driving the external MOSFET on and off. This pulse current produces pulse voltage drops on
the PGND trace and may cause the current sensing signal to be distorted if the SGND shares the
same trace.
Figure 25: VDD Decoupling Capacitor and Ground Layout Guidelines
Rgate
Q1
SW ISNS SGND Using Kelvin sensing connection for
SGND with separate trace from PGND
VIN PGND
FB Keep this trace right beside
88EM8010/ C IC and as short as possible
8011
VDD
Doc. No. MV-S104861-01 Rev. Document Classification: Proprietary Copyright 2009 Marvell
Page 34 September 30, 2009, 2.00
Copyright 2009 Marvell Figure 26: 64W/450V Front-End Boost PFC Schematic 5.6
September 30, 2009, 2.00
Boost PFC Schematics
HVDC SEC_1 SEC_2
T2
J1 3A D5 D4 J2
S1M D6 STTH806DTI +450VDC
F1 S1M
C1 C10
AC input T1 0.22uF 0.01uF
EMI FILTER 305 VAC 630V DC
Q1 DC output
GATE STP8NM60
+ C5
47uF 250V
R4 D8 D7 C2 R14 R15 + C4
600k S1M S1M 0.22uF 10k 499k 47uF 250V
305 VAC
Document Classification: Proprietary R9
0.2R 1W
R5 R8 R13
600k 200R 499k
I-SENSE
HVDC
R1 R6 VIN U1 88EM8011 FB-EN R10
100k 1/4W 600k 4 5 487k
C11
R7 0.1nF VIN FB/EN R11
18k 8.66k
I-SENSE 3 ISNS N/C 6
SEC_1
R2 VDD12 R3 2 SGND VDD 7 VDD12 Design and Applications Information
100k 1/4W 10R 1/4W 1 PGND SW 8 Boost PFC Schematics
C9
D3 D1 0.1uF
15V 1W 1N91 4
+ C3 SEC_2 C8 9 EP RGATE
100uF 4.7uF D2 10
C7 1N914
4.7uF GATE
Doc. No. MV-S104861-01 Rev.
Page 35
Doc. No. MV-S104861-01 Rev. D3 88EM8010/88EM8011
Page 36 1N5406 Datasheet
C13 C14 +20VDC Figure 27: 300W/380V Front-End Boost PFC Schematic
10uF 10uF D2
UF4002
D1
UF4002
FA1 NTC1
5A 5 16 3T
1 2 7 8 60T 14
C8 R22 L1: 250uH D4 380VDC
470pF/250V 665k IDH08SG60C + C11
1206 9
330uF/450V
BD1 1 + C10 VDC
KBU605G 2 1500pF/630V
L R20 1 LF2 4 C4 C3 1 LF1 4 3 2 Q1
G 665k C6 3 C7 IPW50R250CP 1
C9 1206 1uF/275V 2 470pF/250V 1uF/275V
VAC 470pF/250V R21 2 3 0.33uF/630V R26 3
N 665k 0.040
Document Classification: Proprietary 1206 OPTIONAL C5 4.5mH 4AMPS 4- 2512
+20VDC 470pF/250V
R12
Q2 20K R13 R28
4.99 604k
4 PZT3904T1G 1206 1206
SOT223 R27
604k
R1 2 3 +15VDC R9 R25 SENSE GROUND 1206
ZERO 1/4W 200k POWER GROUND R18
C2 + R2 1 1206 200 C18 R16 604k
330uF/25V 10K R19 OPEN 0 1206
200k
ZD1 1206
15V
380VDC 3 2 1 8
R23 ISNS SGND SW +15VDC
200k PGND
1206
R8 R11 C19 4 7
1.8M 22.0k R24 10nF VIN VDD
1206 1206 6.04k
R29 R7 R10 88EM8011 C16 C17
187k 1.8M 22.0k 0.1uF 1uF
1206 1206
R5 R6 6 N/C FB/EN 5
1.8M 22.0k U1
1206 1206 C15 R14
OPEN 12.7k
Q3 Q4 4 2
MMBT2222A 3 1N60
SOT223
13
R4
1 2 ZD3 OPEN C12
220pF/250V
R3 ZD2
Copyright 2009 Marvell 15V +C1
September 30, 2009, 2.00 12.0k 18V 220uF/25V
Copyright 2009 Marvell 6.1 Mechanical Drawings 6
September 30, 2009, 2.00
Figure 28: 8-Pin SOIC Mechanical Drawing
Document Classification: Proprietary Mechanical Drawings
Doc. No. MV-S104861-01 Rev. Notes: Mechanical Drawings
Page 37 Mechanical Drawings
All dimensions in mm.
See Section 7, Part Order Numbering/Package Marking, on page 39 for package marking and pin 1
location.
88EM8010/88EM8011
Datasheet
THIS PAGE INTENTIONALLY LEFT BLANK
Doc. No. MV-S104861-01 Rev. Document Classification: Proprietary Copyright 2009 Marvell
Page 38 September 30, 2009, 2.00
Part Order Numbering/Package Marking
Part Order Numbering
7 Part Order Numbering/Package Marking
7.1 Part Order Numbering
Figure 29 shows the part order numbering scheme. For complete ordering information, contact your
Marvell FAE or sales representative.
Figure 29: 88EM8010/88EM8011 Sample Ordering Part Number
88EM8011 xxSAG2C000xxxx
Part number Custom code (optional)
Custom code
Custom code Temperature code
C = Commercial
Custom code Environmental code
Package code + = RoHS 0/6
= RoHS 5/6
1 = RoHS 6/6
2 = Green Halogen Free
The standard ordering part number for the respective solution is shown in Table 8.
Table 8: 88EM8010/88EM8011 Part Order Options1
Package Type Part Order Number
8-Pin SOIC 88EM8010xx-SAG2C000-xxxx
8-Pin SOIC 88EM8010xx-SAG2C000-T (Tape and Reel)
8-Pin SOIC 88EM8011xx-SAG2C000-xxxx
8-Pin SOIC 88EM8011xx-SAG2C000-T (Tape and Reel)
1. Please note that the 88EM8010 device is 60kHz and the 88EM8011 device is 120kHz.
Copyright 2009 Marvell Document Classification: Proprietary Doc. No. MV-S104861-01 Rev.
September 30, 2009, 2.00 Page 39
88EM8010/88EM8011
Datasheet
7.2 Package Markings
Figure 30 shows a sample package marking and pin 1 location.
Figure 30: Package Marking and Pin 1 Location
MRVL Marvell company abbreviation
801X Abbreviated Part number
YWWG XXXX = 4 character abbreviated part number
Pin 1 location Date code and lot traceability code
Y = Last digit of year
WW = Work Week
G = lot traceability code
Note: The above example is not drawn to scale. Location of markings are approximate.
Doc. No. MV-S104861-01 Rev. Document Classification: Proprietary Copyright 2009 Marvell
Page 40 September 30, 2009, 2.00
G Revision History
Table 9: Revision History
Document Type Document Revision
88EM8010/88EM8011 (Document = Rev. B)
Break-out 8010 (60kHz) and 8011 (120kHz)
Edits to Signals - Pin Descriptions
EC Table edits - change in values
Reworked Applications section
Copyright 2009 Marvell Document Classification: Proprietary Doc. No. MV-S104861-01 Rev.
September 30, 2009, 2.00 Page 41
Back Cover
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Fax: 1.408.752.9028
www.marvell.com
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