88E1111 Product Brief
Integrated 10/100/1000 Ultra
Gigabit Ethernet Transceiver
Doc. No. MV-S105540-00, Rev. --
March 4, 2009
Document Classification: Proprietary Information
Marvell. Moving Forward Faster
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
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Copyright 2009. Marvell International Ltd. All rights reserved. Marvell, the Marvell logo, Moving Forward Faster, Alaska, Fastwriter, Datacom Systems on Silicon, Libertas,
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Doc. No. MV-S105540-00 Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 2 March 4, 2009, Advance
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
OVERVIEW FEATURES
The Alaska Ultra 88E1111 Gigabit Ethernet Trans- 10/100/1000BASE-T IEEE 802.3 compliant
Supports GMII, TBI, reduced pin count GMII
ceiver is a physical layer device for Ethernet (RGMII), reduced pin count TBI (RTBI), and serial
GMII (SGMII) interfaces
1000BASE-T, 100BASE-TX, and 10BASE-T applica- Integrated 1.25 GHz SERDES for 1000BASE-X
fiber applications
tions. It is manufactured using standard digital CMOS Four RGMII timing modes
Energy Detect and Energy Detect+ low power
process and contains all the active circuitry required to modes
implement the physical layer functions to transmit and Three loopback modes for diagnostics
"Downshift" mode for two-pair cable installations
receive data on standard CAT 5 unshielded twisted pair. Fully integrated digital adaptive equalizers, echo
cancellers, and crosstalk cancellers
Advanced digital baseline wander correction
The 88E1111 device incorporates the Marvell Virtual Automatic MDI/MDIX crossover at all speeds of
operation
Cable Tester (VCTTM) feature, which uses Time Automatic polarity correction
IEEE 802.3u compliant Auto-Negotiation
Domain Reflectometry (TDR) technology for the remote Software programmable LED modes including LED
identification of potential cable malfunctions, thus testing
Automatic detection of fiber or copper operation
reducing equipment returns and service calls. Using Supports IEEE 1149.1 JTAG
Two-Wire Serial Interface (TWSI) and MDC/MDIO
VCT, the Alaska 88E1111 device detects and reports CRC checker, packet counter
Packet generation
potential cabling issues such as pair swaps, pair polar- Virtual Cable Tester (VCT)
Auto-Calibration for MAC Interface outputs
ity and excessive pair skew. The device will also detect Requires only two supplies: 2.5V and 1.0V (with
cable opens, shorts or any impedance mismatch in the 1.2V option for the 1.0V supply)
I/Os are 3.3V tolerant
cable and report accurately within one meter the dis- Low power dissipation Pave = 0.75W
117-Pin TFBGA, 96-Pin BCC, and 128 PQFP
tance to the fault. package options
117-Pin TFBGA and 96-Pin BCC packages avail-
The 88E1111 device supports the Gigabit Media Inde- able in Commercial or Industrial grade
RoHS 6/6 compliant packages available
pendent Interface (GMII), Reduced GMII (RGMII),
Serial Gigabit Media Independent Interface (SGMII),
the Ten-Bit Interface (TBI), and Reduced TBI (RTBI) for
direct connection to a MAC/Switch port.
The 88E1111 device incorporates an optional 1.25 GHz
SERDES (Serializer/Deserializer). The serial interface
may be connected directly to a fiber-optic transceiver
for 1000BASE-T/1000BASE-X media conversion appli-
cations. Additionally, the 88E1111 device may be used
to implement 1000BASE-T Gigabit Interface Converter
(GBIC) or Small Form Factor Pluggable (SFP) modules.
The 88E1111 device uses advanced mixed-signal pro-
cessing to perform equalization, echo and crosstalk
cancellation, data recovery, and error correction at a
gigabit per second data rate. The device achieves
robust performance in noisy environments with very low
power dissipation.
The 88E1111 device is offered in three different pack-
age options including a 117-Pin TFBGA, a 96-pin BCC
featuring a body size of only 9 x 9 mm, and a 128 PQFP
package.
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 3
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
M
a
10/100/1000 Mbps 88E1111 g RJ-45 Media Types:
Ethernet MAC Device n - 10BASE-T
e - 100BASE-TX
t - 1000BASE-T
i
MAC Interface Options
- GMII/MII c
- TBI
- RGMII s
- RTBI
- SGMII
- Serial Interface
88E1111 Device used in Copper Application
10/100/1000 Mbps 88E1111 Fiber Media Types:
Ethernet MAC Device Optics - 1000BASE-X
MAC Interface Options Serial
- GMII/MII Interface
- RGMII
88E1111 Device used in Fiber Application
(Effective SGMII MAC)
Gigabit Ethernet 88E1111 3-Speed
MAC Device SFP
MAC Interface Options Serial Interface
- GMII - 4-pin SGMIII
- RGMII
88E1111 RGMII/GMII MAC to SGMII MAC Conversion
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 4 March 4, 2009, Advance
Table of Contents
1.1 117-Pin TFBGA Package................................................................................................6
1.2 96-Pin BCC Package .....................................................................................................7
1.3 128-Pin PQFP Package ..................................................................................................8
1.4 Pin Description ...............................................................................................................9
1.4.1 Pin Type Definitions............................................................................................................ 9
1.5 I/O State at Various Test or Reset Modes ..................................................................33
1.6 117-Pin TFBGA Pin Assignment List - Alphabetical by Signal Name .....................34
1.7 96-Pin BCC Pin Assignment List - Alphabetical by Signal Name............................36
1.8 128-Pin PQFP Pin Assignment List - Alphabetical by Signal Name........................38
2.1 117-pin TFBGA Package..............................................................................................40
2.2 96-pin BCC Package - Top View .................................................................................42
2.3 96-Pin BCC Package - Bottom View ...........................................................................43
2.4 128-Pin PQFP Package ................................................................................................44
3.1 Ordering Part Numbers and Package Markings........................................................45
3.1.1 RoHS 5/6 Compliant Marking Examples .......................................................................... 46
3.1.2 RoHS 6/6 Compliant Marking Examples .......................................................................... 49
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 5
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Section 1. Signal Description
The 88E1111 device is a 10/100/1000BASE-T/1000BASE-X Gigabit Ethernet transceiver.
1.1 117-Pin TFBGA Package
Figure 1: 88E1111 Device 117-Pin TFBGA Package (Top View)
1 2 3 4 5 6 7 8 9
A RXD5 RXD6 S_IN+ S_IN- S_CLK+ S_CLK- S_OUT+ S_OUT- LED_ A
LINK1000
B RX_DV RXD0 RXD3 VDDO CRS COL AVDD LED_ VDDOH B
LINK100
C RX_CLK VDDO RXD2 RXD4 RXD7 DVDD DVDD LED_ LED_RX C
LINK10
D TX_CLK RX_ER RXD1 VSS VSS VSS DVDD CONFIG[0] LED_TX D
E TX_EN GTX_CLK DVDD VSS VSS VSS DVDD LED_ CONFIG[1] E
DUPLEX
F TXD0 TX_ER DVDD VSS VSS VSS VDDOH CONFIG[2] CONFIG[4] F
G NC TXD1 TXD2 VSS VSS VSS CONFIG[3] CONFIG[6] CONFIG[5] G
H TXD4 TXD3 TXD5 VSS VSS VSS VSSC SEL_ XTAL1 H
FREQ
J TXD6 TXD7 DVDD VSS VSS VSS DVDD VDDOH XTAL2 J
K VDDO 125CLK RESETn VSS VSS VSS NC TDO VDDOX K
L INTn VDDOX MDC COMA VSS VSS TDI TMS TCK L
M MDIO RSET AVDD AVDD HSDAC+ HSDAC- AVDD AVDD TRSTn M
N MDI[0]+ MDI[0]- MDI[1]+ MDI[1]- AVDD MDI[2]+ MDI[2]- MDI[3]+ MDI[3]- N
1 2 3 4 5 6 7 8 9
Figure 2: Pin A1 Location
Pin A1 location
88E1111-BAB
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Page 6 March 4, 2009, Advance
1.2 96-Pin BCC Package Signal Description
96-Pin BCC Package
Figure 3: 88E1111 Device 96-Pin BCC Package (Top View)
TCK 49
73 DVDD 71 LED_RX 69 DVDD 67 CONFIG[0] 65 CONFIG[2] 63 CONFIG[3] 61 CONFIG[5] 59 DVDD 57 VSSC 53 NC 51 VDDOX 48TDO 50
56
LED_LINK VDDOH 72 70 LED_TX 68 VDDOH 66 CONFIG[1] 64 DVDD 62 CONFIG[4] 60 CONFIG[6] 58 XTAL2 54 VDDOH 52 TRSTn 47
1000 XTAL1 55 TMS 46
74 LED_LINK LED_DUPL SEL_ AVDD 45
100 EX FREQ TDI 44
75 S_OUT- MDI[3]- 43
MDI[3]+ 42
76 LED_LINK 0 VSS
10 MDI[2]- 41
AVDD 40
77 S_OUT+
MDI[2]+ 39
78 AVDD HSDAC- 38
79 S_CLK+ HSDAC+ 37
AVDD 36
80 S_CLK-
AVDD 35
81 S_IN- MDI[1]- 34
82 S_IN+ MDI[1]+ 33
AVDD 32
83 COL
MDI[0]- 31
84 CRS RSET 30
85 DVDD MDI[0]+ 29
RESETn 28
86 RXD7 88E1111 - CAA
COMA 27
87 RXD6 VDDOX 26
88 VDDO MDC 25
89 RXD5
90 RXD4
91 RXD3
92 RXD1
93 RXD2
94 RX_DV
95 RXD0
96 VDDO 1 DVDD
2 RX_CLK
3 RX_ER
4 TX_CLK
5 VDDO
6 DVDD
7 TX_ER
8 GTX_CLK
9 TX_EN
10 DVDD
11 TXD0
12 TXD1
13 NC
14 TXD2
15 DVDD
16 TXD3
17 TXD4
18 TXD5
19 TXD6
20 TXD7
21 VDDO
22 125CLK
23 INTn
24 MDIO
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 7
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
1.3 128-Pin PQFP Package
Figure 4: 88E1111 Device 128-Pin PQFP Package (Top View)
102 VSS
101 VSS
100 LED_LINK10
99 LED_LINK100
98 LED_LINK1000
97 VDDOH
96 DVDD
95 LED_DUPLEX
94 VSS
93 VSS
92 LED_RX
91 LED_TX
90 DVDD
89 VDDOH
88 CONFIG[0]
87 CONFIG[1]
86 CONFIG[2]
85 DVDD
84 VSS
83 VSS
82 CONFIG[3]
81 CONFIG[4]
80 CONFIG[5]
79 CONFIG[6]
78 DVDD
77 SEL_FREQ
76 XTAL1
75 XTAL2
74 VSSC
73 VDDOH
72 TDO
71 VDDOX
70 TCK
69 TMS
68 TRSTn
67 TDI
66 VSS
65 VSS
VSS 103 88E1111 - RCJ 64 AVDD
AVDD 104 63 VSS
S_OUT- 105 Top View 62 MDI[3]-
61 MDI[3]+
VSS 106 60 VSS
S_OUT+ 107 59 AVDD
58 VSS
VSS 108 57 MDI[2]-
S_CLK- 109 56 MDI[2]+
S_CLK+ 110 55 VSS
54 HSDAC-
VSS 111 53 HSDAC+
S_IN- 112 52 AVDD
S_IN+ 113 51 VSS
50 NC
COL 114 49 AVDD
CRS 115 48 VSS
VSS 116 47 MDI[1]-
DVDD 117 46 MDI[1]+
DVDD 118 45 VSS
VSS 119 44 AVDD
RXD7 120 43 VSS
RXD6 121 42 MDI[0]-
VDDO 122 41 MDI[0]+
RXD5 123 40 VSS
RXD4 124 39 RSET
RXD3 125
RXD2 126
VSS 127
RXD1 128
VSS 1
DVDD 2
RXD0 3
RX_DV 4
VDDO 5
DVDD 6
RX_CLK 7
RX_ER 8
VSS 9
TX_CLK 10
VDDO 11
DVDD 12
TX_ER 13
GTX_CLK 14
VSS 15
TX_EN 16
DVDD 17
TXD0 18
TXD1 19
TXD2 20
VSS 21
VSS 22
DVDD 23
TXD3 24
TXD4 25
TXD5 26
DVDD 27
TXD6 28
TXD7 29
VDDO 30
125CLK 31
INTn 32
MDIO 33
VDDOX 34
MDC 35
RESETn 36
COMA 37
VSS 38
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 8 March 4, 2009, Advance
Signal Description
Pin Description
1.4 Pin Description
1.4.1 Pin Type Definitions
Pin Type Definition
H Input with hysteresis
I/O Input and output
I Input only
O Output only
PU Internal pull up
PD Internal pull down
D Open drain output
Z Tri-state output
mA DC sink capability
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 9
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 1: Media Dependent Interface
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e
Pin # Pin # I/O, D Media Dependent Interface[0].
N1 29 41 MDI[0]+ I/O, D In 1000BASE-T mode in MDI configuration,
MDI[0] correspond to BI_DA.
N2 31 42 MDI[0]- In MDIX configuration, MDI[0] correspond
to BI_DB.
N3 33 46 MDI[1]+
In 100BASE-TX and 10BASE-T modes in
N4 34 47 MDI[1]- MDI configuration, MDI[0] are used for the
transmit pair. In MDIX configuration,
MDI[0] are used for the receive pair.
MDI[0] should be tied to ground if not used.
Media Dependent Interface[1].
In 1000BASE-T mode in MDI configuration,
MDI[1] correspond to BI_DB.
In MDIX configuration, MDI[1] correspond
to BI_DA.
In 100BASE-TX and 10BASE-T modes in
MDI configuration, MDI[1] are used for the
receive pair. In MDIX configuration, MDI[1]
are used for the transmit pair.
MDI[1] should be tied to ground if not used.
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 10 March 4, 2009, Advance
Signal Description
Pin Description
Table 1: Media Dependent Interface (Continued)
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Type
Pin # Pin # I/O, D Media Dependent Interface[2].
N6 39 56 MDI[2]+ I/O, D In 1000BASE-T mode in MDI configuration,
MDI[2] correspond to BI_DC.
N7 41 57 MDI[2]- In MDIX configuration, MDI[2] corresponds
to BI_DD.
N8 42 61 MDI[3]+
In 100BASE-TX and 10BASE-T modes,
N9 43 62 MDI[3]- MDI[2] are not used.
MDI[2] should be tied to ground if not used.
Media Dependent Interface[3].
In 1000BASE-T mode in MDI configuration,
MDI[3] correspond to BI_DD.
In MDIX configuration, MDI[3] correspond
to BI_DC.
In 100BASE-TX and 10BASE-T modes,
MDI[3] are not used.
MDI[3] should be tied to ground if not used.
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 11
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
The GMII interface supports both 1000BASE-T and 1000BASE-X modes of operation. The GMII interface pins are
also used for the TBI interface. See Table 3 for TBI pin definitions. The MAC interface pins are 3.3V tolerant.
Table 2: GMII/MII Interfaces
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e
Pin # Pin # I GMII Transmit Clock. GTX_CLK provides a
125 MHz clock reference for TX_EN,
E2 8 14 GTX_CLK O, Z TX_ER, and TXD[7:0]. This clock can be
stopped when the device is in 10/100BASE-
D1 4 10 TX_CLK T modes, and also during Auto-Negotiation.
MII Transmit Clock. TX_CLK provides a 25
MHz clock reference for TX_EN, TX_ER,
and TXD[3:0] in 100BASE-TX mode, and a
2.5 MHz clock reference in 10BASE-T
mode.
TX_CLK provides a 25 MHz, 2.5 MHz, or 0
MHz clock during 1000 Mbps Good Link,
Auto-Negotiation, and Link Lost states
depending on the setting of register 20.6:4.
The 2.5 MHz clock is the default rate, which
may be programmed to another frequency
by writing to register 20.6:4.
E1 9 16 TX_EN I GMII and MII Transmit Enable. In GMII/MII
mode when TX_EN is asserted, data on
TXD[7:0] along with TX_ER is encoded and
transmitted onto the cable.
TX_EN is synchronous to GTX_CLK, and
synchronous to TX_CLK in 100BASE-TX
and 10BASE-T modes.
F2 7 13 TX_ER I GMII and MII Transmit Error. In GMII/MII
mode when TX_ER and TX_EN are both
asserted, the transmit error symbol is trans-
mitted onto the cable. When TX_ER is
asserted with TX_EN de-asserted, carrier
extension symbol is transmitted onto the
cable.
TX_ER is synchronous to GTX_CLK, and
synchronous to TX_CLK in 100BASE-TX
and 10BASE-T modes.
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 12 March 4, 2009, Advance
Signal Description
Pin Description
Table 2: GMII/MII Interfaces (Continued)
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e
Pin # Pin # GMII and MII Transmit Data. In GMII mode,
I TXD[7:0] present the data byte to be trans-
J2 20 29 TXD[7] mitted onto the cable in 1000BASE-T mode.
J1 19 28 TXD[6] In MII mode, TXD[3:0] present the data nib-
ble to be transmitted onto the cable in
H3 18 26 TXD[5] 100BASE-TX and 10BASE-T modes.
TXD[7:4] are ignored in these modes, but
H1 17 25 TXD[4] should be driven either high or low. These
pins must not float.
H2 16 24 TXD[3]/TXD[3]
TXD[7:0] are synchronous to GTX_CLK, and
G3 14 20 TXD[2]/TXD[2] synchronous to TX_CLK in 100BASE-TX
and 10BASE-T modes.
G2 12 19 TXD[1]/TXD[1]
Inputs TXD[7:4] should be tied low if not
F1 11 18 TXD[0]/TXD[0] used (e.g., RGMII mode).
C1 2 7 RX_CLK O, Z GMII and MII Receive Clock. RX_CLK pro-
vides a 125 MHz clock reference for RX_DV,
B1 94 4 RX_DV O, Z RX_ER, and RXD[7:0] in 1000BASE-T
mode, a 25 MHz clock reference in
D2 3 8 RX_ER O, Z 100BASE-TX mode, and a 2.5 MHz clock
reference in 10BASE-T mode.
TX_TCLK comes from the RX_CLK pins
used in jitter testing. Refer to Register 9 for
jitter test modes.
GMII and MII Receive Data Valid. When
RX_DV is asserted, data received on the
cable is decoded and presented on
RXD[7:0] and RX_ER.
RX_DV is synchronous to RX_CLK.
GMII and MII Receive Error. When RX_ER
and RX_DV are both asserted, the signals
indicate an error symbol is detected on the
cable.
When RX_ER is asserted with RX_DV de-
asserted, a false carrier or carrier extension
symbol is detected on the cable.
RX_ER is synchronous to RX_CLK.
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 13
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 2: GMII/MII Interfaces (Continued)
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e
Pin # Pin # GMII and MII Receive Data. Symbols
O, Z received on the cable are decoded and pre-
C5 86 120 RXD[7] sented on RXD[7:0] in 1000BASE-T mode.
A2 87 121 RXD[6] In MII mode, RXD[3:0] are used in
100BASE-TX and 10BASE-T modes. In MII
A1 89 123 RXD[5] mode, RXD[7:4] are driven low.
C4 90 124 RXD[4] RXD[7:0] is synchronous to RX_CLK.
B3 91 125 RXD[3]/RXD[3] GMII and MII Carrier Sense. CRS asserts
when the receive medium is non-idle. In half-
C3 93 126 RXD[2]/RXD[2] duplex mode, CRS is also asserted during
transmission. CRS assertion during half-
D3 92 128 RXD[1]/RXD[1] duplex transmit can be disabled by program-
ming register 16.11 to 0.
B2 95 3 RXD[0]/RXD[0]
CRS is asynchronous to RX_CLK,
B5 84 115 CRS O, Z GTX_CLK, and TX_CLK.
B6 83 114 COL O, Z GMII and MII Collision. In 10/100/
1000BASE-T full-duplex modes, COL is
always low. In 10/100/1000BASE-T half-
duplex modes, COL asserts only when both
the transmit and receive media are non-idle.
In 10BASE-T half-duplex mode, COL is
asserted to indicate signal quality error
(SQE). SQE can be disabled by clearing reg-
ister 16.2 to zero.
COL is asynchronous to RX_CLK,
GTX_CLK, and TX_CLK.
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 14 March 4, 2009, Advance
Signal Description
Pin Description
The TBI interface supports 1000BASE-T mode of operation. The TBI interface uses the same pins as the GMII
interface. The MAC interface pins are 3.3V tolerant.
Table 3: TBI Interface
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e
Pin # Pin # TBI Transmit Clock. In TBI mode, GTX_CLK
I is used as TBI_TXCLK. TBI_TXCLK is a 125
E2 8 14 GTX_CLK/ MHz transmit clock.
TBI_TXCLK
TBI_TXCLK provides a 125 MHz clock refer-
ence for TX_EN, TX_ER, and TXD[7:0].
D1 4 10 TX_CLK/RCLK1 O, Z TBI 62.5 MHz Receive Clock- even code
group. In TBI mode, TX_CLK is used as
RCLK1.
J2 20 29 TXD[7] I TBI Transmit Data. TXD[7:0] presents the
J1 19 28 TXD[6] data byte to be transmitted onto the cable.
H3 18 26 TXD[5]
H1 17 25 TXD[4] TXD[9:0] are synchronous to GTX_CLK.
H2 16 24 TXD[3]
G3 14 20 TXD[2] Inputs TXD[7:4] should be tied low if not
G2 12 19 TXD[1] used (e.g., RTBI mode).
F1 11 18 TXD[0]
E1 9 16 TX_EN/ I TBI Transmit Data. In TBI mode, TX_EN is
TXD8 used as TXD8.
TXD[9:0] are synchronous to GTX_CLK.
F2 7 13 TX_ER/ I TBI Transmit Data. In TBI mode, TX_ER is
TXD9 used as TXD9.
TXD[9:0] are synchronous to GTX_CLK.
TX_ER should be tied low if not used (e.g.,
RTBI mode).
C1 2 7 RX_CLK/ O, Z TBI 62.5 MHz Receive Clock- odd code
RCLK0 group. In the TBI mode, RX_CLK is used
as RCLK0.
C5 86 120 RXD[7] O, Z TBI Receive Data code group [7:0]. In the
A2 87 121 RXD[6] TBI mode, RXD[7:0] present the data byte to
A1 89 123 RXD[5] be transmitted to the MAC. Symbols
C4 90 124 RXD[4] received on the cable are decoded and pre-
B3 91 125 RXD[3] sented on RXD[7:0].
C3 93 126 RXD[2]
D3 92 128 RXD[1] RXD[7:0] are synchronous to RCLK0 and
B2 95 3 RXD[0] RCLK1.
B1 94 4 RX_DV/ O, Z TBI Receive Data code group bit 8. In the
RXD8 TBI mode, RX_DV is used as RXD8.
RXD[9:0] are synchronous to RCLK0 and
RCLK1.
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March 4, 2009, Advance Page 15
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 3: TBI Interface (Continued)
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e
Pin # Pin # O, Z TBI Receive Data code group bit 9. In the
TBI mode, RX_ER is used as RXD9.
D2 3 8 RX_ER/ O, Z
I RXD[9:0] are synchronous to RCLK0 and
RXD9 RCLK1.
B5 84 115 CRS/ TBI Valid Comma Detect. In the TBI mode,
CRS is used as COMMA.
COMMA
TBI Mode Loopback. In the TBI mode, COL
B6 83 114 COL/LPBK is used to indicate loopback on the TBI.
When a "0 - 1" transition is sampled on this
pin, bit 0.14 is set to 1.
When a "1 - 0" is sampled on this pin, bit
0.14 is reset to 0.
If this feature is not used, the COL pin
should be driven low on the board. This pin
should not be left floating in TBI mode.
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 16 March 4, 2009, Advance
Signal Description
Pin Description
The RGMII interface supports 10/100/1000BASE-T and 1000BASE-X modes of operation.The RGMII interface
pins are also used for the RTBI interface. See Table 5 for RTBI pin definitions. The MAC interface pins are 3.3V
tolerant.
Table 4: RGMII Interface
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Type
Pin # Pin # I RGMII Transmit Clock provides a 125 MHz,
25 MHz, or 2.5 MHz reference clock with
E2 8 14 GTX_CLK/ I 50 ppm tolerance depending on speed. In
RGMII mode, GTX_CLK is used as TXC.
TXC
RGMII Transmit Data. In RGMII mode,
H2 16 24 TXD[3]/TD[3] TXD[3:0] are used as TD[3:0].
In RGMII mode, TXD[3:0] run at double data
G3 14 20 TXD[2]/TD[2] rate with bits [3:0] presented on the rising
edge of GTX_CLK, and bits [7:4] presented
G2 12 19 TXD[1]/TD[1] on the falling edge of GTX_CLK. In this
mode, TXD[7:4] are ignored.
F1 11 18 TXD[0]/TD[0]
In RGMII 10/100BASE-T modes, the trans-
mit data nibble is presented on TXD[3:0] on
the rising edge of GTX_CLK.
E1 9 16 TX_EN/ I RGMII Transmit Control. In RGMII mode,
TX_CTL TX_EN is used as TX_CTL. TX_EN is pre-
sented on the rising edge of GTX_CLK.
A logical derivative of TX_EN and TX_ER is
presented on the falling edge of GTX_CLK.
C1 2 7 RX_CLK/ O, Z RGMII Receive Clock provides a 125 MHz,
RXC 25 MHz, or 2.5 MHz reference clock with
50 ppm tolerance derived from the received
data stream depending on speed. In RGMII
mode, RX_CLK is used as RXC.
B1 94 4 RX_DV/ O, Z RGMII Receive Control. In RGMII mode,
RX_CTL RX_DV is used as RX_CTL. RX_DV is pre-
sented on the rising edge of RX_CLK.
A logical derivative of RX_DV and RX_ER is
presented on the falling edge of RX_CLK.
B3 91 125 RXD[3]/RD[3] O, Z RGMII Receive Data. In RGMII mode,
C3 93 126 RXD[2]/RD[2] RXD[3:0] are used as RD[3:0]. In RGMII
D3 92 128 RXD[1]/RD[1] mode, RXD[3:0] run at double data rate with
B2 95 3 RXD[0]/RD[0] bits [3:0] presented on the rising edge of
RX_CLK, and bits [7:4] presented on the fall-
ing edge of RX_CLK. In this mode, RXD[7:4]
are ignored.
In RGMII 10/100BASE-T modes, the receive
data nibble is presented on RXD[3:0] on the
rising edge of RX_CLK.
RXD[3:0] are synchronous to RX_CLK.
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 17
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
The RTBI interface supports 1000BASE-T mode of operation. The RTBI interface uses the same pins as the
RGMII interface. The MAC interface pins are 3.3V tolerant.
Table 5: RTBI Interface
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e
Pin # Pin # I RGMII Transmit Clock provides a 125 MHz
I reference clock with 50 ppm tolerance. In
E2 8 14 GTX_CLK/ RTBI mode, GTX_CLK is used as TXC.
I
TXC RTBI Transmit Data.
O, Z In RTBI mode, TXD[3:0] are used as
H2 16 24 TXD[3]/TD[3] O, Z TD[3:0]. TD[3:0] run at double data rate with
bits [3:0] presented on the rising edge of
G3 14 20 TXD[2]/TD[2] O, Z GTX_CLK, and bits [8:5] presented on the
falling edge of GTX_CLK. In this mode,
G2 12 19 TXD[1]/TD[1] TXD[7:4] are ignored.
F1 11 18 TXD[0]/TD[0] RTBI Transmit Data.
In RTBI mode, TX_EN is used as TD4_TD9.
E1 9 16 TX_EN/ TD4_TD9 runs at a double data rate with bit
4 presented on the rising edge of GTX_CLK,
TD4_TD9 and bit 9 presented on the falling edge of
GTX_CLK.
C1 2 7 RX_CLK/
RTBI Receive Clock provides a 125 MHz ref-
RXC erence clock with 50 ppm tolerance
derived from the received data stream. In
B3 91 125 RXD[3]/RD[3] RTBI mode, RX_CLK is used as RXC.
C3 93 126 RXD[2]/RD[2] RTBI Receive Data.
In RTBI mode, RXD[3:0] are used as
D3 92 128 RXD[1]/RD[1] RD[3:0]. RD[3:0] runs at double data rate
with bits [3:0] presented on the rising edge of
B2 95 3 RXD[0]/RD[0] RX_CLK, and bits [8:5] presented on the fall-
ing edge of RX_CLK. In this mode, RXD[7:4]
B1 94 4 RX_DV/ are ignored.
RD4_RD9 RTBI Receive Data.
In RTBI mode, RX_DV is used as
RD4_RD9. RD4_RD9 runs at a double data
rate with bit 4 presented on the rising edge
of RX_CLK, and bit 9 presented on the fall-
ing edge of RX_CLK.
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 18 March 4, 2009, Advance
Signal Description
Pin Description
Table 6: SGMII Interface
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Type
Pin # Pin # I SGMII Transmit Data. 1.25 GBaud input -
Positive and Negative.
A3 82 113 S_IN+ I/O
Input impedance on the S_IN pins may be
A4 81 112 S_IN- O, Z programmed for 50 ohm or 75 ohm imped-
ance by setting register 26.6. The input
A5 79 110 S_CLK+ impedance default setting is determined by
the 75/50 OHM configuration pin.
A6 80 109 S_CLK-
SGMII 625 MHz Receive Clock.
A7 77 107 S_OUT+
For Serial Interface modes
A8 75 105 S_OUT- (HWCFG_MODE[3:0] = 1x00) the S_CLK
pins become Signal Detect (SD) inputs.
SGMII Receive Data. 1.25 GBaud output -
Positive and Negative.
Output impedance on the S_OUT pins may
be programmed for 50 ohm or 75 ohm
impedance by setting register 26.5. Output
amplitude can be adjusted via register
26.2:0. The output impedance default setting
is determined by the 75/50 OHM configura-
tion pin.
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 19
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 7: 1.25 GHz Serial High Speed Interface
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e
Pin # Pin # I 1.25 GHz input - Positive and Negative.
When this interface is used as a MAC inter-
A3 82 113 S_IN+ I face, the MAC transmitter's positive output
O, Z connects to the S_IN+. The MAC transmit-
A4 81 112 S_IN- ter's negative output connects to the S_IN-.
O, Z
A5 79 110 S_CLK+/SD+ When this interface is used as a fiber inter-
face, the fiber-optic transceiver's positive
A6 80 109 S_CLK-/SD- output connects to the S_IN+. The fiber-optic
transceiver's negative output connects to the
A7 77 107 S_OUT+ S_IN-.
A8 75 105 S_OUT- Input impedance on the S_IN pins may be
programmed for 50 ohm or 75 ohm imped-
B3 91 125 RXD[3] ance by setting register 26.6. The input
impedance default setting is determined by
the 75/50 OHM configuration pin.
Signal Detect input.
For Serial Interface modes the S_CLK pins
become Signal Detect (SD) inputs.
1.25 GHz output - Positive and Negative.
When this interface is used as a MAC inter-
face, S_OUT+ connects to the MAC
receiver's positive input. S_OUT- connects
to the MAC receiver's negative input.
When this interface is used as a fiber inter-
face, S_OUT+ connects to the fiber-optic
transceiver's positive input. S_OUT- con-
nects to the fiber-optic transceiver's negative
input.
Output impedance on the S_OUT pins may
be programmed for 50 ohm or 75 ohm
impedance by setting register 26.5. Output
amplitude can be adjusted via register
26.2:0. The output impedance default setting
is determined by the 75/50 OHM configura-
tion pin.
Serial MAC interface Copper Link Status[1]
connection.
1 = Copper link up
0 = Copper link down
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Page 20 March 4, 2009, Advance
Signal Description
Pin Description
Table 7: 1.25 GHz Serial High Speed Interface (Continued)
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Type
Pin # Pin # Serial MAC interface Copper Link Status[0]
O, Z connection.
C3 93 126 RXD[2] 1 = Copper link down
0 = Copper link up
D3 92 128 RXD[1] O, Z
Serial MAC interface PHY_SIGDET[1] con-
B2 95 3 RXD[0] O, Z nection.
1 = S_OUT valid code groups according to
clause 36.
0 = S_OUT invalid
Serial MAC interface PHY_SIGDET[0] con-
nection.
1 = S_OUT invalid
0 = S_OUT valid code groups according to
clause 36
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 21
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 8: Management Interface and Interrupt
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin #
Pin # Pin # Ty p e
L3 25 35 MDC I MDC is the management data clock refer-
3.3V ence for the serial management interface. A
Tolerant continuous clock stream is not expected.
The maximum frequency supported is 8.3
MHz.
M1 24 33 MDIO I/O MDIO is the management data. MDIO
3.3V transfers management data in and out of the
Tolerant device synchronously to MDC. This pin
requires a pull-up resistor in a range from
1.5 kohm to 10 kohm.
L1 23 32 INTn D The polarity of the INTn pin may be pro-
grammed at hardware reset by setting the
INT_POL bit.
Polarity:
0 = Active High
1 = Active Low
Table 9: Two-Wire Serial Interface
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e
Pin # Pin # I Two-Wire Serial Interface (TWSI) serial
clock line. When the 88E1111 device is con-
L3 25 35 MDC/SCL I/O nected to the bus, MDC connects to the
serial clock line (SCL).
M1 24 33 MDIO/SDA Data is input on the rising edge of SCL, and
output on the falling edge.
TWSI serial data line. When the 88E1111
device is connected to the bus, MDIO con-
nects to the serial data line (SDA). This pin is
open-drain and may be wire-ORed with any
number of open-drain devices.
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Page 22 March 4, 2009, Advance
Signal Description
Pin Description
Table 10: LED Interface
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Type
Pin # Pin # Parallel LED output for 10BASE-T link or
O, mA speed. This active low LED pin may be pro-
C8 76 100 LED_LINK10 grammed in direct drive or combined LED
modes by programming register LED_LINK
Control register 24.4:3.
In direct drive LED mode, this pin indicates
10 Mbps link up or down.
In combined LED mode, the output from
LED_LINK10, LED_LINK100, and
LED_LINK1000 must be read together to
determine link and speed status.
LED_LINK10 is a multi-function pin used to
configure the 88E1111 device at the de-
assertion of hardware reset.
B8 74 99 LED_LINK100 O, mA Parallel LED output for 100BASE-TX link or
speed. This active low LED pin may be pro-
grammed in direct drive or combined LED
modes by programming register LED_LINK
Control register 24.4:3.
In direct drive LED mode, this pin indicates
100 Mbps link up or down.
In combined LED mode, the output from
LED_LINK10, LED_LINK100, and
LED_LINK1000 must be read together to
determine link and speed status.
LED_LINK100 is a multi-function pin used to
configure the 88E1111 device at the de-
assertion of hardware reset.
A9 73 98 LED_LINK1000 O, mA Parallel LED output for 1000BASE-T link/
speed or link indicator. This active low LED
pin may be programmed in direct drive or
combined LED modes by programming reg-
ister LED_LINK Control register 24.4:3.
In direct drive LED mode, this pin indicates
1000 Mbps link up or down.
In combined LED mode, the output from
LED_LINK1000 indicates link status.
LED_LINK1000 is a multi-function pin used
to configure the 88E1111 device at the de-
assertion of hardware reset.
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 23
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 10: LED Interface (Continued)
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e
Pin # Pin # Parallel LED duplex or duplex/collision
O, mA modes. The LED_DUPLEX pin may be pro-
E8 70 95 LED_DUPLEX grammed to Mode 1 or Mode 2 by setting
register bit 24.2.
Mode 1
Low = Full-duplex
High = Half-duplex
Blink = Collision
Mode 2
Low = Full-duplex
High = Half-duplex
Mode 3
Low = Fiber Link up
High = Fiber Link down
LED_DUPLEX is a multi-function pin used to
configure the 88E1111 device at the de-
assertion of hardware reset.
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Page 24 March 4, 2009, Advance
Signal Description
Pin Description
Table 10: LED Interface (Continued)
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Type
Pin # Pin # Parallel LED Receive Activity or Receive
O, mA Activity/Link modes. LED_RX may be pro-
C9 69 92 LED_RX grammed to Mode 1 or Mode 2 by setting
register bit 24.1.
Mode 1
Low = Receiving
High = Not receiving
Mode 2
Low = Link up
High = Link down
Blink = Receiving
D9 68 91 LED_TX O, mA LED_RX is a multi-function pin used to con-
figure the 88E1111 device at the de-asser-
tion of hardware reset.
Parallel LED Transmit Activity or RX/TX
Activity/Link modes. LED_TX may be pro-
grammed to Mode 1 or Mode 2 by setting
register bit 24.0.
Mode 1
Low = Transmitting
High = Not transmitting
Mode 2
Low = Link up
High = Link down
Blink = Transmitting or receiving
LED_TX is a multi-function pin used to con-
figure the 88E1111 device at the de-asser-
tion of hardware reset.
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 25
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 11: JTAG Interface
117-TFBGA 96-BCC 128-PQFP Pin Type Pin Description
Pin # Name
Pin # Pin # I, PU Boundary scan test data input.
I, PU TDI contains an internal 150 kohm pull-up
L7 44 67 TDI I, PU resistor.
I, PU
L8 46 69 TMS Boundary scan test mode select input.
O, Z TMS contains an internal 150 kohm pull-up
L9 49 70 TCK resistor.
M9 47 68 TRSTn Boundary scan test clock input.
TCK contains an internal 150 kohm pull-up
K8 50 72 TDO resistor.
Boundary scan test reset input. Active low.
TRSTn contains an internal 150 kohm pull-
up resistor as per the 1149.1 specification.
After power up, the JTAG state machine
should be reset by applying a low signal on
this pin, or by keeping TMS high and apply-
ing 5 TCK pulses, or by pulling this pin low
by a 4.7 kohm resistor.
Boundary scan test data output.
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Page 26 March 4, 2009, Advance
Signal Description
Pin Description
Table 12: Clock/Configuration/Reset/I/O
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Type
Pin # Pin # O Clock 125. A generic 125 MHz clock refer-
I ence generated for use on the MAC device.
K2 22 31 125CLK This output can be disabled via DIS_125
I through the CONFIG[3] pin.
D8 65 88 CONFIG[0]
I CONFIG[0] pin configures PHY_ADR[2:0]
E9 64 87 CONFIG[1] bits of the physical address.
F8 63 86 CONFIG[2] Each LED pin is hardwired to a constant
value. The values associated to the CON-
FIG[0] pin are latched at the de-assertion of
hardware reset.
CONFIG[0] pin must be tied to one of the
pins based on the configuration options
selected. They should not be left floating.
For the Two-Wire Serial Interface (TWSI)
device address, the lower 5 bits, which are
PHYADR[4:0], are latched during hardware
reset, and the device address bits [6:5] are
fixed at `10'.
CONFIG[1] pin configures PHY_ADR[4:3]
and ENA_PAUSE options.
Each LED pin is hardwired to a constant
value. The values associated to the CON-
FIG[1] pin are latched at the de-assertion of
hardware reset.
CONFIG[1] pin must be tied to one of the
pins based on the configuration options
selected. They should not be left floating.
For the TWSI device address, the lower 5
bits, which are PHYADR[4:0], are latched
during hardware reset, and the device
address bits [6:5] are fixed at `10'.
CONFIG[2] pin configures ANEG[3:1] bits.
Each LED pin is hardwired to a constant
value. The values associated to the CON-
FIG[2] pin are latched at the de-assertion of
hardware reset.
CONFIG[2] pin must be tied to one of the
pins based on the configuration options
selected. They should not be left floating.
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 27
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 12: Clock/Configuration/Reset/I/O (Continued)
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e
Pin # Pin # CONFIG[3] pin configures ANEG[0],
I ENA_XC, and DIS_125 options.
G7 61 82 CONFIG[3]
Each LED pin is hardwired to a constant
F9 60 81 CONFIG[4] I value. The values associated to the CON-
FIG[3] pin are latched at the de-assertion of
G9 59 80 CONFIG[5] I hardware reset.
G8 58 79 CONFIG[6] I CONFIG[3] pin must be tied to one of the
pins based on the configuration options
H8 56 77 SEL_FREQ selected. They should not be left floating.
H9 55 76 XTAL1 I CONFIG[4] pin configures
HWCFG_MODE[2:0] options.
J9 54 75 XTAL2 0
CONFIG[5] pin configures DIS_FC,
DIS_SLEEP, and HWCFG_MODE[3]
options.
CONFIG[6] pin configures SEL_TWSI,
INT_POL, and 75/50 OHM options.
Frequency Selection for XTAL1 input
NC = Selects 25 MHz clock input.
Tied low = Selects 125 MHz clock input.
Internally divided to 25 MHz. SEL_FREQ is
internally pulled up.
Reference Clock. 25 MHz 50 ppm or 125
MHz 50 ppm oscillator input. PLL clocks
are not recommended.
Reference Clock. 25 MHz 50 ppm toler-
ance crystal reference. When the XTAL2 pin
is not connected, it should be left floating.
There is no option for a 125 MHz crystal.
See "Crystal Oscillator" Application Note for
details.
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 28 March 4, 2009, Advance
Signal Description
Pin Description
Table 12: Clock/Configuration/Reset/I/O (Continued)
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Type
Pin # Pin # Hardware reset. Active low. XTAL1 must be
I active for a minimum of 10 clock cycles
K3 28 36 RESETn before the rising edge of RESETn. RESETn
must be pulled high for normal operation.
L4 27 37 COMA I
COMA disables all active circuitry to draw
absolute minimum power. The COMA power
mode can be activated by asserting high on
the COMA pin. To deactivate the COMA
power mode, tie the COMA pin low. Upon
deactivating COMA mode, the 88E1111
device will continue normal operation.
The COMA power mode cannot be enabled
as long as hardware reset is enabled.
In COMA mode, the PHY cannot wake up on
its own by detecting activity on the CAT 5
cable.
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 29
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 13: Test
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e
Pin # Pin # Test pins. These pins should be left floating
Analog but brought out for probing.
M5 37 53 HSDAC+ PD
M6 38 54 HSDAC-
Table 14: Control and Reference
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e
Pin # Pin # Constant voltage reference. External 5.0
Analog kohm 1% resistor connection to VSS
M2 30 39 RSET I required for each pin.
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Page 30 March 4, 2009, Advance
Signal Description
Pin Description
Table 15: Power & Ground
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Type Analog Power. 2.5V.
Pin # Pin #
Power
B7 32 44 AVDD
M3 35 49
M4 36 52
M7 40 59
M8 45 64
N5 78 104
C6 1 2 DVDD Power Digital Power. 1.0V (Instead of 1.0V, 1.2V
can be used).
C7 6 6
D7 10 12
E3 15 17
E7 57 23
F3 62 27
J3 67 78
J7 71 85
85 90
96
117
118
B9 52 73 VDDOH Power 2.5V Power Supply for LED and CONFIG
pins.
F7 66 89
J8 72 97
K9 26 34 VDDOX Power 2.5V Supply for the MDC/MDIO, INTn,
Power 125CLK, RESETn, JTAG pin Power.
L2 48 71
2.5V I/O supply for the MAC interface pins.
B4 5 5 VDDO
C2 21 11
K1 88 30
96 122
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 31
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Table 15: Power & Ground (Continued)
117-TFBGA 96-BCC 128-PQFP Pin Name Pin Description
Pin # Ty p e Global ground
Pin # Pin #
GND
D4 0 1 VSS
D5 9
D6 15
E4 21
E5 22
E6 38
F4 40
F5 43
F6 45
G4 48
G5 51
G6 55
H4 58
H5 60
H6 63
J4 65
J5 66
J6 83
K4 84
K5 93
K6 94
L5 101
L6 102
103
106
108
111
116
119
127
H7 53 74 VSSC GND Ground reference for XTAL1 and XTAL2
NC pins. This pin must be connected to the
G1 13 50 NC ground.
K7 51 No connect. Do not connect these pins to
anything
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Page 32 March 4, 2009, Advance
Signal Description
I/O State at Various Test or Reset Modes
1.5 I/O State at Various Test or Reset Modes
Pin(s) Isolate Loopback Software Hardware Power Down Coma Power
or Normal Reset Reset Down and
MDI[3:0] Active operation Tri-state Tri-state Tri-state Isolate
TX_CLK Tri-state Tri-state Low Reg. 16.3 state Tri-state
Active Reg. 16.3 0 = Low Reg. 16.3 Tri-state
state High 1 = Active state
Active 0 = Low 0 = Low Tri-state
1 = Active High 0 = Static but
can be either
RXD[0], Tri-state Active High high or low
RXD[2] Tri-state Low
Active High
RXD[7:3,1], Tri-state Tri-state
RX_DV, TBI mode - Low Low Low Tri-state
RX_ER, input Reg. 16.3
CRS else -active state Tri-state TBI mode - TBI mode - Tri-state
Active 0 = Low input input
COL 1 = Active Low else - low else - low Tri-state
Reg. 16.3 state
RX_CLK Tri-state Tri-state 0 = Low Reg. 16.3 Active
1 = Active state
S_CLK Active Active Tri-state Tri-state 0 = Low Active
S_OUT Tri-state Reg. 16.3 state 0 = Static but Tri-state
Active Active Active High 0 = Tri-state can be either High
MDIO Tri-state 1 = Active high or low Tri-state
INT Active Active Tri-state Toggle Active Reg. 16.4
LED_*** Tri-state Tri-state state
TDO Active Active High High 0 = Toggle
125CLK Tri-state Tri-state 1 = Low
Tri-state Tri-state Tri-state Reg. 16.4 state
0 = Toggle Tri-state
Reg. 16.4 Reg. 16.4 Reg. 16.4 1 = Low
state state state High
0 = Toggle 0 = Toggle 0 = Toggle
1 = Low 1 = Low 1 = Low Active
Reg. 16.3
state
0 = Static but
can be either
high or low
0 = Low
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 33
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
1.6 117-Pin TFBGA Pin Assignment List - Alphabetical by
Signal Name
Pin # Pin Name Pin # Pin Name
K2 125CLK A9 LED_LINK1000
B7 AVDD C9 LED_RX
M3 AVDD D9 LED_TX
M4 AVDD L3 MDC
M7 AVDD N2 MDI[0]-
M8 AVDD N1 MDI[0]+
N5 AVDD N4 MDI[1]-
B6 COL N3 MDI[1]+
L4 COMA N7 MDI[2]-
D8 CONFIG[0] N6 MDI[2]+
E9 CONFIG[1] N9 MDI[3]-
F8 CONFIG[2] N8 MDI[3]+
G7 CONFIG[3] M1 MDIO
F9 CONFIG[4] G1 NC
G9 CONFIG[5] K7 NC
G8 CONFIG[6] K3 RESETn
B5 CRS M2 RSET
C6 DVDD B2 RXD0
C7 DVDD D3 RXD1
D7 DVDD C3 RXD2
E3 DVDD B3 RXD3
E7 DVDD C4 RXD4
F3 DVDD A1 RXD5
J3 DVDD A2 RXD6
J7 DVDD C5 RXD7
E2 GTX_CLK C1 RX_CLK
M6 HSDAC- B1 RX_DV
M5 HSDAC+ D2 RX_ER
L1 INTn A6 S_CLK-
E8 LED_DUPLEX A5 S_CLK+
C8 LED_LINK10 A4 S_IN-
B8 LED_LINK100 A3 S_IN+
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 34 March 4, 2009, Advance
Signal Description
117-Pin TFBGA Pin Assignment List - Alphabetical by Signal Name
1.6 117-Pin TFBGA Pin Assignment List - Alphabetical by
Signal Name (Continued)
Pin # Pin Name Pin # Pin Name
A8 S_OUT- D4 VSS
A7 S_OUT+ D5 VSS
H8 SEL_FREQ D6 VSS
L9 TCK E4 VSS
L7 TDI E5 VSS
K8 TDO E6 VSS
L8 TMS F4 VSS
M9 TRSTn F5 VSS
F1 TXD0 F6 VSS
G2 TXD1 G4 VSS
G3 TXD2 G5 VSS
H2 TXD3 G6 VSS
H1 TXD4 H4 VSS
H3 TXD5 H5 VSS
J1 TXD6 H6 VSS
J2 TXD7 J4 VSS
D1 TX_CLK J5 VSS
E1 TX_EN J6 VSS
F2 TX_ER K4 VSS
B4 VDDO K5 VSS
C2 VDDO K6 VSS
K1 VDDO L5 VSS
B9 VDDOH L6 VSS
F7 VDDOH H7 VSSC
J8 VDDOH H9 XTAL1
K9 VDDOX J9 XTAL2
L2 VDDOX
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 35
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
1.7 96-Pin BCC Pin Assignment List - Alphabetical by
Signal Name
Pin # Pin Name Pin # Pin Name
22 125CLK 74 LED_LINK100
32 AVDD 73 LED_LINK1000
35 AVDD 69 LED_RX
36 AVDD 68 LED_TX
40 AVDD 25 MDC
45 AVDD 31 MDI[0]-
78 AVDD 29 MDI[0]+
83 COL 34 MDI[1]-
27 COMA 33 MDI[1]+
65 CONFIG[0] 41 MDI[2]-
64 CONFIG[1] 39 MDI[2]+
63 CONFIG[2] 43 MDI[3]-
61 CONFIG[3] 42 MDI[3]+
60 CONFIG[4] 24 MDIO
59 CONFIG[5] 13 NC
58 CONFIG[6] 51 NC
84 CRS 28 RESETn
1 DVDD 30 RSET
6 DVDD 95 RXD0
10 DVDD 92 RXD1
15 DVDD 93 RXD2
57 DVDD 91 RXD3
62 DVDD 90 RXD4
67 DVDD 89 RXD5
71 DVDD 87 RXD6
85 DVDD 86 RXD7
8 GTX_CLK 2 RX_CLK
38 HSDAC- 94 RX_DV
37 HSDAC+ 3 RX_ER
23 INTn 80 S_CLK-
70 LED_DUPLEX 79 S_CLK+
76 LED_LINK10 81 S_IN-
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 36 March 4, 2009, Advance
Signal Description
96-Pin BCC Pin Assignment List - Alphabetical by Signal Name
1.7 96-Pin BCC Pin Assignment List - Alphabetical by
Signal Name (Continued)
Pin # Pin Name Pin # Pin Name
82 S_IN+ 4 TX_CLK
75 S_OUT- 9 TX_EN
77 S_OUT+ 7 TX_ER
56 SEL_FREQ 5 VDDO
49 TCK 21 VDDO
44 TDI 88 VDDO
50 TDO 96 VDDO
46 TMS 52 VDDOH
47 TRSTn 66 VDDOH
11 TXD0 72 VDDOH
12 TXD1 26 VDDOX
14 TXD2 48 VDDOX
16 TXD3 0 VSS
17 TXD4 53 VSSC
18 TXD5 55 XTAL1
19 TXD6 54 XTAL2
20 TXD7
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 37
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
1.8 128-Pin PQFP Pin Assignment List - Alphabetical by
Signal Name
Pin # Pin Name Pin # Pin Name
31 125CLK 32 INTn
44 AVDD 95 LED_DUPLEX
49 AVDD 100 LED_LINK10
52 AVDD 99 LED_LINK100
59 AVDD 98 LED_LINK1000
64 AVDD 92 LED_RX
104 AVDD 91 LED_TX
114 COL 35 MDC
37 COMA 41 MDI[0]+
88 CONFIG[0] 42 MDI[0]-
87 CONFIG[1] 46 MDI[1]+
86 CONFIG[2] 47 MDI[1]-
82 CONFIG[3] 56 MDI[2]+
81 CONFIG[4] 57 MDI[2]-
80 CONFIG[5] 61 MDI[3]+
79 CONFIG[6] 62 MDI[3]-
115 CRS 33 MDIO
2 DVDD 50 NC
6 DVDD 36 RESETn
12 DVDD 39 RSET
17 DVDD 7 RX_CLK
23 DVDD 4 RX_DV
27 DVDD 8 RX_ER
78 DVDD 3 RXD0
85 DVDD 128 RXD1
90 DVDD 126 RXD2
96 DVDD 125 RXD3
117 DVDD 124 RXD4
118 DVDD 123 RXD5
14 GTX_CLK 121 RXD6
53 HSDAC+ 120 RXD7
54 HSDAC- 110 S_CLK+
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 38 March 4, 2009, Advance
Signal Description
128-Pin PQFP Pin Assignment List - Alphabetical by Signal Name
1.8 128-Pin PQFP Pin Assignment List - Alphabetical by
Signal Name (Continued)
Pin # Pin Name Pin # Pin Name
109 S_CLK- 9 VSS
113 S_IN+ 15 VSS
112 S_IN- 21 VSS
107 S_OUT+ 22 VSS
105 S_OUT- 38 VSS
77 SEL_FREQ 40 VSS
70 TCK 43 VSS
67 TDI 45 VSS
72 TDO 48 VSS
69 TMS 51 VSS
68 TRSTn 55 VSS
10 TX_CLK 58 VSS
16 TX_EN 60 VSS
13 TX_ER 63 VSS
18 TXD0 65 VSS
19 TXD1 66 VSS
20 TXD2 83 VSS
24 TXD3 84 VSS
25 TXD4 93 VSS
26 TXD5 94 VSS
28 TXD6 101 VSS
29 TXD7 102 VSS
5 VDDO 103 VSS
11 VDDO 106 VSS
30 VDDO 108 VSS
122 VDDO 111 VSS
73 VDDOH 116 VSS
89 VDDOH 119 VSS
97 VDDOH 127 VSS
34 VDDOX 74 VSSC
71 VDDOX 76 XTAL1
1 VSS 75 XTAL2
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 39
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Section 2. Package Mechanical Dimensions
2.1 117-pin TFBGA Package
(All dimensions in mm.)
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 40 March 4, 2009, Advance
Package Mechanical Dimensions
117-pin TFBGA Package
Table 16: 117-Pin TFBGA Package Dimensions
Dimensions in mm
Symbol MIN NOM MAX
A -- -- 1.54
A1 0.60
A2 0.40 0.50 0.94
c 0.84 0.89 0.40
D 0.32 0.36 10.10
E 9.90 10.00 14.10
D1 13.90 14.00
E1 8.00 --
e -- 12.00 --
b -- 1.00 --
aaa -- 0.60 0.70
bbb 0.50 0.20
ccc 0.25
ddd 0.35
0.15
MD/ME
NOTE:
1. CONTROLLING DIMENSION: MILLIMETER.
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL
DIAMETER, PARALLEL TO PRIMARY DATUM C.
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 41
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
2.2 96-pin BCC Package - Top View
PIN 1 CORNER 9.000.10
X 73
71
0.300.05 75 74
0.08 M Z X Y
1
9.000.10
96C0.23
95
0.4000.05
0.08 M Z X Y
DETAIL "A" (1X)
23 25 47 49 51
24 27 50
Y 0.15
TOP VIEW
0.6700.025
0.20 Z
Z 0.80 MAX 0.05 Z
0.0750.025
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 42 March 4, 2009, Advance
Package Mechanical Dimensions
96-Pin BCC Package - Bottom View
2.3 96-Pin BCC Package - Bottom View
4.100 3.50 ''A''
0.600 TYP. 0.600.10 (PIN 1 CORNER)
5.800 4.800 0.600.10
3.50
CL.(PKG.)
9.00
8.20 0.2
7.20
"B"
0.2 0.600 TYP. 0.400.05
7.00 4.100
7.200CL.(PKG.) 0.08 M Z X Y
8.20
9.00 0.300.05
BOTTOM VIEW 0.08 M Z X Y
DETAIL "B" (95X)
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 43
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
2.4 128-Pin PQFP Package 65
64
23.20 0.20
20.00 0.10
102
103
14.00 0.10
17.20 0.20
128 PIN1 39
INDICATOR 38
1.6 Nominal
1 3.40 Max
0.25 0.22 0.05 0.88 0.15
min
0.5 Basic
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 44 March 4, 2009, Advance
Order Information
Ordering Part Numbers and Package Markings
Section 3. Order Information
3.1 Ordering Part Numbers and Package Markings
Figure 5 shows the ordering part numbering scheme for the 88E1111 devices. Contact Marvell FAEs or sales
representatives for complete ordering information.
Figure 5: Sample Part Number
88E1111 xx xxx Cxxx - xxxx
Part Number Custom Code (optional)
88E1111 Custom Code
Custom Code Temperature Range
C = Commercial
Package Code I = Industrial
BAB = 117-pin TFBGA
CAA = 96-pin BCC Environmental
RCJ - 128-pin PQFP "-" = RoHS 5/6 compliant package
1 = RoHS 6/6 compliant package
Table 17: 88E1111 Part Order Options - RoHS 5/6 Compliant Package
Package Type Part Order Number
88E1111 117-pin TFBGA - Commercial 88E1111-XX-BAB-C000
88E1111 117-pin TFBGA - Industrial 88E1111-XX-BAB-I000
88E1111 96-pin BCC - Commercial 88E1111-XX-CAA-C000
88E1111 96-pin BCC - Industrial 88E1111-XX-CAA-I000
88E1111 128-pin PQFP - Commercial 88E1111-XX-RCJ-C000
Table 18: 88E1111 Part Order Options - RoHS 6/6 Compliant Package
Package Type Part Order Number
88E1111 117-pin TFBGA - Commercial 88E1111-XX-BAB1C000
88E1111 117-pin TFBGA - Industrial 88E1111-XX-BAB1I000
88E1111 96-pin BCC - Commercial 88E1111-XX-CAA1C000
88E1111 96-pin BCC - Industrial 88E1111-XX-CAA1I000
88E1111 128-pin PQFP - Commercial 88E1111-XX-RCJ1C000
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 45
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
3.1.1 RoHS 5/6 Compliant Marking Examples
Figure 6 is an example of the package marking and pin 1 location for the 88E1111 117-pin TFBGA commercial
RoHS 5/6 compliant package.
Figure 6: 88E1111 117-pin TFBGA Commercial RoHS 5/6 Compliant Package Marking and Pin
1 Location
Logo
Country of origin 88E1111-BAB Part number, package code, environmental code
Environmental Code - No code = RoHS 5/6
(Contained in the mold ID or Lot Number
marked as the last line on YYWW xx@ 1 = RoHS 6/6
the package.)
Country Date code, custom code, assembly plant code
YYWW = Date code
xx = Custom code
@ = Assembly location code
Pin 1 location
Note: The above example is not drawn to scale. Location of markings is approximate.
Figure 7 is an example of the package marking and pin 1 location for the 88E1111 117-pin TFBGA Industrial RoHS
5/6 compliant package.
Figure 7: 88E1111 117-pin TFBGA Industrial RoHS 5/6 Compliant Package Marking and Pin 1
Location
Logo
Country of origin 88E1111-BAB Part number, package code, environmental code
Environmental Code - No code = RoHS 5/6
(Contained in the mold ID or Lot Number
marked as the last line on YYWW xx@ 1 = RoHS 6/6
the package.)
Country I Date code, custom code, assembly plant code
YYWW = Date code
xx = Custom code
@ = Assembly location code
Industrial Grade Package Marking
Pin 1 location
Note: The above example is not drawn to scale. Location of markings is approximate.
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 46 March 4, 2009, Advance
Order Information
Ordering Part Numbers and Package Markings
Figure 8 is an example of the package marking and pin 1 location for the 88E1111 96-pin BCC Commercial RoHS
5/6 compliant package.
Figure 8: 88E1111 96-pin BCC Commercial RoHS 5/6 Compliant Package Marking and Pin 1
Location
Logo
Country of origin 88E1111-CAA Part number, package code, environmental code
Environmental Code - No code = RoHS 5/6
(Contained in the mold ID or Lot Number
marked as the last line on YYWW xx@ 1 = RoHS 6/6
the package.)
Country Date code, custom code, assembly plant code
YYWW = Date code
xx = Custom code
@ = Assembly location code
Pin 1 location
Note: The above example is not drawn to scale. Location of markings is approximate.
Figure 9 is an example of the package marking and pin 1 location for the 88E1111 96-pin BCC Industrial RoHS 5/
6 compliant package.
Figure 9: 88E1111 96-pin BCC Industrial RoHS 5/6 Compliant Package Marking and Pin 1 Loca-
tion
Logo
Country of origin 88E1111-CAA Part number, package code, environmental code
Environmental Code - No code = RoHS 5/6
(Contained in the mold ID or Lot Number
marked as the last line on YYWW xx@ 1 = RoHS 6/6
the package.)
Country I Date code, custom code, assembly plant code
YYWW = Date code
xx = Custom code
@ = Assembly location code
Industrial Grade Package Marking
Pin 1 location
Note: The above example is not drawn to scale. Location of markings is approximate.
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 47
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Figure 10 is an example of the package marking and pin 1 location for the 88E1111 128-pin PQFP Commercial
RoHS 5/6 compliant package.
Figure 10: 88E1111 128-pin PQFP Commercial RoHS 5/6 Compliant Package Marking and Pin 1
Location
Logo
Country of origin 88E1111-RCJ Part number, package code, environmental code
Environmental Code - No code = RoHS 5/6
(Contained in the mold ID or Lot Number
marked as the last line on YYWW xx@ 1 = RoHS 6/6
the package.)
Country Date code, custom code, assembly plant code
YYWW = Date code
xx = Custom code
@ = Assembly location code
Pin 1 location
Note: The above example is not drawn to scale. Location of markings is approximate.
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 48 March 4, 2009, Advance
Order Information
Ordering Part Numbers and Package Markings
3.1.2 RoHS 6/6 Compliant Marking Examples
Figure 11 is an example of the package marking and pin 1 location for the 88E1111 117-pin TFBGA commercial
RoHS 6/6 compliant package.
Figure 11: 88E1111 117-pin TFBGA Commercial RoHS 6/6 Compliant Package Marking and Pin
1 Location
Logo
Country of origin 88E1111-BAB1 Part number, package code, environmental code
Environmental Code - No code = RoHS 5/6
(Contained in the mold ID or Lot Number
marked as the last line on YYWW xx@ 1 = RoHS 6/6
the package.)
Country Date code, custom code, assembly plant code
YYWW = Date code
xx = Custom code
@ = Assembly location code
Pin 1 location
Note: The above example is not drawn to scale. Location of markings is approximate.
Figure 12 is an example of the package marking and pin 1 location for the 88E1111 117-pin TFBGA industrial
RoHS 6/6 compliant package.
Figure 12: 88E1111 117-pin TFBGA Industrial RoHS 6/6 Compliant Package Marking and Pin 1
Location
Logo
Country of origin 88E1111-BAB1 Part number, package code, environmental code
Environmental Code - No code = RoHS 5/6
(Contained in the mold ID or Lot Number
marked as the last line on YYWW xx@ 1 = RoHS 6/6
the package.)
Country I Date code, custom code, assembly plant code
YYWW = Date code
xx = Custom code
@ = Assembly location code
Industrial Grade Package Marking
Pin 1 location
Note: The above example is not drawn to scale. Location of markings is approximate.
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 49
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Figure 13 is an example of the package marking and pin 1 location for the 88E1111 96-pin BCC Commercial
RoHS 6/6 compliant package.
Figure 13: 88E1111 96-pin BCC Commercial RoHS 6/6 Compliant Package Marking and Pin 1
Location
Logo
Country of origin 88E1111-CAA1 Part number, package code, environmental code
Environmental Code - No code = RoHS 5/6
(Contained in the mold ID or Lot Number
marked as the last line on YYWW xx@ 1 = RoHS 6/6
the package.)
Country Date code, custom code, assembly plant code
YYWW = Date code
xx = Custom code
@ = Assembly location code
Pin 1 location
Note: The above example is not drawn to scale. Location of markings is approximate.
Figure 14 is an example of the package marking and pin 1 location for the 88E1111 96-pin BCC Industrial RoHS 6/
6 compliant package.
Figure 14: 88E1111 96-pin BCC Industrial RoHS 6/6 Compliant Package Marking and Pin 1 Loca-
tion
Logo
Country of origin 88E1111-CAA1 Part number, package code, environmental code
Environmental Code - No code = RoHS 5/6
(Contained in the mold ID or Lot Number
marked as the last line on YYWW xx@ 1 = RoHS 6/6
the package.)
Country I Date code, custom code, assembly plant code
YYWW = Date code
xx = Custom code
@ = Assembly location code
Industrial Grade Package Marking
Pin 1 location
Note: The above example is not drawn to scale. Location of markings is approximate.
Doc. No. MV-S105540-00, Rev. -- Document Classification: Proprietary Information Copyright 2009 Marvell
Page 50 March 4, 2009, Advance
Order Information
Ordering Part Numbers and Package Markings
Figure 15 is an example of the package marking and pin 1 location for the 88E1111 128-pin PQFP Commercial
RoHS 6/6 compliant package.
Figure 15: 88E1111 128-pin PQFP Commercial RoHS 6/6 Compliant Package Marking and Pin 1
Location
Logo
Country of origin 88E1111-RCJ1 Part number, package code, environmental code
Environmental Code - No code = RoHS 5/6
(Contained in the mold ID or Lot Number
marked as the last line on YYWW xx@ 1 = RoHS 6/6
the package.)
Country Date code, custom code, assembly plant code
YYWW = Date code
xx = Custom code
@ = Assembly location code
Pin 1 location
Note: The above example is not drawn to scale. Location of markings is approximate.
Copyright 2009 Marvell Document Classification: Proprietary Information Doc. No. MV-S105540-00, Rev. --
March 4, 2009, Advance Page 51
Back Cover
Marvell Semiconductor, Inc.
5488 Marvell Lane
Santa Clara, CA 95054, USA
Tel: 1.408.222.2500
Fax: 1.408.752.9028
www.marvell.com
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