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74LVTH162244MTD

器件型号:74LVTH162244MTD
器件类别:逻辑    逻辑   
厂商名称:Fairchild
厂商官网:http://www.fairchildsemi.com/
标准:
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器件描述

LVT SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48

参数
Brand NameFairchild Semiconduc
是否无铅不含铅
是否Rohs认证符合
厂商名称Fairchild
零件包装代码TSSOP
包装说明TSSOP, TSSOP48,.3,20
针数48
制造商包装代码48 LD,TSSOP,JEDEC MO-153, 6.1MM WIDE
Reach Compliance Codecompli
ECCN代码EAR99
控制类型ENABLE LOW
系列LVT
JESD-30 代码R-PDSO-G48
JESD-609代码e4
长度12.5 mm
逻辑集成电路类型BUS DRIVER
最大I(ol)0.012 A
湿度敏感等级2
位数4
功能数量4
端口数量2
端子数量48
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE WITH SERIES RESISTOR
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP48,.3,20
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)260
电源3.3 V
Prop。Delay @ Nom-Su4 ns
传播延迟(tpd)4.8 ns
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)2.7 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术BICMOS
温度等级INDUSTRIAL
端子面层Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式GULL WING
端子节距0.5 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度6.1 mm
Base Number Matches1

文档预览

74LVT162244 • 74LVTH162244 Low Voltage 16-Bit Buffer/Line Driver with 3-STATE Outputs and 25: Series
Resistors in the Outputs
March 1999
Revised June 2005
74LVT162244 • 74LVTH162244
Low Voltage 16-Bit Buffer/Line Driver
with 3-STATE Outputs
and 25: Series Resistors in the Outputs
General Description
The LVT162244 and LVTH162244 contain sixteen non-
inverting buffers with 3-STATE outputs designed to be
employed as a memory and address driver, clock driver, or
bus oriented transmitter/receiver. The device is nibble con-
trolled. Individual 3-STATE control inputs can be shorted
together for 8-bit or 16-bit operation.
The LVT162244 and LVTH162244 are designed with
equivalent 25
:
series resistance in both the HIGH and
LOW states of the output. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The LVTH162244 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These buffers and line drivers are designed for low-voltage
(3.3V) V
CC
applications, but with the capability to provide a
TTL interface to a 5V environment. The LVT162244 and
LVTH162244 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162244),
also available without bushold feature (74LVT162244).
s
Live insertion/extraction permitted
s
Power Up/Power Down high impedance provides glitch-
free bus loading
s
Outputs include equivalent series resistance of 25
:
to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s
Functionally compatible with the 74 series 162244
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device
!
1000V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
74LVT162244G
(Note 1)(Note 2)
74LVT162244MEA
(Note 2)
74LVT162244MTD
(Note 2)
74LVTH162244G
(Note 1)(Note 2)
74LVTH162244MEA
74LVTH162244MEX
74LVTH162244MTD
74LVTH162244MTX
Package
Number
BGA54A
MS48A
MTD48
BGA54A
MS48A
MS48A
MTD48
MTD48
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[Tube]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[Tape and Reel]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[Tube]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[Tape and Reel]
Note 1:
Ordering code “G” indicates Trays.
Note 2:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2005 Fairchild Semiconductor Corporation
DS012445
www.fairchildsemi.com
74LVT162244 • 74LVTH162244
Logic Symbol
Pin Descriptions
Pin Names
OE
n
I
0
–I
15
O
0
–O
15
NC
Description
Output Enable Inputs (Active LOW)
Inputs
Outputs
No Connect
Connection Diagrams
Pin Assignment for SSOP and TSSOP
FBGA Pin Assignments
1
A
B
C
D
E
F
G
H
J
O
0
O
2
O
4
O
6
O
8
O
10
O
12
O
14
O
15
2
NC
O
1
O
3
O
5
O
7
O
9
O
11
O
13
NC
3
OE
1
NC
V
CC
GND
GND
GND
V
CC
NC
OE
4
4
OE
2
NC
V
CC
GND
GND
GND
V
CC
NC
OE
3
5
NC
I
1
I
3
I
5
I
7
I
9
I
11
I
13
NC
6
I
0
I
2
I
4
I
6
I
8
I
10
I
12
I
14
I
15
Truth Table
Inputs
OE
1
L
L
H
OE
2
L
L
H
OE
3
L
Pin Assignment for FBGA
L
H
OE
4
L
L
H
H
Z
HIGH Voltage Level
High Impedance
Outputs
I
0
–I
3
L
H
X
I
4
–I
7
L
H
X
I
8
–I
11
L
H
X
I
12
–I
15
L
H
X
L LOW Voltage Level
X Immaterial
O
0
–O
3
L
H
Z
O
4
–O
7
L
H
Z
O
8
–O
11
L
H
Z
O
12
–O
15
L
H
Z
(Top Thru View)
www.fairchildsemi.com
2
74LVT162244 • 74LVTH162244
Functional Description
The LVT162244 and LVTH162244 contain sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits)
controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to
obtain full 16-bit operation.
Logic Diagram
3
www.fairchildsemi.com
74LVT162244 • 74LVTH162244
Absolute Maximum Ratings
(Note 3)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 4)
V
I

GND
V
O

GND
V
O
!
V
CC
V
O
!
V
CC
Output at HIGH State
Output at LOW State
V
mA
mA
mA
mA
mA

0.5 to

4.6

0.5 to

7.0

0.5 to

7.0

0.5 to

7.0

50

50
64
128
r
64
r
128

65 to

150
q
C
Recommended Operating Conditions
Symbol
V
CC
V
I
I
OH
I
OL
T
A
Supply Voltage
Input Voltage
HIGH-Level Output Current
LOW-Level Output Current
Free Air Operating Temperature
Input Edge Rate, V
IN
0.8V–2.0V, V
CC
3.0V
Parameter
Min
2.7
0
Max
3.6
5.5
Units
V
V
mA
mA

12
12

40
0

85
10
q
C
ns/V
'
t/
'
V
Note 3:
Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4:
I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
V
OH
V
OL
I
I(HOLD)
(Note 5)
I
I(OD)
(Note 5)
I
I
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
I
OFF
I
PU/PD
I
OZL
I
OZH
I
OZH

I
CCH
I
CCL
I
CCZ
Power Off Leakage Current
Power Up/Down
3-STATE Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Bushold Input Minimum Drive
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
3.0
2.7
3.0
3.0
3.0
3.6
3.6
3.6
0
0–1.5V
3.6
3.6
3.6
3.6
3.6
3.6
75
V
CC

0.2
2.0
0.2
0.8
2.0
0.8
T
A

40
q
C to

85
q
C
Max
Min
Units
V
V
V
V
V
I
I
Conditions

1.2

18 mA
V
O
d
0.1V or
V
O
t
V
CC

0.1V
I
OH
I
OH
I
OL
I
OL
V
I
V
I

100
P
A

12 mA
100
P
A
12 mA
0.8V
2.0V

75
500
P
A
P
A
10
(Note 6)
(Note 7)
V
I
5.5V
0V or V
CC
0V
V
CC
0.5V to 3.0V
GND or V
CC
0.5V
3.0V
V
I
V
I
V
I

500
r
1

5
1
P
A
r
100
r
100

5
5
10
0.19
5
0.19
P
A
P
A
P
A
P
A
P
A
mA
mA
mA
0V
d
V
I
or V
O
d
5.5V
V
O
V
I
V
O
V
O
V
CC

V
O
d
5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
www.fairchildsemi.com
4
74LVT162244 • 74LVTH162244
DC Electrical Characteristics
Symbol
I
CCZ

Parameter
Power Supply Current
Increase in Power Supply Current
(Note 8)
Note 5:
Applies to bushold versions only (74LVTH162244).
(Continued)
V
CC
(V)
3.6
3.6
T
A

40
q
C to

85
q
C
Max
0.19
0.2
Units
Conditions
V
CC
d
V
O
d
5.5V,
Outputs Disabled
One Input at V
CC

0.6V
Other Inputs at V
CC
or GND
Min
mA
mA
'
I
CC
Note 6:
An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7:
An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8:
This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
V
CC
(V)
3.3
3.3
(Note 9)
T
A
25
q
C
Typ
0.8
Max
Conditions
Units
V
V
C
L
50 pF, R
L
(Note 10)
(Note 10)
500
:
Min

0.8
Note 9:
Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10:
Max number of outputs defined as (n). n

1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
T
A
Symbol
Parameter
V
CC
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Output to Output Skew
(Note 11)
Output Disable Time
Output Enable Time
Propagation Delay Data to Output
1.4
1.2
1.2
1.4
2.0
1.5

40
q
C to

85
q
C, C
L
3.3V
r
0.3V
Max
4.0
3.7
5.1
5.4
5.0
5.0
1.0
50 pF, R
L
V
CC
Min
1.4
1.2
1.2
1.4
2.0
1.5
500
:
2.7V
Max
4.8
4.1
6.5
6.9
5.4
5.4
1.0
Units
ns
ns
ns
ns
Note 11:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
Symbol
C
IN
C
OUT
(Note 12)
Parameter
Conditions
V
CC
V
CC
0V, V
I
0V or V
CC
0V or V
CC
3.0V, V
O
Typical
4
8
Units
pF
pF
Input Capacitance
Output Capacitance
Note 12:
Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
5
www.fairchildsemi.com

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