August 1986 DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control
Revised February 1999
DM74LS191
Synchronous 4-Bit Up/Down Counter with Mode Control
General Description Two outputs have been made available to perform the cas-
cading function: ripple clock and maximum/minimum count.
The DM74LS191 circuit is a synchronous, reversible, up/ The latter output produces a high-level output pulse with a
down counter. Synchronous operation is provided by hav- duration approximately equal to one complete cycle of the
ing all flip-flops clocked simultaneously, so that the outputs clock when the counter overflows or underflows. The ripple
change simultaneously when so instructed by the steering clock output produces a low-level output pulse equal in
logic. This mode of operation eliminates the output count- width to the low-level portion of the clock input when an
ing spikes normally associated with asynchronous (ripple overflow or underflow condition exists. The counters can be
clock) counters. easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking
The outputs of the four master-slave flip-flops are triggered is used, or to the clock input if parallel enabling is used.
on a LOW-to-HIGH level transition of the clock input, if the The maximum/minimum count output can be used to
enable input is LOW. A HIGH at the enable input inhibits accomplish look-ahead for high-speed operation.
counting. Level changes at either the enable input or the
down/up input should be made only when the clock input is Features
HIGH. The direction of the count is determined by the level
of the down/up input. When LOW, the counter counts up s Counts binary
and when HIGH, it counts down. s Single down/up count control line
s Count enable control input
The counter is fully programmable; that is, the outputs may s Ripple clock output for cascading
be preset to either level by placing a LOW on the load input s Asynchronously presettable with load control
and entering the desired data at the data inputs. The output s Parallel outputs
will change independent of the level of the clock input. This s Cascadable for n-bit applications
feature allows the counters to be used as modulo-N divid- s Average propagation delay 20 ns
ers by simply modifying the count length with the preset s Typical clock frequency 25 MHz
inputs.
s Typical power dissipation 100 mW
The clock, down/up, and load inputs are buffered to lower
the drive requirement; which significantly reduces the num-
ber of clock drivers, etc., required for long parallel words.
Ordering Code:
Order Number Package Number Package Description
DM74LS191M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body
DM74LS191N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
1999 Fairchild Semiconductor Corporation DS006405.prf www.fairchildsemi.com
DM74LS191 Connection Diagram
Timing Diagram
www.fairchildsemi.com 2
Logic Diagram DM74LS191
Pin (16) = VCC, Pin (8) = GND www.fairchildsemi.com
3
DM74LS191 Absolute Maximum Ratings(Note 1)
Storage Temperature Range -65C to +150C Note 1: The "Absolute Maximum Ratings" are those values beyond which
Input Voltage 7V the safety of the device cannot be guaranteed. The device should not be
Operating Free Air Temp. Range operated at these limits. The parametric values defined in the Electrical
Supply Voltage 0C to +70C Characteristics tables are not guaranteed at the absolute maximum ratings.
7V The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol Parameter Min Nom Max Units
5.25 V
VCC Supply Voltage 4.75 5 V
0.8 V
VIH HIGH Level Input Voltage 2 -0.4 mA
mA
VIL LOW Level Input Voltage 8
20 MHz
IOH HIGH Level Output Current ns
70
IOL LOW Level Output Current ns
Max ns
fCLK Clock Frequency (Note 2) 0 ns
-1.5 C
tW Pulse Width Clock 25
0.4 Units
(Note 2) Load 35 0.5
0.4 V
tSU Data Setup Time (Note 2) 20 0.3
0.1 V
tH Data Hold Time (Note 2) 0 60
20 V
tEN Enable Time to Clock (Note 2) 30 -1.08
-0.4 mA
TA Free Air Operating Temperature 0 -100
-100 A
Note 2: TA = 25C and VCC = 5V. 35
mA
DC Electrical Characteristics
mA
Symbol Parameter Conditions Min Typ
(Note 3) mA
VI Input Clamp Voltage VCC = Min, II = - 18 mA
3.4
VOH HIGH Level Output VCC = Min, IOH = Max Mil 2.5 3.4
0.25
Voltage VIL = Max, VIH = Min Com 2.7 0.35
0.25
VOL LOW Level Output VCC = Min, IOL = Max
20
Voltage VIL = Max, VIH = Min
IOL = 4 mA, VCC = Min
II Input Current @ Max VCC = Max Enable
Input Voltage VI = 7V Others
IIH HIGH Level Input VCC = Max Enable
Current VI = 2.7V Others
IIL LOW Level Input VCC = Max Enable
Current VI = 0.4V Others
IOS Short Circuit VCC = Max Mil -20
Output Current (Note 4) Com -20
ICC Supply Current VCC = Max (Note 5)
Note 3: All typicals are at VCC = 5V, TA = 25C.
Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 5: ICC is measured with all inputs grounded and all outputs open.
www.fairchildsemi.com 4
AC Electrical Characteristics DM74LS191
From (Input) RL = 2 k
To (Output)
Symbol Parameter CL = 15 pF CL = 50 pF Units
MHz
Min Max Min Max
ns
fMAX Maximum Clock 20 20 ns
tPLH Frequency ns
tPHL Propagation Delay Time Load to 33 43 ns
tPLH LOW-to-HIGH Level Output Any Q ns
tPHL Propagation Delay Time Load to 50 59 ns
tPLH HIGH-to-LOW Level Output Any Q ns
tPHL Propagation Delay Time Data to 22 26 ns
tPLH LOW-to-HIGH Level Output Any Q ns
tPHL Propagation Delay Time Data to 50 62 ns
tPLH HIGH-to-LOW Level Output Any Q ns
tPHL Propagation Delay Time Clock to 20 24 ns
tPLH LOW-to-HIGH Level Output Ripple Clock ns
tPHL Propagation Delay Time Clock to 24 33 ns
tPLH HIGH-to-LOW Level Output Ripple Clock ns
tPHL Propagation Delay Time Clock to 24 29 ns
tPLH LOW-to-HIGH Level Output Any Q
tPHL Propagation Delay Time Clock to 36 45
HIGH-to-LOW Level Output Any Q
Propagation Delay Time Clock to 42 47
LOW-to-HIGH Level Output Max/Min
Propagation Delay Time Clock to 52 65
HIGH-to-LOW Level Output Max/Min
Propagation Delay Time Up/Down to 45 50
LOW-to-HIGH Level Output Ripple Clock
Propagation Delay Time Up/Down to 45 54
HIGH-to-LOW Level Output Ripple Clock
Propagation Delay Time Down/Up to 33 36
LOW-to-HIGH Level Output Max/Min
Propagation Delay Time Down/Up to 33 42
HIGH-to-LOW Level Output Max/Min
Propagation Delay Time Enable to 33 36
LOW-to-HIGH Level Output Ripple Clock
Propagation Delay Time Enable to 33 42
HIGH-to-LOW Level Output Ripple Clock
5 www.fairchildsemi.com
DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS012, 0.150" Narrow Body
Package Number M16A
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 300" Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support
which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea-
body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support
to perform when properly used in accordance with device or system, or to affect its safety or effectiveness.
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the www.fairchildsemi.com
user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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采用光纤或双绞线接口、符合 EMI/EMC 标准的 10/100Mbps 以太网砖型模块参考设计
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