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器件描述：SPECIAL ENVIRONMENT 80960CF-30, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR
器件厂商：INTEL [Intel Corporation]
厂商主页：http://www.intel.com/
文件大小：1177.31KB
文件页数：62
PDF阅读：80960CF-30.pdf (点击阅读器件资料)
摘要：
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
January 1995COPYRIGHT ' INTEL CORPORATION, 1995 Order Number: 271328-001
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
PROCESSOR
# Socket and Object Code Compatible with 80960CA
# Two Instructions/Clock Sustained Execution
# Four 59 Mbytes/s DMA Channels with Data Chaining
# Demultiplexed 32-bit Burst Bus with Pipelining
Y
32-bit Parallel Architecture
— Two Instructions/clock Execution
— Load/Store Architecture
— Sixteen 32-bit Global Registers
— Sixteen 32-bit Local Registers
— Manipulate 64-bit Bit Fields
— 11 Addressing Modes
— Full Parallel Fault Model
— Supervisor Protection Model
Y
Fast Procedure Call/Return Model
— Full Procedure Call in 4 clocks
Y
On-Chip Register Cache
— Caches Registers on Call/Ret
— Minimum of 6 Frames provided
— Up to 15 Programmable Frames
Y
On-Chip Instruction Cache
— 4 Kbyte Two-Way Set Associative
— 128-bit Path to Instruction Sequencer
— Cache-Lock Modes
— Cache-Off Mode
Y
On-Chip Data Cache
— 1 Kbyte Direct-Mapped,
Write Through
— 128 bits per Clock Access on
Cache Hit
Y
Product Grades Available
— SE3:
b
40§Cto
a
110§C
Y
High Bandwidth On-Chip Data RAM
— 1 Kbytes On-Chip RAM for Data
— Sustain 128 bits per clock access
Y
Four On-Chip DMA Channels
— 59 Mbytes/s Fly-by Transfers
— 32 Mbytes/s Two-Cycle Transfers
— Data Chaining
— Data Packing/Unpacking
— Programmable Priority Method
Y
32-Bit Demultiplexed Burst Bus
— 128-bit Internal Data Paths to and
from Registers
— Burst Bus for DRAM Interfacing
— Address Pipelining Option
— Fully Programmable Wait States
— Supports 8, 16 or 32-bit Bus Widths
— Supports Unaligned Accesses
— Supervisor Protection Pin
Y
Selectable Big or Little Endian Byte
Ordering
Y
High-Speed Interrupt Controller
— Up to 248 External Interrupts
— 32 Fully Programmable Priorities
— Multi-mode 8-bit Interrupt Port
— Four Internal DMA Interrupts
— Separate, Non-maskable Interrupt Pin
— Context Switch in 750 ns Typical
相关器件：80960CF-16 80960CF-25
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