EEWorld咨询电话：82357002，82350740－8068 邮件咨询：datasheet@eeworld.com.cn
器件描述：80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR
器件厂商：INTEL [Intel Corporation]
厂商主页：http://www.intel.com/
文件大小：1315.84KB
文件页数：77
PDF阅读：80960CF-16.pdf (点击阅读器件资料)
摘要：
? INTEL CORPORATION, 1996 June 1996 Order Number: 272886-001
A PRELIMINARY
80960CF-40, -33, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
EMBEDDED MICROPROCESSOR
? Socket and Object Code Compatible with 80960CA
? Two Instructions/Clock Sustained Execution
? Four 71 Mbytes/s DMA Channels with Data Chaining
? Demultiplexed 32-Bit Burst Bus with Pipelining
a73 32-Bit Parallel Architecture
— Two Instructions/clock Execution
— Load/Store Architecture
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers
— Manipulates 64-Bit Bit Fields
— 11 Addressing Modes
— Full Parallel Fault Model
— Supervisor Protection Model
a73 Fast Procedure Call/Return Model
— Full Procedure Call in 4 Clocks
a73 On-Chip Register Cache
— Caches Registers on Call/Ret
— Minimum of 6 Frames Provided
— Up to 15 Programmable Frames
a73 On-Chip Instruction Cache
— 4 Kbyte Two-Way Set Associative
— 128-Bit Path to Instruction Sequencer
— Cache-Lock Modes
— Cache-Off Mode
a73 High Bandwidth On-Chip Data RAM
— 1 Kbyte On-Chip Data RAM
— Sustains 128 bits per Clock Access
a73 Selectable Big or Little Endian Byte
Ordering
a73 Four On-Chip DMA Channels
— 71 Mbytes/s Fly-by Transfers
— 40 Mbytes/s Two-Cycle Transfers
— Data Chaining
— Data Packing/Unpacking
— Programmable Priority Method
a73 32-Bit Demultiplexed Burst Bus
— 128-Bit Internal Data Paths to and from
Registers
— Burst Bus for DRAM Interfacing
— Address Pipelining Option
— Fully Programmable Wait States
— Supports 8-, 16- or 32-Bit Bus Widths
— Supports Unaligned Accesses
— Supervisor Protection Pin
a73 High-Speed Interrupt Controller
— Up to 248 External Interrupts
— 32 Fully Programmable Priorities
— Multi-mode 8-Bit Interrupt Port
— Four Internal DMA Interrupts
— Separate, Non-maskable Interrupt Pin
— Context Switch in 625 ns Typical
a73 On-Chip Data Cache
— 1 Kbyte Direct-Mapped, Write Through
— 128 bits per Clock Access on Cache Hit
相关器件：80960CF-40 80960CF-25 80960CF-33
|
