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器件描述：Octal D-Type Flip-Flop with Clock Enable
器件厂商：NSC [National Semiconductor]
厂商主页：http://www.national.com
文件大小：151.86KB
文件页数：8
PDF阅读：54ABT377E-QML.pdf (点击阅读器件资料)
摘要：
54ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ’ABT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
n Clock enable for address and data synchronization
applications
n Eight edge-triggered D flip-flops
n Buffered common clock
n See ’ABT273 for master reset version
n See ’ABT373 for transparent latch version
n See ’ABT374 for TRI-STATE
?
version
n Output sink capability of 48 mA, source capability of
24 mA
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Disable time less than enable time to avoid bus
contention
n Standard Microcircuit Drawing (SMD) 5962-9314801
Ordering Code:
Military Package Package Description
Number
54ABT377J-QML J20A 20-Lead Ceramic Dual-In-Line
54ABT377W-QML W20A 20-Lead Cerpack
54ABT377E-QML E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagram
Pin
Names
Description
D
0
–D
7
Data Inputs
CE Clock Enable (Active LOW)
CP Clock Pulse Input
Q
0
–Q
7
Data Outputs
TRI-STATE
?
is a registered trademark of National Semiconductor Corporation.
Pin Assignment for
DIP and Cerpack
DS100216-1
Pin Assignment for LCC
DS100216-11
July 1998
54ABT377
Octal
D-T
ype
Flip-Flop
with
Clock
Enable
? 1998 National Semiconductor Corporation DS100216 www.national.com
相关器件：54ABT377W-QML 54ABT377J-QML 54ABT377
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