IS24C128 ISSI
131,072-bit 2-WIRE SERIAL PRELIMINARY INFORMATION
CMOS EEPROM MARCH 2003
FEATURES DESCRIPTION
Organization:
The IS24C128 is an electrically erasable PROM
16K-bit x 8-bit device that uses the standard 2-wire interface for
64-Byte Page Write Buffer communications. The IS24C128 contains a memory
Two-Wire Serial Interface array of 128K-bits (16,384 x 8), and is further
subdivided into 256 pages of 64 bytes each for page-
Bi-directional data transfer protocol write mode. This EEPROM is offered in wide operating
Low Power CMOS Technology voltages of 1.8V to 5.5V (IS24C128-2) and 2.5V to 5.5V
(IS24C128-3) to be compatible with most application
Active Current less than 2 mA (5V) voltages. ISSI designed the IS24C128 to be a low-cost
Standby Current less than 5 A (5V) and low-power 2-wire EEPROM solution. The devices
Standby Current less than 2 A (2.5V) are packaged in 8-pin PDIP, 8-pin SOIC, and 14-pin
Low Voltage Operation TSSOP.
IS24C128-2: Vcc = 1.8V to 5.5V
IS24C128-3: Vcc = 2.5V to 5.5V The IS24C128 maintains compatibility with the popular
400 KHz (I2C Protocol) Compatibility 2-wire bus protocol, so it is easy to design into
Hardware Data Protection applications implementing this bus type. The simple
Write Protect pin bus consists of the Serial Clock wire (SCL) and the
Sequential Read Feature Serial Data wire (SDA). Using the bus, a Master
Filtered Inputs for Noise Suppression device such as a microcontroller is usually connected
Self time Write cycle with auto clear to one or more Slave devices such as the IS24C128.
5 ms @ 2.5V The bit stream over the SDA line includes a series of
High Reliability bytes, which identifies a particular Slave device, an
Endurance: 100,000 Cycles instruction, an address within that Slave device, and a
Data Retention: 40 Years series of data, if appropriate. The IS24C128 has a
Commercial and Industrial temperature ranges Write Protect pin (WP) to allow blocking of any write
8-pin PDIP, 8-pin SOIC, and 14-pin TSSOP instruction transmitted over the bus.
Copyright 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI
assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device
specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 1
PRELIMINARYINFORMATION Rev.00B
03/11/03
IS24C128 ISSI
FUNCTIONAL BLOCK DIAGRAM
Vcc HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
SDA CONTROL X
SCL LOGIC DECODER
WP
SLAVE ADDRESS EEPROM
A0 REGISTER & ARRAY
A1 COMPARATOR
NC
WORD ADDRESS Y
COUNTER DECODER
GND ACK Clock > DATA
DI/O
REGISTER
nMOS
2 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00B
03/11/03
IS24C128 ISSI
PIN CONFIGURATION 14-pin TSSOP
8-Pin DIP and SOIC
A0 1 14 VCC
A0 1 8 VCC A1 2 13 WP
A1 2 7 WP
NC 3 6 SCL NC 3 12 NC
GND 4 5 SDA
NC 4 11 NC
NC 5 10 NC
NC 6 9 SCL
GND 7 8 SDA
PIN DESCRIPTIONS
A0-A1 Address Inputs drain output and can be wire Or'ed with other open drain
SDA Serial Address/Data I/O or open collector outputs. The SDA bus requires a pullup
SCL Serial Clock Input resistor to Vcc.
WP Write Protect Input
Vcc Power Supply A0, A1
NC No Connect
GND Ground The A0, and A1 are the device address inputs that are
hardwired or left not connected for hardware compatibility
SCL with the 24C32/64. When pins are hardwired, as many as
four 128K devices may be addressed on a single bus
This input clock pin is used to synchronize the data system. When the pins are not hardwired, the default A0
transfer to and from the device. and A1 are zero.
SDA WP
The SDA is a Bi-directional pin used to transfer addresses WP is the Write Protect pin. If the WP pin is tied to Vcc
and data into and out of the device. The SDA pin is an open the entire array becomes Write Protected (Read only).
When WP is tied to GND or left floating, normal read/write
operations are allowed to the device.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 3
PRELIMINARYINFORMATION Rev.00A
03/11/03
IS24C128 ISSI
DEVICE OPERATION Standby Mode
The IS24C128 features a serial communication and Power consumption in reduced in standby mode. The
supports a bi-directional 2-wire bus transmission protocol. IS24C128 will enter standby mode: a) At Power-up, and
remain in it until SCL or SDA toggles; b) Following the Stop
2-WIRE BUS signal if no write operation is initiated; or c) Following any
internal write operation
The two-wire bus is defined as a Serial Data line (SDA),
and a Serial Clock line (SCL). The protocol defines any DEVICE ADDRESSING
device that sends data onto the SDA bus as a transmitter,
and the receiving devices as a receiver. The bus is The Master begins a transmission by sending a Start
controlled by Master device which generates the SCL, condition. The Master then sends the address of the
controls the bus access and generates the Stop and Start particular Slave devices it is requesting. The Slave
conditions. The IS24C128 is the Slave device on the bus. (Fig. 5) address is 8 bits.
The Bus Protocol: The four most significant bits of the address are fixed as
1010 for the IS24C128.
Data transfer may be initiated only when the bus is not
busy This device has two address bits (A1 and A0), which
allows up to four IS24C128 devices to share the 2-wire
During a data transfer, the data line must remain stable bus. Upon receiving the Slave address, the device
whenever the clock line is high. Any changes in the compares the two address bits with the hardwired A1
data line while the clock line is high will be interpreted and A0 input pins to determine if it is the appropriate
as a Start or Stop condition. Slave. If the A1 and A0 pins are not biased to High nor
Low, then internal circuitry defaults the value to Low.
The state of the data line represents valid data after a Start
condition. The data line must be stable for the duration of The last bit of the Slave address specifies whether a Read
the High period of the clock signal. The data on the SDA or Write operation is to be performed. When this bit is set
line may be changed during the Low period of the clock to 1, a Read operation is selected, and when set to 0, a
signal. There is one clock pulse per bit of data. Each data Write operation is selected.
transfer is initiated with a Start condition and terminated
with a Stop condition. After the Master transmits the Start condition and
Slave address byte (Fig. 5), the appropriate 2-wire
Start Condition Slave (eg. IS24C128) will respond with ACK on the
SDA line. The Slave will pull down the SDA on the
The Start condition precedes all commands to the device ninth clock cycle, signaling that it received the eight
and is defined as a High to Low transition of SDA when bits of data. The selected IS24C128 then prepares for a
SCL is High. The IS24C128 monitors the SDA and SCL Read or Write operation by monitoring the bus.
lines and will not respond until the Start condition is met.
WRITE OPERATION
Stop Condition
Byte Write
The Stop condition is defined as a Low to High transition
of SDA when SCL is High. All operations must end with In the Byte Write mode, the Master device sends the Start
a Stop condition. condition and the Slave address information (with the R/
W set to Zero) to the Slave device. After the Slave
Acknowledge (ACK) generates an ACK, the Master sends two byte addresses
that are to be written into the address pointer of the
After a successful data transfer, each receiving device is IS24C128. After receiving another ACK from the Slave,
required to generate an ACK. The Acknowledging device the Master device transmits the data byte to be written into
pulls down the SDA line. the address memory location. The IS24C128
acknowledges once more and the Master generates the
Reset Stop condition, at which time the device begins its internal
programming cycle. While this internal cycle is in progress,
The IS24C128 contains a reset function in case the 2- the device will not respond to any request from the Master
wire bus transmission is accidentally interrupted (eg. a device.
power loss), or needs to be terminated mid-stream.
The reset is caused when the Master device creates a
Start condition. To do this, it may be necessary for the
Master device to monitor the SDA line while cycling the
SCL up to nine times. (For each clock signal transition
to High, the Master checks for a High level on SDA.)
4 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00B
03/11/03
IS24C128 ISSI
Page Write Random Address Read
The IS24C128 is capable of 64-byte Page-Write operation. A Selective Read operations allow the Master device to
Page-Write is initiated in the same manner as a Byte Write, select at random any memory location for a Read
but instead of terminating the internal Write cycle after the operation. The Master device first performs a 'dummy'
first data word is transferred, the Master device can transmit Write operation by sending the Start condition, Slave
up to 63 more bytes. After the receipt of each data word, the address and word address of the location it wishes to
IS24C128 responds immediately with an ACK on SDA line, read. After the IS24C128 acknowledges the word address,
and the six lower order data word address bits are internally the Master device resends the Start condition and the
incremented by one, while the higher order bits of the data Slave address, this time with the R/W bit set to one. The
word address remain constant. If the Master device should IS24C128 then responds with its ACK and sends the data
transmit more than 64 words, prior to issuing the Stop requested. The Master device does not send an ACK but
condition, the address counter will "roll over," and the previously will generate a Stop condition. (Refer to Figure 9. Random
written data will be overwritten. Once all 64 bytes are Address Read Diagram.)
received and the Stop condition has been sent by the Master,
the internal programming cycle begins. At this point, all Sequential Read
received data is written to the IS24C128 in a single Write
cycle. All inputs are disabled until completion of the internal Sequential Reads can be initiated as either a Current
Write cycle. Address Read or Random Address Read. After the
IS24C128 sends initial byte sequence, the Master device
Acknowledge (ACK) Polling now responds with an ACK indicating it requires additional
data from the IS24C128. The IS24C128 continues to
The disabling of the inputs can be used to take advantage output data for each ACK received. The Master device
of the typical Write cycle time. Once the Stop condition terminates the sequential Read operation by pulling SDA
is issued to indicate the end of the host's Write operation, High (no ACK) indicating the last data word to be read,
the IS24C128 initiates the internal Write cycle. ACK followed by a Stop condition.
polling can be initiated immediately. This involves issuing
the Start condition followed by the Slave address for a The data output is sequential, with the data from address
Write operation. If the IS24C128 is still busy with the Write n followed by the data from address n+1, ... etc. The
operation, no ACK will be returned. If the IS24C128 has address counter increments by one automatically, allowing
completed the Write operation, an ACK will be returned the entire memory contents to be serially read during
and the host can then proceed with the next Read or Write sequential Read operation. When the memory address
operation. boundary 16383 is reached, the address counter "rolls
over" to address 0, and the IS24C128 continues to output
READ OPERATION data for each ACK received. (Refer to Figure 10. Sequential
Read Operation Starting with a Random Address Read
Read operations are initiated in the same manner as Write Diagram.)
operations, except that the (R/W) bit of the Slave address
is set to "1". There are three Read operation options:
current address read, random address read and sequential
read.
Current Address Read
The IS24C128 contains an internal address counter which
maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation
is either a Read or Write operation addressed to the
address location n, the internal address counter would
increment to address location n+1. When the IS24C128
receives the Device Addressing Byte with a Read operation
(R/W bit set to "1"), it will respond an ACK and transmit the
8-bit data word stored at address location n+1. The
Master should not acknowledge the transfer but should
generate a Stop condition so the IS24C128 discontinues
transmission. If 'n' is the last byte of the memory, then the
data from location '0' will be transmitted. (Refer to
Figure 8. Current Address Read Diagram.)
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 5
PRELIMINARYINFORMATION Rev.00A
03/11/03
IS24C128 ISSI
Figure 1. Typical System Bus Configuration
Vcc
SDA
SCL
Master IS24C128
Transmitter/
Receiver
Figure 2. Output Acknowledge
SCL from 1 8 9
Master
Data Output tAA tAA
from
ACK
Transmitter
Data Output
from
Receiver
Figure 3. Start and Stop ConditionsSTART STOP
Condition Condition
SCL
SDA
6 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00B
03/11/03
IS24C128 ISSI
Figure 4. Data Validity Protocol
Data Change
SCL Data Stable Data Stable
SDA
Figure 5. Slave Address
BIT 7 6 5 4 3 2 1 0
1 0 1 0 0 A1 A0 R/W
Figure 6. Byte Write
S W S
T R
A I T
R Device T O
T Address E Word Address Word Address Data P
SDA A A A A
Bus C** C C C
Activity K K K K
M L M
S S
B B S * = Don't care bits
R/W B
Figure 7. Page Write
S W S
T R T
A I O
R Device T Data (n) Data (n+1) Data (n+63) P
SDA T Address E Word Address (n) Word Address (n) A A
C C
Bus A A A A K K
Activity
C** C C C
K K K K
M L
S S
B B * = Don't care bits
R/W
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 7
PRELIMINARYINFORMATION Rev.00A
03/11/03
IS24C128 ISSI
Figure 8. Current Address Read
S
T R S
A E T
R Device A O
T Address D Data P
SDA A
Bus C
Activity K
M L N
O
S S
B B A
R/W C
K
Figure 9. Random Address Read
S W S
T R T R S
A Device I Word Word A Device E Data n T
R Address T Address (n) Address (n) R Address A O
T E T D P
SDA A A A A
Bus C* * C C C
Activity
K K K K
M L N
O
S S
B B * = Don't care bits A
R/W C
K
DUMMY WRITE
Figure 10. Sequential Read
R Data Byte n Data Byte n+1 Data Byte n+2 S
E T
SDA Device A A A A O
Bus Address D Data Byte n+X P
Activity C C C
A N
C K K K O
K A
C
R/W K
8 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00B
03/11/03
IS24C128 ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VS Supply Voltage
VP Voltage on Any Pin +0.5 to +6.25 V
TBIAS Temperature Under Bias
TSTG Storage Temperature 0.5 to Vcc +0.5 V
IOUT Output Current
40 to +85 C
65 to +150 C
5 mA
Notes:
1. Stresses violating the conditions listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only. Functional operation of the
device outside these conditions or those indicated in the operational sections of this
specification is not implied. Exposure to these conditions for extended periods may affect
reliability.
OPERATING RANGE (IS24C128-2)
Range Ambient Temperature VCC
Commercial 0C to +70C 1.8V to 5.5V
Industrial 1.8V to 5.5V
40C to +85C
OPERATING RANGE (IS24C128-3)
Range Ambient Temperature VCC
Commercial 0C to +70C 2.5V to 5.5V
Industrial 2.5V to 5.5V
40C to +85C
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 5.0V.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 9
PRELIMINARYINFORMATION Rev.00A
03/11/03
IS24C128 ISSI
DC ELECTRICAL CHARACTERISTICS
Commercial (TA = 0OC to +70OC) Industrial (TA = -40OC to +85OC)
Symbol Parameter Test Conditions Min. Max. Unit
V
VOL1 Output Low Voltage VCC = 1.8V, IOL = 0.15 mA -- 0.2 V
V
VOL2 Output Low Voltage VCC = 2.5V, IOL = 1.0 mA -- 0.4 V
A
VIH Input High Voltage VCC X 0.7 VCC + 0.5 A
VIL Input Low Voltage 1.0 VCC X 0.3
ILI Input Leakage Current VIN = VCC max. -- 3
ILO Output Leakage Current -- 3
Notes: VIL min and VIH max are reference only and are not tested.
POWER SUPPLY CHARACTERISTICS
Commercial (TA = 0OC to +70OC) Industrial (TA = -40OC to +85OC)
Symbol Parameter Test Conditions Min. Max. Unit
Read at 100 KHz (Vcc = 5V)
ICC1 Vcc Operating Current Write at 100 KHz (Vcc = 5V) -- 2.0 mA
Vcc = 1.8V, Vcc = 2.5V
ICC2 Vcc Operating Current Vcc = 5.0V -- 3.0 mA
ISB1 Standby Current -- 2 A
ISB2 Standby Current -- 5 A
AC ELECTRICAL CHARACTERISTICS
Commercial (TA = 0OC to +70OC) Industrial (TA = -40OC to +85OC)
Symbol Parameter 1.8V 2.5V 5.0V(1,2) Unit
Min. Max. Min. Max. Min. Max. KHz
fSCL SCL Clock Frequency ns
0 100 0 400 0 1000 s
T Noise Suppression Time(1) -- 100 -- 50 -- 50 s
4.7 -- 1.3 -- 0.6 -- s
tLow Clock Low Period 4-- 0.6 -- 0.4 -- s
4.7 -- 1.2 -- 0.5 -- s
tHigh Clock High Period 4.7 -- 0.6 -- 0.25 -- s
4.7 -- 0.6 -- 0.25 -- s
tBUF Bus Free Time Before New Transmission(1) 4-- 0.6 -- 0.25 -- ns
4-- 0.6 -- 0.6 -- ns
tSU:STA Start Condition Setup Time 200 -- 100 -- 100 -- s
0-- 0-- 0-- s
tSU:STO Stop Condition Setup Time 4-- 0.6 -- 0.6 -- ns
4.7 -- 1.3 -- 1.3 -- ns
tHD:STA Start Condition Hold Time 200 -- 200 -- 200 -- ns
200 3500 200 900 200 550 ns
tHD:STO Stop Condition Hold Time -- 1000 -- 300 -- 300 ms
-- 300 -- 300 -- 300
tSU:DAT Data In Setup Time -- 10 --5 --5
tHD:DAT Data In Hold Time
tSU:WP WP pin Setup Time
tHD:WP WP pin Hold Time
tDH Data Out Hold Time (SCL Low to SDA Data Out Change)
tAA Clock to Output (SCL Low to SDA Data Out Valid)
tR SCL and SDA Rise Time(1)
tF SCL and SDA Fall Time(1)
tWR Write Cycle Time
Note:
1. This parameter is characterized but not 100% tested.
2. Preliminary only.
10 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00B
03/11/03
IS24C128 ISSI
AC WAVEFORMS
Figure 11. Bus Timing
tR tF tHIGH tLOW tSU:STO
tBUF
SCL tSU:STA tHD:DAT
SDAIN tHD:STA
SDAOUT tSU:DAT
tAA tDH
tSU:WP tHD:WP
WP
Figure 12. Write Cycle Timing
SCL
SDA 8th BIT ACK
WORD n tWR
STOP START
Condition Condition
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 11
PRELIMINARYINFORMATION Rev.00A
03/11/03
IS24C128 ISSI
ORDERING INFORMATION Package
Commercial Range: 0C to +70C 300-mil Plastic DIP (8-pin)
Small Outline (JEDEC STD) (8-pin)
Frequency Voltage Part Number TSSOP (14-pin)
400 KHz Range
IS24C128-3P Package
2.5V IS24C128-3G 300-mil Plastic DIP (8-pin)
to 5.5V IS24C128-3Z Small Outline (JEDEC STD) (8-pin)
TSSOP (14-pin)
Industrial Range: 40C to +85C
Frequency Voltage Part Number
400 KHz Range
IS24C128-3PI
2.5V IS24C128-3GI
to 5.5V IS24C128-3ZI
ISSI
Integrated Silicon Solution, Inc. Tel: 1-800-379-4774
Fax: (408) 588-0806
2231 Lawson Lane E-mail: sales@issi.com
Santa Clara, CA 95054
www.issi.com
12 Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARYINFORMATION Rev. 00B
03/11/03
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