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器件描述：GENLINX-TM II EB9021 Evaluation Board
器件厂商：GENNUM [Gennum Corporation]
厂商主页：http://www.gennum.com
文件大小：413.76KB
文件页数：8
PDF阅读：EB9021.pdf (点击阅读器件资料)
摘要：
PRELIMINARY
GENLINX
?
II
EB9021 Evaluation Board
EB9021 BLOCK DIAGRAM
Document No. VB2934 - 1
I
2
C INTERFACE
CONFIGURATION JUMPERS
ECL
TO
TTL
TTL
TO
ECL
GS9021
EDH
COPROCESSOR
PLD
EDH & FVH LEDs
DB25F
DB25F
PARALLEL
DATA
IN
PARALLEL
DATA
OUT
I
2
C is a registered Trademark of Philips
A PLD is provided primarily to interface to the Flag Port of the
GS9021 and extract the Ancillary, Full Field, and Active
Picture error flags. The PLD is designed to cycle the S[1:0]
inputs of the GS9021, read and demultiplex the output error
flags, and drive the EDH LEDs providing visual indication of
the type of EDH errors present. The PLD is also designed to
control which error flags are read from the GS9021 Flag Port
— incoming or outgoing. Upon power-up or RESET, the
board is configured to display the outgoing EDH error flags.
When the INC. FLAGS push-button is depressed, the PLD
writes to the GS9021 flag port instructing it to output the
incoming EDH error flags instead. To return to the outgoing
error flags, the system must be RESET. Finally, the PLD is
used to buffer the GS9021 field, vertical, and horizontal
output signals and drive the respective LEDs.
A DB9F connector is provided for access to the I
2
C interface
of the GS9021. I
2
C slave address bits are set via configuration
jumpers. For a detailed description of the GS9021 I
2
C
interface refer to the GS9021 data sheet.
1
INTRODUCTION
The EB9021 is an evaluation and reference design platform
for the GENLINX
?
II GS9021 EDH Coprocessor. The
EB9021 is a parallel ECL input, parallel ECL output board
that fully supports Error Detection and Handling (EDH)
according to SMPTE RP165. The board operates to 54MHz
and supports the following standards:
- 4:2:2 Component with 13.5 MHz Y sampling (NTSC & PAL)
- 4:2:2 Component with 18.0 MHz Y sampling (NTSC & PAL)
- 4fsc Composite (NTSC & PAL)
- 4:4:4:4 Component Single Link with 13.5 MHz Y sampling
(NTSC & PAL)
CIRCUIT DESCRIPTION
A block diagram of the board is shown below and illustrates
the primary circuit functions. A full schematic is also included.
Bit parallel data is connected to the board through a DB25F
connector with a pin configuration in accordance with SMPTE
125 and SMPTE 244M. Three 10125 ECL to TTL converter
ICs are used to shift the logic levels of the bit parallel data to
directly interface with the GS9021 EDH Coprocessor. The
resulting CMOS (TTL compatible) outputs of the GS9021 are
supplied to three 10124 TTL to ECL converter ICs. These
ECL outputs are then available at the output DB25F connector.
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