ATtiny416/417/814/816/817
Automotive
tinyAVR
®
1-series
Introduction
The ATtiny416/417/814/816/817 Automotive are members of the tinyAVR
®
1-series of microcontrollers,
using the AVR
®
processor with hardware multiplier, running at up to 16 MHz, with 4/8 KB Flash, 256/512
bytes of SRAM, and 128 bytes of EEPROM in a 14-, 20- or 24-pin package. The tinyAVR
®
1-series uses
the latest technologies with a flexible, low-power architecture including Event System and SleepWalking,
accurate analog features, and Core Independent Peripherals. Capacitive touch interfaces with driven
shield are supported with the integrated QTouch
®
peripheral touch controller.
(1)
Features
• CPU
– AVR
®
CPU
– Running at up to 16 MHz
– Single-cycle I/O access
– Two-level interrupt controller
– Two-cycle hardware multiplier
• Memories
– 4/8 KB In-system self-programmable Flash memory
– 128B EEPROM
– 256/512B SRAM
– Write/erase endurance:
• Flash: 10,000 cycles
• EEPROM: 100,000 cycles
– Data retention: 40 years at 55°C
• System
– Power-on Reset (POR)
– Brown-out Detector (BOD)
– Clock options:
• 16 MHz low-power internal RC oscillator
• 32.768 kHz Ultra Low-Power (ULP) internal RC oscillator
• 32.768 kHz external crystal oscillator
• External clock input
– Single-pin Unified Program and Debug Interface (UPDI)
– Three sleep modes:
• Idle with all peripherals running for immediate wake-up
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• Standby
– Configurable operation of selected peripherals
– SleepWalking peripherals
• Power-Down with full data retention
• Peripherals
– One 16-bit Timer/Counter Type A (TCA) with a dedicated period register and three compare
channels
– One 16-bit Timer/Counter Type B (TCB) with input capture
– One 12-bit Timer/Counter Type D (TCD) optimized for control applications
– One 16-bit Real-Time Counter (RTC) running from external crystal or internal RC oscillator
– Watchdog Timer (WDT) with Window mode, with a separate on-chip oscillator
– One USART with fractional baud rate generator, auto-baud, and start-of-frame detection
– One master/slave Serial Peripheral Interface (SPI)
– One Two-Wire Interface (TWI) with dual address match
• Philips I
2
C compatible
• Standard mode (Sm, 100 kHz)
• Fast mode (Fm, 400 kHz)
• Fast mode plus (Fm+, 1 MHz)
– One Analog Comparator (AC) with a low propagation delay
– One 10-bit 115 ksps Analog-to-Digital Converter (ADC)
– One 8-bit Digital-to-Analog Converter (DAC)
– Multiple voltage references (VREF):
• 0.55V
• 1.1V
• 1.5V
• 2.5V
• 4.3V
– Event System (EVSYS) for CPU independent and predictable inter-peripheral signaling
– Configurable Custom Logic (CCL) with two programmable look-up tables
– Automated CRC memory scan (CRCSCAN)
– Peripheral Touch Controller (PTC)
(1)
• Capacitive touch buttons, sliders, wheels and 2D surfaces
• Wake-up on touch
• Driven shield for improved moisture and noise handling performance
• Up to six self capacitance channels
• Up to nine mutual capacitance channels
– External interrupt on all general purpose pins
• I/O and Packages:
– 12/18/22 programmable I/O lines
– 14-pin SOIC150
– 20-pin VQFN 3x3 mm with wettable flanks
– 20-pin SOIC300
– 24-pin VQFN 4x4 mm with wettable flanks
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Complete Datasheet
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ATtiny416/417/814/816/817 Automotiv...
• Temperature Ranges:
– -40°C to 105°C
– -40°C to 125°C
• Speed Grades:
– 0-8 MHz @ 2.7V – 5.5V
– 0-16 MHz @ 4.5V – 5.5V
Note:
1. Only available in devices with 8 KB Flash.
©
2019 Microchip Technology Inc.
Complete Datasheet
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ATtiny416/417/814/816/817 Automotiv...
Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Silicon Errata and Data Sheet Clarification Document............................................ 11
2. tinyAVR
®
1-series Overview.................................................................................... 12
2.1.
Configuration Summary..............................................................................................................12
3. Block Diagram......................................................................................................... 14
4. Pinout...................................................................................................................... 17
4.1.
4.2.
4.3.
4.4.
14-Pin SOIC............................................................................................................................... 17
20-Pin SOIC............................................................................................................................... 18
20-Pin VQFN.............................................................................................................................. 19
24-Pin VQFN.............................................................................................................................. 20
5. I/O Multiplexing and Considerations........................................................................21
5.1.
Multiplexed Signals.................................................................................................................... 21
6. Automotive Quality Grade....................................................................................... 22
7. Memories.................................................................................................................23
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
Overview.................................................................................................................................... 23
Memory Map.............................................................................................................................. 24
In-System Reprogrammable Flash Program Memory................................................................24
SRAM Data Memory.................................................................................................................. 25
EEPROM Data Memory............................................................................................................. 25
User Row....................................................................................................................................26
Signature Bytes.......................................................................................................................... 26
Memory Section Access from CPU and UPDI on Locked Device..............................................26
I/O Memory.................................................................................................................................28
Configuration and User Fuses (FUSE).......................................................................................30
8. Peripherals and Architecture................................................................................... 46
8.1.
8.2.
8.3.
Peripheral Module Address Map................................................................................................ 46
Interrupt Vector Mapping............................................................................................................ 47
System Configuration (SYSCFG)...............................................................................................49
9. AVR CPU................................................................................................................. 52
9.1.
9.2.
9.3.
9.4.
9.5.
9.6.
Features..................................................................................................................................... 52
Overview.................................................................................................................................... 52
Architecture................................................................................................................................ 52
Arithmetic Logic Unit (ALU)........................................................................................................ 54
Functional Description................................................................................................................55
Register Summary - CPU...........................................................................................................60
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9.7.
Register Description................................................................................................................... 60
10. Nonvolatile Memory Controller (NVMCTRL)........................................................... 64
10.1.
10.2.
10.3.
10.4.
10.5.
Features..................................................................................................................................... 64
Overview.................................................................................................................................... 64
Functional Description................................................................................................................65
Register Summary - NVMCTRL................................................................................................. 72
Register Description................................................................................................................... 72
11. Clock Controller (CLKCTRL)................................................................................... 80
11.1.
11.2.
11.3.
11.4.
11.5.
Features..................................................................................................................................... 80
Overview.................................................................................................................................... 80
Functional Description................................................................................................................82
Register Summary - CLKCTRL.................................................................................................. 87
Register Description................................................................................................................... 87
12. Sleep Controller (SLPCTRL)................................................................................... 97
12.1.
12.2.
12.3.
12.4.
12.5.
Features..................................................................................................................................... 97
Overview.................................................................................................................................... 97
Functional Description................................................................................................................98
Register Summary - SLPCTRL................................................................................................ 101
Register Description................................................................................................................. 101
13. Reset Controller (RSTCTRL).................................................................................103
13.1.
13.2.
13.3.
13.4.
13.5.
Features................................................................................................................................... 103
Overview.................................................................................................................................. 103
Functional Description..............................................................................................................104
Register Summary - RSTCTRL................................................................................................107
Register Description................................................................................................................. 107
14. CPU Interrupt Controller (CPUINT)....................................................................... 110
14.1.
14.2.
14.3.
14.4.
14.5.
Features................................................................................................................................... 110
Overview...................................................................................................................................110
Functional Description.............................................................................................................. 112
Register Summary - CPUINT................................................................................................... 119
Register Description................................................................................................................. 119
15. Event System (EVSYS)......................................................................................... 124
15.1.
15.2.
15.3.
15.4.
15.5.
Features................................................................................................................................... 124
Overview.................................................................................................................................. 124
Functional Description..............................................................................................................127
Register Summary - EVSYS.................................................................................................... 129
Register Description................................................................................................................. 129
16. Port Multiplexer (PORTMUX)................................................................................ 137
16.1. Overview.................................................................................................................................. 137
16.2. Register Summary - PORTMUX.............................................................................................. 138
16.3. Register Description................................................................................................................. 138
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Complete Datasheet
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